factor: rename [ ] [ ] unit-test -> { } [ ] unit-test using a refactoring tool!

[factor.git] / basis / compiler / cfg / intrinsics / simd / simd-tests.factor

diff --git a/basis/compiler/cfg/intrinsics/simd/simd-tests.factor b/basis/compiler/cfg/intrinsics/simd/simd-tests.factor
index 7f952284ab8f5f96394a8c0d48f0cbfe86249dfa..deb92f353a8b95a64b4f8f0012bb14f35e203b3c 100644 (file)
--- a/basis/compiler/cfg/intrinsics/simd/simd-tests.factor
+++ b/basis/compiler/cfg/intrinsics/simd/simd-tests.factor
@@ -118,31 +118,31 @@ M: simple-ops-cpu %gather-vector-4-reps { int-4-rep uint-4-rep float-4-rep } ;
 M: simple-ops-cpu %alien-vector-reps all-reps ;
 
 ! v+
-[ { ##add-vector } ]
+{ { ##add-vector } }
 [ simple-ops-cpu float-4-rep [ emit-simd-v+ ] test-emit ]
 unit-test
 
 ! v-
-[ { ##sub-vector } ]
+{ { ##sub-vector } }
 [ simple-ops-cpu float-4-rep [ emit-simd-v- ] test-emit ]
 unit-test
 
 ! vneg
-[ { ##load-reference ##sub-vector } ]
+{ { ##load-reference ##sub-vector } }
 [ simple-ops-cpu float-4-rep [ emit-simd-vneg ] test-emit ]
 unit-test
 
-[ { ##zero-vector ##sub-vector } ]
+{ { ##zero-vector ##sub-vector } }
 [ simple-ops-cpu int-4-rep [ emit-simd-vneg ] test-emit ]
 unit-test
 
 ! v*
-[ { ##mul-vector } ]
+{ { ##mul-vector } }
 [ simple-ops-cpu float-4-rep [ emit-simd-v* ] test-emit ]
 unit-test
 
 ! v/
-[ { ##div-vector } ]
+{ { ##div-vector } }
 [ simple-ops-cpu float-4-rep [ emit-simd-v/ ] test-emit ]
 unit-test
 
@@ -150,15 +150,15 @@ TUPLE: addsub-cpu < simple-ops-cpu ;
 M: addsub-cpu %add-sub-vector-reps { int-4-rep float-4-rep } ;
 
 ! v+-
-[ { ##add-sub-vector } ]
+{ { ##add-sub-vector } }
 [ addsub-cpu float-4-rep [ emit-simd-v+- ] test-emit ]
 unit-test
 
-[ { ##load-reference ##xor-vector ##add-vector } ]
+{ { ##load-reference ##xor-vector ##add-vector } }
 [ simple-ops-cpu float-4-rep [ emit-simd-v+- ] test-emit ]
 unit-test
 
-[ { ##load-reference ##xor-vector ##sub-vector ##add-vector } ]
+{ { ##load-reference ##xor-vector ##sub-vector ##add-vector } }
 [ simple-ops-cpu int-4-rep [ emit-simd-v+- ] test-emit ]
 unit-test
 
@@ -168,41 +168,41 @@ M: saturating-cpu %saturated-sub-vector-reps { int-4-rep } ;
 M: saturating-cpu %saturated-mul-vector-reps { int-4-rep } ;
 
 ! vs+
-[ { ##add-vector } ]
+{ { ##add-vector } }
 [ simple-ops-cpu float-4-rep [ emit-simd-vs+ ] test-emit ]
 unit-test
 
-[ { ##add-vector } ]
+{ { ##add-vector } }
 [ saturating-cpu float-4-rep [ emit-simd-vs+ ] test-emit ]
 unit-test
 
-[ { ##saturated-add-vector } ]
+{ { ##saturated-add-vector } }
 [ saturating-cpu int-4-rep [ emit-simd-vs+ ] test-emit ]
 unit-test
 
 ! vs-
-[ { ##sub-vector } ]
+{ { ##sub-vector } }
 [ simple-ops-cpu float-4-rep [ emit-simd-vs- ] test-emit ]
 unit-test
 
-[ { ##sub-vector } ]
+{ { ##sub-vector } }
 [ saturating-cpu float-4-rep [ emit-simd-vs- ] test-emit ]
 unit-test
 
-[ { ##saturated-sub-vector } ]
+{ { ##saturated-sub-vector } }
 [ saturating-cpu int-4-rep [ emit-simd-vs- ] test-emit ]
 unit-test
 
 ! vs*
-[ { ##mul-vector } ]
+{ { ##mul-vector } }
 [ simple-ops-cpu float-4-rep [ emit-simd-vs* ] test-emit ]
 unit-test
 
-[ { ##mul-vector } ]
+{ { ##mul-vector } }
 [ saturating-cpu float-4-rep [ emit-simd-vs* ] test-emit ]
 unit-test
 
-[ { ##saturated-mul-vector } ]
+{ { ##saturated-mul-vector } }
 [ saturating-cpu int-4-rep [ emit-simd-vs* ] test-emit ]
 unit-test
 
@@ -217,20 +217,20 @@ M: compare-cpu %compare-vector-reps drop signed-reps ;
 M: compare-cpu %compare-vector-ccs nip f 2array 1array f ;
 
 ! vmin
-[ { ##min-vector } ]
+{ { ##min-vector } }
 [ minmax-cpu float-4-rep [ emit-simd-vmin ] test-emit ]
 unit-test
 
-[ { ##compare-vector ##and-vector ##andn-vector ##or-vector } ]
+{ { ##compare-vector ##and-vector ##andn-vector ##or-vector } }
 [ compare-cpu float-4-rep [ emit-simd-vmin ] test-emit ]
 unit-test
 
 ! vmax
-[ { ##max-vector } ]
+{ { ##max-vector } }
 [ minmax-cpu float-4-rep [ emit-simd-vmax ] test-emit ]
 unit-test
 
-[ { ##compare-vector ##and-vector ##andn-vector ##or-vector } ]
+{ { ##compare-vector ##and-vector ##andn-vector ##or-vector } }
 [ compare-cpu float-4-rep [ emit-simd-vmax ] test-emit ]
 unit-test
 
@@ -243,50 +243,50 @@ M: horizontal-cpu %unpack-vector-head-reps signed-reps ;
 M: horizontal-cpu %unpack-vector-tail-reps signed-reps ;
 
 ! v.
-[ { ##dot-vector } ]
+{ { ##dot-vector } }
 [ dot-cpu float-4-rep [ emit-simd-v. ] test-emit ]
 unit-test
 
-[ { ##mul-vector ##horizontal-add-vector ##horizontal-add-vector ##vector>scalar } ]
+{ { ##mul-vector ##horizontal-add-vector ##horizontal-add-vector ##vector>scalar } }
 [ horizontal-cpu float-4-rep [ emit-simd-v. ] test-emit ]
 unit-test
 
-[ {
+{ {
     ##mul-vector
     ##merge-vector-head ##merge-vector-tail ##add-vector
     ##merge-vector-head ##merge-vector-tail ##add-vector
     ##vector>scalar
-} ]
+} }
 [ simple-ops-cpu float-4-rep [ emit-simd-v. ] test-emit ]
 unit-test
 
 ! vsqrt
-[ { ##sqrt-vector } ]
+{ { ##sqrt-vector } }
 [ simple-ops-cpu float-4-rep [ emit-simd-vsqrt ] test-emit ]
 unit-test
 
 ! sum
-[ { ##horizontal-add-vector ##vector>scalar } ]
+{ { ##horizontal-add-vector ##vector>scalar } }
 [ horizontal-cpu double-2-rep [ emit-simd-sum ] test-emit ]
 unit-test
 
-[ { ##horizontal-add-vector ##horizontal-add-vector ##vector>scalar } ]
+{ { ##horizontal-add-vector ##horizontal-add-vector ##vector>scalar } }
 [ horizontal-cpu float-4-rep [ emit-simd-sum ] test-emit ]
 unit-test
 
-[ {
+{ {
     ##unpack-vector-head ##unpack-vector-tail ##add-vector
     ##horizontal-add-vector ##horizontal-add-vector
     ##vector>scalar
-} ]
+} }
 [ horizontal-cpu short-8-rep [ emit-simd-sum ] test-emit ]
 unit-test
 
-[ {
+{ {
     ##unpack-vector-head ##unpack-vector-tail ##add-vector
     ##horizontal-add-vector ##horizontal-add-vector ##horizontal-add-vector
     ##vector>scalar
-} ]
+} }
 [ horizontal-cpu char-16-rep [ emit-simd-sum ] test-emit ]
 unit-test
 
@@ -294,39 +294,39 @@ TUPLE: abs-cpu < simple-ops-cpu ;
 M: abs-cpu %abs-vector-reps signed-reps ;
 
 ! vabs
-[ { } ]
+{ { } }
 [ simple-ops-cpu uint-4-rep [ emit-simd-vabs ] test-emit ]
 unit-test
 
-[ { ##abs-vector } ]
+{ { ##abs-vector } }
 [ abs-cpu float-4-rep [ emit-simd-vabs ] test-emit ]
 unit-test
 
-[ { ##load-reference ##andn-vector } ]
+{ { ##load-reference ##andn-vector } }
 [ simple-ops-cpu float-4-rep [ emit-simd-vabs ] test-emit ]
 unit-test
 
-[ { ##zero-vector ##sub-vector ##compare-vector ##and-vector ##andn-vector ##or-vector } ]
+{ { ##zero-vector ##sub-vector ##compare-vector ##and-vector ##andn-vector ##or-vector } }
 [ compare-cpu int-4-rep [ emit-simd-vabs ] test-emit ]
 unit-test
 
 ! vand
-[ { ##and-vector } ]
+{ { ##and-vector } }
 [ simple-ops-cpu float-4-rep [ emit-simd-vand ] test-emit ]
 unit-test
 
 ! vandn
-[ { ##andn-vector } ]
+{ { ##andn-vector } }
 [ simple-ops-cpu float-4-rep [ emit-simd-vandn ] test-emit ]
 unit-test
 
 ! vor
-[ { ##or-vector } ]
+{ { ##or-vector } }
 [ simple-ops-cpu float-4-rep [ emit-simd-vor ] test-emit ]
 unit-test
 
 ! vxor
-[ { ##xor-vector } ]
+{ { ##xor-vector } }
 [ simple-ops-cpu float-4-rep [ emit-simd-vxor ] test-emit ]
 unit-test
 
@@ -334,11 +334,11 @@ TUPLE: not-cpu < simple-ops-cpu ;
 M: not-cpu %not-vector-reps signed-reps ;
 
 ! vnot
-[ { ##not-vector } ]
+{ { ##not-vector } }
 [ not-cpu float-4-rep [ emit-simd-vnot ] test-emit ]
 unit-test
 
-[ { ##fill-vector ##xor-vector } ]
+{ { ##fill-vector ##xor-vector } }
 [ simple-ops-cpu float-4-rep [ emit-simd-vnot ] test-emit ]
 unit-test
 
@@ -355,30 +355,30 @@ M: horizontal-shift-cpu %horizontal-shl-vector-imm-reps signed-reps ;
 M: horizontal-shift-cpu %horizontal-shr-vector-imm-reps signed-reps ;
 
 ! vlshift
-[ { ##shl-vector-imm } ]
+{ { ##shl-vector-imm } }
 [ shift-imm-cpu 2 int-4-rep [ emit-simd-vlshift ] test-emit-literal ]
 unit-test
 
-[ { ##shl-vector } ]
+{ { ##shl-vector } }
 [ shift-cpu int-4-rep [ emit-simd-vlshift ] test-emit ]
 unit-test
 
 ! vrshift
-[ { ##shr-vector-imm } ]
+{ { ##shr-vector-imm } }
 [ shift-imm-cpu 2 int-4-rep [ emit-simd-vrshift ] test-emit-literal ]
 unit-test
 
-[ { ##shr-vector } ]
+{ { ##shr-vector } }
 [ shift-cpu int-4-rep [ emit-simd-vrshift ] test-emit ]
 unit-test
 
 ! hlshift
-[ { ##horizontal-shl-vector-imm } ]
+{ { ##horizontal-shl-vector-imm } }
 [ horizontal-shift-cpu 2 int-4-rep [ emit-simd-hlshift ] test-emit-literal ]
 unit-test
 
 ! hrshift
-[ { ##horizontal-shr-vector-imm } ]
+{ { ##horizontal-shr-vector-imm } }
 [ horizontal-shift-cpu 2 int-4-rep [ emit-simd-hrshift ] test-emit-literal ]
 unit-test
 
@@ -389,44 +389,44 @@ TUPLE: shuffle-cpu < simple-ops-cpu ;
 M: shuffle-cpu %shuffle-vector-reps signed-reps ;
 
 ! vshuffle-elements
-[ { ##load-reference ##shuffle-vector } ]
+{ { ##load-reference ##shuffle-vector } }
 [ shuffle-cpu { 0 1 2 3 } int-4-rep [ emit-simd-vshuffle-elements ] test-emit-literal ]
 unit-test
 
-[ { ##shuffle-vector-imm } ]
+{ { ##shuffle-vector-imm } }
 [ shuffle-imm-cpu { 0 1 2 3 } int-4-rep [ emit-simd-vshuffle-elements ] test-emit-literal ]
 unit-test
 
 ! vshuffle-bytes
-[ { ##shuffle-vector } ]
+{ { ##shuffle-vector } }
 [ shuffle-cpu int-4-rep [ emit-simd-vshuffle-bytes ] test-emit ]
 unit-test
 
 ! vmerge-head
-[ { ##merge-vector-head } ]
+{ { ##merge-vector-head } }
 [ simple-ops-cpu float-4-rep [ emit-simd-vmerge-head ] test-emit ]
 unit-test
 
 ! vmerge-tail
-[ { ##merge-vector-tail } ]
+{ { ##merge-vector-tail } }
 [ simple-ops-cpu float-4-rep [ emit-simd-vmerge-tail ] test-emit ]
 unit-test
 
 ! v<= etc.
-[ { ##compare-vector } ]
+{ { ##compare-vector } }
 [ compare-cpu int-4-rep [ emit-simd-v<= ] test-emit ]
 unit-test
 
-[ { ##min-vector ##compare-vector } ]
+{ { ##min-vector ##compare-vector } }
 [ minmax-cpu int-4-rep [ emit-simd-v<= ] test-emit ]
 unit-test
 
-[ { ##load-reference ##xor-vector ##xor-vector ##compare-vector } ]
+{ { ##load-reference ##xor-vector ##xor-vector ##compare-vector } }
 [ compare-cpu uint-4-rep [ emit-simd-v<= ] test-emit ]
 unit-test
 
 ! vany? etc.
-[ { ##test-vector } ]
+{ { ##test-vector } }
 [ simple-ops-cpu int-4-rep [ emit-simd-vany? ] test-emit ]
 unit-test
 
@@ -435,30 +435,30 @@ M: convert-cpu %integer>float-vector-reps { int-4-rep } ;
 M: convert-cpu %float>integer-vector-reps { float-4-rep } ;
 
 ! v>float
-[ { } ]
+{ { } }
 [ convert-cpu float-4-rep [ emit-simd-v>float ] test-emit ]
 unit-test
 
-[ { ##integer>float-vector } ]
+{ { ##integer>float-vector } }
 [ convert-cpu int-4-rep [ emit-simd-v>float ] test-emit ]
 unit-test
 
 ! v>integer
-[ { } ]
+{ { } }
 [ convert-cpu int-4-rep [ emit-simd-v>integer ] test-emit ]
 unit-test
 
-[ { ##float>integer-vector } ]
+{ { ##float>integer-vector } }
 [ convert-cpu float-4-rep [ emit-simd-v>integer ] test-emit ]
 unit-test
 
 ! vpack-signed
-[ { ##signed-pack-vector } ]
+{ { ##signed-pack-vector } }
 [ simple-ops-cpu int-4-rep [ emit-simd-vpack-signed ] test-emit ]
 unit-test
 
 ! vpack-unsigned
-[ { ##unsigned-pack-vector } ]
+{ { ##unsigned-pack-vector } }
 [ simple-ops-cpu int-4-rep [ emit-simd-vpack-unsigned ] test-emit ]
 unit-test
 
@@ -468,60 +468,60 @@ TUPLE: unpack-cpu < unpack-head-cpu ;
 M: unpack-cpu %unpack-vector-tail-reps all-reps ;
 
 ! vunpack-head
-[ { ##unpack-vector-head } ]
+{ { ##unpack-vector-head } }
 [ unpack-head-cpu int-4-rep [ emit-simd-vunpack-head ] test-emit ]
 unit-test
 
-[ { ##zero-vector ##merge-vector-head } ]
+{ { ##zero-vector ##merge-vector-head } }
 [ simple-ops-cpu uint-4-rep [ emit-simd-vunpack-head ] test-emit ]
 unit-test
 
-[ { ##merge-vector-head ##shr-vector-imm } ]
+{ { ##merge-vector-head ##shr-vector-imm } }
 [ shift-imm-cpu int-4-rep [ emit-simd-vunpack-head ] test-emit ]
 unit-test
 
-[ { ##zero-vector ##compare-vector ##merge-vector-head } ]
+{ { ##zero-vector ##compare-vector ##merge-vector-head } }
 [ compare-cpu int-4-rep [ emit-simd-vunpack-head ] test-emit ]
 unit-test
 
 ! vunpack-tail
-[ { ##unpack-vector-tail } ]
+{ { ##unpack-vector-tail } }
 [ unpack-cpu int-4-rep [ emit-simd-vunpack-tail ] test-emit ]
 unit-test
 
-[ { ##tail>head-vector ##unpack-vector-head } ]
+{ { ##tail>head-vector ##unpack-vector-head } }
 [ unpack-head-cpu int-4-rep [ emit-simd-vunpack-tail ] test-emit ]
 unit-test
 
-[ { ##zero-vector ##merge-vector-tail } ]
+{ { ##zero-vector ##merge-vector-tail } }
 [ simple-ops-cpu uint-4-rep [ emit-simd-vunpack-tail ] test-emit ]
 unit-test
 
-[ { ##merge-vector-tail ##shr-vector-imm } ]
+{ { ##merge-vector-tail ##shr-vector-imm } }
 [ shift-imm-cpu int-4-rep [ emit-simd-vunpack-tail ] test-emit ]
 unit-test
 
-[ { ##zero-vector ##compare-vector ##merge-vector-tail } ]
+{ { ##zero-vector ##compare-vector ##merge-vector-tail } }
 [ compare-cpu int-4-rep [ emit-simd-vunpack-tail ] test-emit ]
 unit-test
 
 ! with
-[ { ##scalar>vector ##shuffle-vector-imm } ]
+{ { ##scalar>vector ##shuffle-vector-imm } }
 [ shuffle-imm-cpu float-4-rep [ emit-simd-with ] test-emit ]
 unit-test
 
 ! gather-2
-[ { ##gather-vector-2 } ]
+{ { ##gather-vector-2 } }
 [ simple-ops-cpu double-2-rep [ emit-simd-gather-2 ] test-emit ]
 unit-test
 
 ! gather-4
-[ { ##gather-vector-4 } ]
+{ { ##gather-vector-4 } }
 [ simple-ops-cpu float-4-rep [ emit-simd-gather-4 ] test-emit ]
 unit-test
 
 ! select
-[ { ##shuffle-vector-imm ##vector>scalar } ]
+{ { ##shuffle-vector-imm ##vector>scalar } }
 [ shuffle-imm-cpu 1 float-4-rep [ emit-simd-select ] test-emit-literal ]
 unit-test