use radix literals

[factor.git] / basis / cpu / x86 / bootstrap.factor

diff --git a/basis/cpu/x86/bootstrap.factor b/basis/cpu/x86/bootstrap.factor
index ba5f2f8594e51526c8e85a4cef535d3cc577e98a..3c6d7ae8de60449f3cefe90b72e4eaaae5eafa89 100644 (file)
--- a/basis/cpu/x86/bootstrap.factor
+++ b/basis/cpu/x86/bootstrap.factor
@@ -3,7 +3,7 @@
 USING: bootstrap.image.private compiler.constants
 compiler.codegen.relocation compiler.units cpu.x86.assembler
 cpu.x86.assembler.operands kernel kernel.private layouts
-locals.backend make math math.private namespaces sequences
+locals locals.backend make math math.private namespaces sequences
 slots.private strings.private vocabs ;
 IN: bootstrap.x86
 
@@ -73,22 +73,9 @@ big-endian off
     ! need a parameter here.
 
     ! See the comment for M\ x86.32 stack-cleanup in cpu.x86.32
-    HEX: ffff RET f rc-absolute-2 rel-untagged
+    0xffff RET f rc-absolute-2 rel-untagged
 ] callback-stub jit-define
 
-[
-    ! Load word
-    temp0 0 MOV f rc-absolute-cell rel-literal
-    ! Bump profiling counter
-    temp0 profile-count-offset [+] 1 tag-fixnum ADD
-    ! Load word->code
-    temp0 temp0 word-code-offset [+] MOV
-    ! Compute word entry point
-    temp0 compiled-header-size ADD
-    ! Jump to entry point
-    temp0 JMP
-] jit-profiling jit-define
-
 [
     ! load literal
     temp0 0 MOV f rc-absolute-cell rel-literal
@@ -102,6 +89,47 @@ big-endian off
     0 CALL f rc-relative rel-word-pic
 ] jit-word-call jit-define
 
+! The *-signal-handler subprimitives are special-cased in vm/quotations.cpp
+! not to trigger generation of a stack frame, so they can
+! peform their own prolog/epilog preserving registers.
+
+[| |
+    jit-signal-handler-prolog :> frame-size
+    jit-save-context
+    temp0 vm-reg vm-signal-handler-addr-offset [+] MOV
+    temp0 CALL
+    frame-size jit-signal-handler-epilog
+    0 RET
+] \ signal-handler define-sub-primitive
+
+: leaf-frame-size ( -- n ) 4 bootstrap-cells ;
+
+[| |
+    jit-signal-handler-prolog :> frame-size
+    jit-save-context
+    temp0 vm-reg vm-signal-handler-addr-offset [+] MOV
+    temp0 CALL
+    frame-size jit-signal-handler-epilog
+    ! Pop the fake leaf frame along with our return address
+    leaf-frame-size bootstrap-cell - RET
+] \ leaf-signal-handler define-sub-primitive
+
+[| |
+    jit-signal-handler-prolog :> frame-size
+    temp0 vm-reg vm-signal-handler-addr-offset [+] MOV
+    temp0 CALL
+    frame-size jit-signal-handler-epilog
+    red-zone-size RET
+] \ ffi-signal-handler define-sub-primitive
+
+[| |
+    jit-signal-handler-prolog :> frame-size
+    temp0 vm-reg vm-signal-handler-addr-offset [+] MOV
+    temp0 CALL
+    frame-size jit-signal-handler-epilog
+    red-zone-size 16 bootstrap-cell - + RET
+] \ ffi-leaf-signal-handler define-sub-primitive
+
 [
     ! load boolean
     temp0 ds-reg [] MOV
@@ -198,7 +226,6 @@ big-endian off
 ] jit-execute jit-define
 
 [
-    jit-safepoint
     stack-reg stack-frame-size bootstrap-cell - ADD
 ] jit-epilog jit-define
 
@@ -210,7 +237,7 @@ big-endian off
 
 ! Load a value from a stack position
 [
-    temp1 ds-reg HEX: 7f [+] MOV f rc-absolute-1 rel-untagged
+    temp1 ds-reg 0x7f [+] MOV f rc-absolute-1 rel-untagged
 ] pic-load jit-define
 
 [ temp1 tag-mask get AND ] pic-tag jit-define
@@ -225,7 +252,7 @@ big-endian off
 ] pic-tuple jit-define
 
 [
-    temp1 HEX: 7f CMP f rc-absolute-1 rel-untagged
+    temp1 0x7f CMP f rc-absolute-1 rel-untagged
 ] pic-check-tag jit-define
 
 [ 0 JE f rc-relative rel-word ] pic-hit jit-define