use radix literals

[factor.git] / basis / cpu / x86 / bootstrap.factor

diff --git a/basis/cpu/x86/bootstrap.factor b/basis/cpu/x86/bootstrap.factor
index e0d1ef9bf77a00a3182b17c8ab9d29fe346e2d80..3c6d7ae8de60449f3cefe90b72e4eaaae5eafa89 100644 (file)
--- a/basis/cpu/x86/bootstrap.factor
+++ b/basis/cpu/x86/bootstrap.factor
@@ -73,22 +73,9 @@ big-endian off
     ! need a parameter here.
 
     ! See the comment for M\ x86.32 stack-cleanup in cpu.x86.32
-    HEX: ffff RET f rc-absolute-2 rel-untagged
+    0xffff RET f rc-absolute-2 rel-untagged
 ] callback-stub jit-define
 
-[
-    ! Load word
-    temp0 0 MOV f rc-absolute-cell rel-literal
-    ! Bump profiling counter
-    temp0 profile-count-offset [+] 1 tag-fixnum ADD
-    ! Load word->code
-    temp0 temp0 word-code-offset [+] MOV
-    ! Compute word entry point
-    temp0 compiled-header-size ADD
-    ! Jump to entry point
-    temp0 JMP
-] jit-profiling jit-define
-
 [
     ! load literal
     temp0 0 MOV f rc-absolute-cell rel-literal
@@ -102,8 +89,8 @@ big-endian off
     0 CALL f rc-relative rel-word-pic
 ] jit-word-call jit-define
 
-! The signal-handler and leaf-signal-handler subprimitives are special-cased
-! in vm/quotations.cpp not to trigger generation of a stack frame, so they can
+! The *-signal-handler subprimitives are special-cased in vm/quotations.cpp
+! not to trigger generation of a stack frame, so they can
 ! peform their own prolog/epilog preserving registers.
 
 [| |
@@ -112,8 +99,11 @@ big-endian off
     temp0 vm-reg vm-signal-handler-addr-offset [+] MOV
     temp0 CALL
     frame-size jit-signal-handler-epilog
+    0 RET
 ] \ signal-handler define-sub-primitive
 
+: leaf-frame-size ( -- n ) 4 bootstrap-cells ;
+
 [| |
     jit-signal-handler-prolog :> frame-size
     jit-save-context
@@ -121,9 +111,25 @@ big-endian off
     temp0 CALL
     frame-size jit-signal-handler-epilog
     ! Pop the fake leaf frame along with our return address
-    stack-frame-size cell - RET
+    leaf-frame-size bootstrap-cell - RET
 ] \ leaf-signal-handler define-sub-primitive
 
+[| |
+    jit-signal-handler-prolog :> frame-size
+    temp0 vm-reg vm-signal-handler-addr-offset [+] MOV
+    temp0 CALL
+    frame-size jit-signal-handler-epilog
+    red-zone-size RET
+] \ ffi-signal-handler define-sub-primitive
+
+[| |
+    jit-signal-handler-prolog :> frame-size
+    temp0 vm-reg vm-signal-handler-addr-offset [+] MOV
+    temp0 CALL
+    frame-size jit-signal-handler-epilog
+    red-zone-size 16 bootstrap-cell - + RET
+] \ ffi-leaf-signal-handler define-sub-primitive
+
 [
     ! load boolean
     temp0 ds-reg [] MOV
@@ -220,7 +226,6 @@ big-endian off
 ] jit-execute jit-define
 
 [
-    jit-safepoint
     stack-reg stack-frame-size bootstrap-cell - ADD
 ] jit-epilog jit-define
 
@@ -232,7 +237,7 @@ big-endian off
 
 ! Load a value from a stack position
 [
-    temp1 ds-reg HEX: 7f [+] MOV f rc-absolute-1 rel-untagged
+    temp1 ds-reg 0x7f [+] MOV f rc-absolute-1 rel-untagged
 ] pic-load jit-define
 
 [ temp1 tag-mask get AND ] pic-tag jit-define
@@ -247,7 +252,7 @@ big-endian off
 ] pic-tuple jit-define
 
 [
-    temp1 HEX: 7f CMP f rc-absolute-1 rel-untagged
+    temp1 0x7f CMP f rc-absolute-1 rel-untagged
 ] pic-check-tag jit-define
 
 [ 0 JE f rc-relative rel-word ] pic-hit jit-define