USING: bootstrap.image.private compiler.constants
compiler.codegen.relocation compiler.units cpu.x86.assembler
cpu.x86.assembler.operands kernel kernel.private layouts
-locals.backend make math math.private namespaces sequences
+locals locals.backend make math math.private namespaces sequences
slots.private strings.private vocabs ;
IN: bootstrap.x86
HEX: ffff RET f rc-absolute-2 rel-untagged
] callback-stub jit-define
-[
- ! Load word
- temp0 0 MOV f rc-absolute-cell rel-literal
- ! Bump profiling counter
- temp0 profile-count-offset [+] 1 tag-fixnum ADD
- ! Load word->code
- temp0 temp0 word-code-offset [+] MOV
- ! Compute word entry point
- temp0 compiled-header-size ADD
- ! Jump to entry point
- temp0 JMP
-] jit-profiling jit-define
-
[
! load literal
temp0 0 MOV f rc-absolute-cell rel-literal
0 CALL f rc-relative rel-word-pic
] jit-word-call jit-define
+! The *-signal-handler subprimitives are special-cased in vm/quotations.cpp
+! not to trigger generation of a stack frame, so they can
+! peform their own prolog/epilog preserving registers.
+
+[| |
+ jit-signal-handler-prolog :> frame-size
+ jit-save-context
+ temp0 vm-reg vm-signal-handler-addr-offset [+] MOV
+ temp0 CALL
+ frame-size jit-signal-handler-epilog
+ 0 RET
+] \ signal-handler define-sub-primitive
+
+: leaf-frame-size ( -- n ) 4 bootstrap-cells ;
+
+[| |
+ jit-signal-handler-prolog :> frame-size
+ jit-save-context
+ temp0 vm-reg vm-signal-handler-addr-offset [+] MOV
+ temp0 CALL
+ frame-size jit-signal-handler-epilog
+ ! Pop the fake leaf frame along with our return address
+ leaf-frame-size bootstrap-cell - RET
+] \ leaf-signal-handler define-sub-primitive
+
+[| |
+ jit-signal-handler-prolog :> frame-size
+ temp0 vm-reg vm-signal-handler-addr-offset [+] MOV
+ temp0 CALL
+ frame-size jit-signal-handler-epilog
+ red-zone-size RET
+] \ ffi-signal-handler define-sub-primitive
+
+[| |
+ jit-signal-handler-prolog :> frame-size
+ temp0 vm-reg vm-signal-handler-addr-offset [+] MOV
+ temp0 CALL
+ frame-size jit-signal-handler-epilog
+ red-zone-size 16 bootstrap-cell - + RET
+] \ ffi-leaf-signal-handler define-sub-primitive
+
[
! load boolean
temp0 ds-reg [] MOV
] jit-execute jit-define
[
- jit-safepoint
stack-reg stack-frame-size bootstrap-cell - ADD
] jit-epilog jit-define