call-next-method
dup [ dst>> ] [ insn-slot# ] [ insn-object ] tri
2dup live-slot dup [
- 2nip int-rep \ ##copy new-insn analyze-aliases* nip
+ 2nip any-rep \ ##copy new-insn analyze-aliases* nip
] [
drop remember-slot
] if ;
! Inputs to the final instruction need to be copied because of
! loc>vreg sync. ^^offset>slot always returns a fresh vreg,
! though.
- ds-pop ^^offset>slot i ##dispatch emit-if ;
+ ds-pop ^^offset>slot next-vreg ##dispatch emit-if ;
! #call
M: #call emit-node
V{ } clone >>predecessors
\ basic-block counter >>id ;
-TUPLE: cfg { entry basic-block } word label spill-area-size post-order ;
+TUPLE: cfg { entry basic-block } word label spill-area-size reps post-order ;
: <cfg> ( entry word label -- cfg )
cfg new
entry>> instructions>> ;
[ V{
- T{ ##load-immediate { dst V int-rep 1 } { val 8 } }
- T{ ##load-immediate { dst V int-rep 2 } { val 16 } }
- T{ ##add { dst V int-rep 3 } { src1 V int-rep 1 } { src2 V int-rep 2 } }
- T{ ##replace { src V int-rep 3 } { loc D 0 } }
+ T{ ##load-immediate { dst 1 } { val 8 } }
+ T{ ##load-immediate { dst 2 } { val 16 } }
+ T{ ##add { dst 3 } { src1 1 } { src2 2 } }
+ T{ ##replace { src 3 } { loc D 0 } }
} ] [ V{
- T{ ##load-immediate { dst V int-rep 1 } { val 8 } }
- T{ ##load-immediate { dst V int-rep 2 } { val 16 } }
- T{ ##add { dst V int-rep 3 } { src1 V int-rep 1 } { src2 V int-rep 2 } }
- T{ ##replace { src V int-rep 3 } { loc D 0 } }
+ T{ ##load-immediate { dst 1 } { val 8 } }
+ T{ ##load-immediate { dst 2 } { val 16 } }
+ T{ ##add { dst 3 } { src1 1 } { src2 2 } }
+ T{ ##replace { src 3 } { loc D 0 } }
} test-dce ] unit-test
[ V{ } ] [ V{
- T{ ##load-immediate { dst V int-rep 1 } { val 8 } }
- T{ ##load-immediate { dst V int-rep 2 } { val 16 } }
- T{ ##add { dst V int-rep 3 } { src1 V int-rep 1 } { src2 V int-rep 2 } }
+ T{ ##load-immediate { dst 1 } { val 8 } }
+ T{ ##load-immediate { dst 2 } { val 16 } }
+ T{ ##add { dst 3 } { src1 1 } { src2 2 } }
} test-dce ] unit-test
[ V{ } ] [ V{
- T{ ##load-immediate { dst V int-rep 3 } { val 8 } }
- T{ ##allot { dst V int-rep 1 } { temp V int-rep 2 } }
+ T{ ##load-immediate { dst 3 } { val 8 } }
+ T{ ##allot { dst 1 } { temp 2 } }
} test-dce ] unit-test
[ V{ } ] [ V{
- T{ ##load-immediate { dst V int-rep 3 } { val 8 } }
- T{ ##allot { dst V int-rep 1 } { temp V int-rep 2 } }
- T{ ##set-slot-imm { obj V int-rep 1 } { src V int-rep 3 } }
+ T{ ##load-immediate { dst 3 } { val 8 } }
+ T{ ##allot { dst 1 } { temp 2 } }
+ T{ ##set-slot-imm { obj 1 } { src 3 } }
} test-dce ] unit-test
[ V{
- T{ ##load-immediate { dst V int-rep 3 } { val 8 } }
- T{ ##allot { dst V int-rep 1 } { temp V int-rep 2 } }
- T{ ##set-slot-imm { obj V int-rep 1 } { src V int-rep 3 } }
- T{ ##replace { src V int-rep 1 } { loc D 0 } }
+ T{ ##load-immediate { dst 3 } { val 8 } }
+ T{ ##allot { dst 1 } { temp 2 } }
+ T{ ##set-slot-imm { obj 1 } { src 3 } }
+ T{ ##replace { src 1 } { loc D 0 } }
} ] [ V{
- T{ ##load-immediate { dst V int-rep 3 } { val 8 } }
- T{ ##allot { dst V int-rep 1 } { temp V int-rep 2 } }
- T{ ##set-slot-imm { obj V int-rep 1 } { src V int-rep 3 } }
- T{ ##replace { src V int-rep 1 } { loc D 0 } }
+ T{ ##load-immediate { dst 3 } { val 8 } }
+ T{ ##allot { dst 1 } { temp 2 } }
+ T{ ##set-slot-imm { obj 1 } { src 3 } }
+ T{ ##replace { src 1 } { loc D 0 } }
} test-dce ] unit-test
[ V{
- T{ ##allot { dst V int-rep 1 } { temp V int-rep 2 } }
- T{ ##replace { src V int-rep 1 } { loc D 0 } }
+ T{ ##allot { dst 1 } { temp 2 } }
+ T{ ##replace { src 1 } { loc D 0 } }
} ] [ V{
- T{ ##allot { dst V int-rep 1 } { temp V int-rep 2 } }
- T{ ##replace { src V int-rep 1 } { loc D 0 } }
+ T{ ##allot { dst 1 } { temp 2 } }
+ T{ ##replace { src 1 } { loc D 0 } }
} test-dce ] unit-test
[ V{
- T{ ##allot { dst V int-rep 1 } { temp V int-rep 2 } }
- T{ ##replace { src V int-rep 1 } { loc D 0 } }
- T{ ##load-immediate { dst V int-rep 3 } { val 8 } }
- T{ ##set-slot-imm { obj V int-rep 1 } { src V int-rep 3 } }
+ T{ ##allot { dst 1 } { temp 2 } }
+ T{ ##replace { src 1 } { loc D 0 } }
+ T{ ##load-immediate { dst 3 } { val 8 } }
+ T{ ##set-slot-imm { obj 1 } { src 3 } }
} ] [ V{
- T{ ##allot { dst V int-rep 1 } { temp V int-rep 2 } }
- T{ ##replace { src V int-rep 1 } { loc D 0 } }
- T{ ##load-immediate { dst V int-rep 3 } { val 8 } }
- T{ ##set-slot-imm { obj V int-rep 1 } { src V int-rep 3 } }
+ T{ ##allot { dst 1 } { temp 2 } }
+ T{ ##replace { src 1 } { loc D 0 } }
+ T{ ##load-immediate { dst 3 } { val 8 } }
+ T{ ##set-slot-imm { obj 1 } { src 3 } }
} test-dce ] unit-test
classes.tuple accessors prettyprint prettyprint.config assocs
prettyprint.backend prettyprint.custom prettyprint.sections
parser compiler.tree.builder compiler.tree.optimizer
-compiler.cfg.builder compiler.cfg.linearization
+cpu.architecture compiler.cfg.builder compiler.cfg.linearization
compiler.cfg.registers compiler.cfg.stack-frame
compiler.cfg.linear-scan compiler.cfg.two-operand
compiler.cfg.optimizer compiler.cfg.instructions
-compiler.cfg.utilities compiler.cfg.mr compiler.cfg ;
+compiler.cfg.utilities compiler.cfg.def-use
+compiler.cfg.rpo compiler.cfg.mr compiler.cfg ;
IN: compiler.cfg.debugger
GENERIC: test-cfg ( quot -- cfgs )
] each ;
! Prettyprinting
-M: vreg pprint*
- <block
- \ V pprint-word [ rep>> pprint* ] [ n>> pprint* ] bi
- block> ;
-
: pprint-loc ( loc word -- ) <block pprint-word n>> pprint* block> ;
M: ds-loc pprint* \ D pprint-loc ;
0 1 edge
1 { 2 3 } edges
2 4 edge
- 3 4 edge ;
\ No newline at end of file
+ 3 4 edge ;
+
+: fake-representations ( cfg -- )
+ post-order [
+ instructions>>
+ [ [ temp-vregs ] [ defs-vreg ] bi [ suffix ] when* ]
+ map concat
+ ] map concat
+ [ int-rep ] H{ } map>assoc representations set ;
\ No newline at end of file
compiler.cfg.registers ;
V{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##peek f V int-rep 1 D 0 }
- T{ ##peek f V int-rep 2 D 0 }
+ T{ ##peek f 0 D 0 }
+ T{ ##peek f 1 D 0 }
+ T{ ##peek f 2 D 0 }
} 1 test-bb
V{
- T{ ##replace f V int-rep 2 D 0 }
+ T{ ##replace f 2 D 0 }
} 2 test-bb
1 2 edge
V{
- T{ ##replace f V int-rep 0 D 0 }
+ T{ ##replace f 0 D 0 }
} 3 test-bb
2 3 edge
V{ } 4 test-bb
V{ } 5 test-bb
3 { 4 5 } edges
V{
- T{ ##phi f V int-rep 2 H{ { 2 V int-rep 0 } { 3 V int-rep 1 } } }
+ T{ ##phi f 2 H{ { 2 0 } { 3 1 } } }
} 6 test-bb
4 6 edge
5 6 edge
namespaces accessors sequences ;
: test-gc-checks ( -- )
+ H{ } clone representations set
cfg new 0 get >>entry
compute-predecessors
insert-gc-checks
V{
T{ ##inc-d f 3 }
- T{ ##replace f V int-rep 0 D 1 }
+ T{ ##replace f 0 D 1 }
} 0 test-bb
V{
- T{ ##box-float f V int-rep 0 V int-rep 1 }
+ T{ ##box-float f 0 1 }
} 1 test-bb
0 1 edge
! Copyright (C) 2009 Slava Pestov.
! See http://factorcode.org/license.txt for BSD license.
USING: accessors kernel sequences assocs fry
+cpu.architecture
compiler.cfg.rpo
-compiler.cfg.hats
compiler.cfg.registers
compiler.cfg.instructions
compiler.cfg.stacks.uninitialized ;
IN: compiler.cfg.gc-checks
+! Garbage collection check insertion. This pass runs after representation
+! selection, so it must keep track of representations.
+
: insert-gc-check? ( bb -- ? )
instructions>> [ ##allocation? ] any? ;
: insert-gc-check ( bb -- )
dup '[
- i i f f _ uninitialized-locs \ ##gc new-insn
+ int-rep next-vreg-rep
+ int-rep next-vreg-rep
+ f f _ uninitialized-locs \ ##gc new-insn
prefix
] change-instructions drop ;
compiler.cfg.instructions ;
IN: compiler.cfg.hats
-: i ( -- vreg ) int-rep next-vreg ; inline
-: ^^i ( -- vreg vreg ) i dup ; inline
-: ^^i1 ( obj -- vreg vreg obj ) [ ^^i ] dip ; inline
-: ^^i2 ( obj obj -- vreg vreg obj obj ) [ ^^i ] 2dip ; inline
-: ^^i3 ( obj obj obj -- vreg vreg obj obj obj ) [ ^^i ] 3dip ; inline
+: ^^r ( -- vreg vreg ) next-vreg dup ; inline
+: ^^r1 ( obj -- vreg vreg obj ) [ ^^r ] dip ; inline
+: ^^r2 ( obj obj -- vreg vreg obj obj ) [ ^^r ] 2dip ; inline
+: ^^r3 ( obj obj obj -- vreg vreg obj obj obj ) [ ^^r ] 3dip ; inline
-: d ( -- vreg ) double-float-rep next-vreg ; inline
-: ^^d ( -- vreg vreg ) d dup ; inline
-: ^^d1 ( obj -- vreg vreg obj ) [ ^^d ] dip ; inline
-: ^^d2 ( obj obj -- vreg vreg obj obj ) [ ^^d ] 2dip ; inline
-: ^^d3 ( obj obj obj -- vreg vreg obj obj obj ) [ ^^d ] 3dip ; inline
-
-: ^^load-literal ( obj -- dst ) ^^i1 ##load-literal ; inline
-: ^^copy ( src -- dst ) ^^i1 dup rep>> ##copy ; inline
-: ^^slot ( obj slot tag -- dst ) ^^i3 i ##slot ; inline
-: ^^slot-imm ( obj slot tag -- dst ) ^^i3 ##slot-imm ; inline
-: ^^set-slot ( src obj slot tag -- ) i ##set-slot ; inline
-: ^^string-nth ( obj index -- dst ) ^^i2 i ##string-nth ; inline
-: ^^add ( src1 src2 -- dst ) ^^i2 ##add ; inline
-: ^^add-imm ( src1 src2 -- dst ) ^^i2 ##add-imm ; inline
-: ^^sub ( src1 src2 -- dst ) ^^i2 ##sub ; inline
-: ^^sub-imm ( src1 src2 -- dst ) ^^i2 ##sub-imm ; inline
+: ^^load-literal ( obj -- dst ) ^^r1 ##load-literal ; inline
+: ^^copy ( src -- dst ) ^^r1 any-rep ##copy ; inline
+: ^^slot ( obj slot tag -- dst ) ^^r3 next-vreg ##slot ; inline
+: ^^slot-imm ( obj slot tag -- dst ) ^^r3 ##slot-imm ; inline
+: ^^set-slot ( src obj slot tag -- ) next-vreg ##set-slot ; inline
+: ^^string-nth ( obj index -- dst ) ^^r2 next-vreg ##string-nth ; inline
+: ^^add ( src1 src2 -- dst ) ^^r2 ##add ; inline
+: ^^add-imm ( src1 src2 -- dst ) ^^r2 ##add-imm ; inline
+: ^^sub ( src1 src2 -- dst ) ^^r2 ##sub ; inline
+: ^^sub-imm ( src1 src2 -- dst ) ^^r2 ##sub-imm ; inline
: ^^neg ( src -- dst ) [ 0 ^^load-literal ] dip ^^sub ; inline
-: ^^mul ( src1 src2 -- dst ) ^^i2 ##mul ; inline
-: ^^mul-imm ( src1 src2 -- dst ) ^^i2 ##mul-imm ; inline
-: ^^and ( input mask -- output ) ^^i2 ##and ; inline
-: ^^and-imm ( input mask -- output ) ^^i2 ##and-imm ; inline
-: ^^or ( src1 src2 -- dst ) ^^i2 ##or ; inline
-: ^^or-imm ( src1 src2 -- dst ) ^^i2 ##or-imm ; inline
-: ^^xor ( src1 src2 -- dst ) ^^i2 ##xor ; inline
-: ^^xor-imm ( src1 src2 -- dst ) ^^i2 ##xor-imm ; inline
-: ^^shl ( src1 src2 -- dst ) ^^i2 ##shl ; inline
-: ^^shl-imm ( src1 src2 -- dst ) ^^i2 ##shl-imm ; inline
-: ^^shr ( src1 src2 -- dst ) ^^i2 ##shr ; inline
-: ^^shr-imm ( src1 src2 -- dst ) ^^i2 ##shr-imm ; inline
-: ^^sar ( src1 src2 -- dst ) ^^i2 ##sar ; inline
-: ^^sar-imm ( src1 src2 -- dst ) ^^i2 ##sar-imm ; inline
-: ^^not ( src -- dst ) ^^i1 ##not ; inline
-: ^^log2 ( src -- dst ) ^^i1 ##log2 ; inline
-: ^^bignum>integer ( src -- dst ) ^^i1 i ##bignum>integer ; inline
-: ^^integer>bignum ( src -- dst ) ^^i1 i ##integer>bignum ; inline
-: ^^add-float ( src1 src2 -- dst ) ^^d2 ##add-float ; inline
-: ^^sub-float ( src1 src2 -- dst ) ^^d2 ##sub-float ; inline
-: ^^mul-float ( src1 src2 -- dst ) ^^d2 ##mul-float ; inline
-: ^^div-float ( src1 src2 -- dst ) ^^d2 ##div-float ; inline
-: ^^float>integer ( src -- dst ) ^^i1 ##float>integer ; inline
-: ^^integer>float ( src -- dst ) ^^d1 ##integer>float ; inline
-: ^^allot ( size class -- dst ) ^^i2 i ##allot ; inline
+: ^^mul ( src1 src2 -- dst ) ^^r2 ##mul ; inline
+: ^^mul-imm ( src1 src2 -- dst ) ^^r2 ##mul-imm ; inline
+: ^^and ( input mask -- output ) ^^r2 ##and ; inline
+: ^^and-imm ( input mask -- output ) ^^r2 ##and-imm ; inline
+: ^^or ( src1 src2 -- dst ) ^^r2 ##or ; inline
+: ^^or-imm ( src1 src2 -- dst ) ^^r2 ##or-imm ; inline
+: ^^xor ( src1 src2 -- dst ) ^^r2 ##xor ; inline
+: ^^xor-imm ( src1 src2 -- dst ) ^^r2 ##xor-imm ; inline
+: ^^shl ( src1 src2 -- dst ) ^^r2 ##shl ; inline
+: ^^shl-imm ( src1 src2 -- dst ) ^^r2 ##shl-imm ; inline
+: ^^shr ( src1 src2 -- dst ) ^^r2 ##shr ; inline
+: ^^shr-imm ( src1 src2 -- dst ) ^^r2 ##shr-imm ; inline
+: ^^sar ( src1 src2 -- dst ) ^^r2 ##sar ; inline
+: ^^sar-imm ( src1 src2 -- dst ) ^^r2 ##sar-imm ; inline
+: ^^not ( src -- dst ) ^^r1 ##not ; inline
+: ^^log2 ( src -- dst ) ^^r1 ##log2 ; inline
+: ^^bignum>integer ( src -- dst ) ^^r1 next-vreg ##bignum>integer ; inline
+: ^^integer>bignum ( src -- dst ) ^^r1 next-vreg ##integer>bignum ; inline
+: ^^add-float ( src1 src2 -- dst ) ^^r2 ##add-float ; inline
+: ^^sub-float ( src1 src2 -- dst ) ^^r2 ##sub-float ; inline
+: ^^mul-float ( src1 src2 -- dst ) ^^r2 ##mul-float ; inline
+: ^^div-float ( src1 src2 -- dst ) ^^r2 ##div-float ; inline
+: ^^float>integer ( src -- dst ) ^^r1 ##float>integer ; inline
+: ^^integer>float ( src -- dst ) ^^r1 ##integer>float ; inline
+: ^^allot ( size class -- dst ) ^^r2 next-vreg ##allot ; inline
: ^^allot-tuple ( n -- dst ) 2 + cells tuple ^^allot ; inline
: ^^allot-array ( n -- dst ) 2 + cells array ^^allot ; inline
: ^^allot-byte-array ( n -- dst ) 2 cells + byte-array ^^allot ; inline
-: ^^box-alien ( src -- dst ) ^^i1 i ##box-alien ; inline
-: ^^unbox-alien ( src -- dst ) ^^i1 ##unbox-alien ; inline
-: ^^unbox-c-ptr ( src class -- dst ) ^^i2 i ##unbox-c-ptr ;
-: ^^alien-unsigned-1 ( src -- dst ) ^^i1 ##alien-unsigned-1 ; inline
-: ^^alien-unsigned-2 ( src -- dst ) ^^i1 ##alien-unsigned-2 ; inline
-: ^^alien-unsigned-4 ( src -- dst ) ^^i1 ##alien-unsigned-4 ; inline
-: ^^alien-signed-1 ( src -- dst ) ^^i1 ##alien-signed-1 ; inline
-: ^^alien-signed-2 ( src -- dst ) ^^i1 ##alien-signed-2 ; inline
-: ^^alien-signed-4 ( src -- dst ) ^^i1 ##alien-signed-4 ; inline
-: ^^alien-cell ( src -- dst ) ^^i1 ##alien-cell ; inline
-: ^^alien-float ( src -- dst ) ^^d1 ##alien-float ; inline
-: ^^alien-double ( src -- dst ) ^^d1 ##alien-double ; inline
-: ^^alien-global ( symbol library -- dst ) ^^i2 ##alien-global ; inline
-: ^^compare ( src1 src2 cc -- dst ) ^^i3 i ##compare ; inline
-: ^^compare-imm ( src1 src2 cc -- dst ) ^^i3 i ##compare-imm ; inline
-: ^^compare-float ( src1 src2 cc -- dst ) ^^i3 i ##compare-float ; inline
+: ^^box-alien ( src -- dst ) ^^r1 next-vreg ##box-alien ; inline
+: ^^unbox-alien ( src -- dst ) ^^r1 ##unbox-alien ; inline
+: ^^unbox-c-ptr ( src class -- dst ) ^^r2 next-vreg ##unbox-c-ptr ;
+: ^^alien-unsigned-1 ( src -- dst ) ^^r1 ##alien-unsigned-1 ; inline
+: ^^alien-unsigned-2 ( src -- dst ) ^^r1 ##alien-unsigned-2 ; inline
+: ^^alien-unsigned-4 ( src -- dst ) ^^r1 ##alien-unsigned-4 ; inline
+: ^^alien-signed-1 ( src -- dst ) ^^r1 ##alien-signed-1 ; inline
+: ^^alien-signed-2 ( src -- dst ) ^^r1 ##alien-signed-2 ; inline
+: ^^alien-signed-4 ( src -- dst ) ^^r1 ##alien-signed-4 ; inline
+: ^^alien-cell ( src -- dst ) ^^r1 ##alien-cell ; inline
+: ^^alien-float ( src -- dst ) ^^r1 ##alien-float ; inline
+: ^^alien-double ( src -- dst ) ^^r1 ##alien-double ; inline
+: ^^alien-global ( symbol library -- dst ) ^^r2 ##alien-global ; inline
+: ^^compare ( src1 src2 cc -- dst ) ^^r3 next-vreg ##compare ; inline
+: ^^compare-imm ( src1 src2 cc -- dst ) ^^r3 next-vreg ##compare-imm ; inline
+: ^^compare-float ( src1 src2 cc -- dst ) ^^r3 next-vreg ##compare-float ; inline
: ^^offset>slot ( vreg -- vreg' ) cell 4 = [ 1 ^^shr-imm ] [ ^^copy ] if ; inline
-: ^^tag-fixnum ( src -- dst ) ^^i1 ##tag-fixnum ; inline
-: ^^untag-fixnum ( src -- dst ) ^^i1 ##untag-fixnum ; inline
-: ^^fixnum-add ( src1 src2 -- dst ) ^^i2 ##fixnum-add ; inline
-: ^^fixnum-sub ( src1 src2 -- dst ) ^^i2 ##fixnum-sub ; inline
-: ^^fixnum-mul ( src1 src2 -- dst ) ^^i2 ##fixnum-mul ; inline
-: ^^phi ( inputs -- dst ) ^^i1 ##phi ; inline
\ No newline at end of file
+: ^^tag-fixnum ( src -- dst ) ^^r1 ##tag-fixnum ; inline
+: ^^untag-fixnum ( src -- dst ) ^^r1 ##untag-fixnum ; inline
+: ^^fixnum-add ( src1 src2 -- dst ) ^^r2 ##fixnum-add ; inline
+: ^^fixnum-sub ( src1 src2 -- dst ) ^^r2 ##fixnum-sub ; inline
+: ^^fixnum-mul ( src1 src2 -- dst ) ^^r2 ##fixnum-mul ; inline
+: ^^phi ( inputs -- dst ) ^^r1 ##phi ; inline
\ No newline at end of file
! Copyright (C) 2008, 2009 Slava Pestov.
! See http://factorcode.org/license.txt for BSD license.
-USING: layouts namespaces kernel accessors sequences
-classes.algebra compiler.tree.propagation.info
-compiler.cfg.stacks compiler.cfg.hats compiler.cfg.instructions
+USING: layouts namespaces kernel accessors sequences classes.algebra
+compiler.tree.propagation.info compiler.cfg.stacks compiler.cfg.hats
+compiler.cfg.registers compiler.cfg.instructions
compiler.cfg.utilities compiler.cfg.builder.blocks ;
IN: compiler.cfg.intrinsics.slots
dup third value-info-small-fixnum?
[ (emit-set-slot-imm) ] [ (emit-set-slot) ] if
] [ first class>> immediate class<= ] bi
- [ drop ] [ i i ##write-barrier ] if
+ [ drop ] [ next-vreg next-vreg ##write-barrier ] if
] [ drop emit-primitive ] if ;
: emit-string-nth ( -- )
: emit-set-string-nth-fast ( -- )
3inputs [ ^^untag-fixnum ] [ ^^untag-fixnum ] [ ] tri*
- swap i ##set-string-nth-fast ;
+ swap next-vreg ##set-string-nth-fast ;
! See http://factorcode.org/license.txt for BSD license.
USING: accessors assocs combinators cpu.architecture fry heaps
kernel math math.order namespaces sequences vectors
-compiler.cfg compiler.cfg.linear-scan.live-intervals ;
+compiler.cfg compiler.cfg.registers
+compiler.cfg.linear-scan.live-intervals ;
IN: compiler.cfg.linear-scan.allocation.state
! Start index of current live interval. We ensure that all
SYMBOL: active-intervals
: active-intervals-for ( vreg -- seq )
- rep>> reg-class-of active-intervals get at ;
+ rep-of reg-class-of active-intervals get at ;
: add-active ( live-interval -- )
dup vreg>> active-intervals-for push ;
SYMBOL: inactive-intervals
: inactive-intervals-for ( vreg -- seq )
- rep>> reg-class-of inactive-intervals get at ;
+ rep-of reg-class-of inactive-intervals get at ;
: add-inactive ( live-interval -- )
dup vreg>> inactive-intervals-for push ;
SYMBOL: spill-slots
: assign-spill-slot ( vreg -- n )
- spill-slots get [ rep>> next-spill-slot ] cache ;
+ spill-slots get [ rep-of next-spill-slot ] cache ;
: init-allocator ( registers -- )
registers set
! A utility used by register-status and spill-status words
: free-positions ( new -- assoc )
- vreg>> rep>> reg-class-of registers get at [ 1/0. ] H{ } map>assoc ;
+ vreg>> rep-of reg-class-of registers get at [ 1/0. ] H{ } map>assoc ;
: add-use-position ( n reg assoc -- ) [ [ min ] when* ] change-at ;
init-unhandled ;
: insert-spill ( live-interval -- )
- [ reg>> ] [ vreg>> rep>> ] [ spill-to>> ] tri _spill ;
+ [ reg>> ] [ vreg>> rep-of ] [ spill-to>> ] tri _spill ;
: handle-spill ( live-interval -- )
dup spill-to>> [ insert-spill ] [ drop ] if ;
pending-interval-heap get (expire-old-intervals) ;
: insert-reload ( live-interval -- )
- [ reg>> ] [ vreg>> rep>> ] [ reload-from>> ] tri _reload ;
+ [ reg>> ] [ vreg>> rep-of ] [ reload-from>> ] tri _reload ;
: handle-reload ( live-interval -- )
dup reload-from>> [ insert-reload ] [ drop ] if ;
: trace-on-gc ( assoc -- assoc' )
! When a GC occurs, virtual registers which contain tagged data
! are traced by the GC. Outputs a sequence physical registers.
- [ drop rep>> int-rep eq? ] { } assoc-filter-as values ;
+ [ drop rep-of int-rep eq? ] { } assoc-filter-as values ;
: spill-on-gc? ( vreg reg -- ? )
- [ rep>> int-rep? not ] [ spill-slot? not ] bi* and ;
+ [ rep-of int-rep? not ] [ spill-slot? not ] bi* and ;
: spill-on-gc ( assoc -- assoc' )
! When a GC occurs, virtual registers which contain untagged data,
[
[
2dup spill-on-gc?
- [ swap [ assign-spill-slot ] [ rep>> ] bi 3array , ] [ 2drop ] if
+ [ swap [ assign-spill-slot ] [ rep-of ] bi 3array , ] [ 2drop ] if
] assoc-each
] { } make ;
compiler.cfg.rpo
compiler.cfg.linearization
compiler.cfg.debugger
+compiler.cfg.def-use
compiler.cfg.comparisons
compiler.cfg.linear-scan
compiler.cfg.linear-scan.numbering
cfg new 0 >>spill-area-size cfg set
H{ } spill-slots set
+H{
+ { 1 single-float-rep }
+ { 2 single-float-rep }
+ { 3 single-float-rep }
+} representations set
+
[
T{ live-interval
- { vreg V single-float-rep 1 }
+ { vreg 1 }
{ start 0 }
{ end 2 }
{ uses V{ 0 1 } }
{ spill-to 0 }
}
T{ live-interval
- { vreg V single-float-rep 1 }
+ { vreg 1 }
{ start 5 }
{ end 5 }
{ uses V{ 5 } }
}
] [
T{ live-interval
- { vreg V single-float-rep 1 }
+ { vreg 1 }
{ start 0 }
{ end 5 }
{ uses V{ 0 1 5 } }
[
T{ live-interval
- { vreg V single-float-rep 2 }
+ { vreg 2 }
{ start 0 }
{ end 1 }
{ uses V{ 0 } }
{ spill-to 4 }
}
T{ live-interval
- { vreg V single-float-rep 2 }
+ { vreg 2 }
{ start 1 }
{ end 5 }
{ uses V{ 1 5 } }
}
] [
T{ live-interval
- { vreg V single-float-rep 2 }
+ { vreg 2 }
{ start 0 }
{ end 5 }
{ uses V{ 0 1 5 } }
[
T{ live-interval
- { vreg V single-float-rep 3 }
+ { vreg 3 }
{ start 0 }
{ end 1 }
{ uses V{ 0 } }
{ spill-to 8 }
}
T{ live-interval
- { vreg V single-float-rep 3 }
+ { vreg 3 }
{ start 20 }
{ end 30 }
{ uses V{ 20 30 } }
}
] [
T{ live-interval
- { vreg V single-float-rep 3 }
+ { vreg 3 }
{ start 0 }
{ end 30 }
{ uses V{ 0 20 30 } }
} 10 split-for-spill
] unit-test
+H{
+ { 1 int-rep }
+ { 2 int-rep }
+ { 3 int-rep }
+} representations set
+
[
{
3
{ int-regs
V{
T{ live-interval
- { vreg V int-rep 1 }
+ { vreg 1 }
{ reg 1 }
{ start 1 }
{ end 15 }
{ uses V{ 1 3 7 10 15 } }
}
T{ live-interval
- { vreg V int-rep 2 }
+ { vreg 2 }
{ reg 2 }
{ start 3 }
{ end 8 }
{ uses V{ 3 4 8 } }
}
T{ live-interval
- { vreg V int-rep 3 }
+ { vreg 3 }
{ reg 3 }
{ start 3 }
{ end 10 }
} active-intervals set
H{ } inactive-intervals set
T{ live-interval
- { vreg V int-rep 1 }
+ { vreg 1 }
{ start 5 }
{ end 5 }
{ uses V{ 5 } }
{ int-regs
V{
T{ live-interval
- { vreg V int-rep 1 }
+ { vreg 1 }
{ reg 1 }
{ start 1 }
{ end 15 }
{ uses V{ 1 } }
}
T{ live-interval
- { vreg V int-rep 2 }
+ { vreg 2 }
{ reg 2 }
{ start 3 }
{ end 8 }
} active-intervals set
H{ } inactive-intervals set
T{ live-interval
- { vreg V int-rep 3 }
+ { vreg 3 }
{ start 5 }
{ end 5 }
{ uses V{ 5 } }
spill-status
] unit-test
+H{ { 1 int-rep } { 2 int-rep } } representations set
+
[ ] [
{
T{ live-interval
- { vreg V int-rep 1 }
+ { vreg 1 }
{ start 0 }
{ end 100 }
{ uses V{ 0 100 } }
[ ] [
{
T{ live-interval
- { vreg V int-rep 1 }
+ { vreg 1 }
{ start 0 }
{ end 10 }
{ uses V{ 0 10 } }
{ ranges V{ T{ live-range f 0 10 } } }
}
T{ live-interval
- { vreg V int-rep 2 }
+ { vreg 2 }
{ start 11 }
{ end 20 }
{ uses V{ 11 20 } }
[ ] [
{
T{ live-interval
- { vreg V int-rep 1 }
+ { vreg 1 }
{ start 0 }
{ end 100 }
{ uses V{ 0 100 } }
{ ranges V{ T{ live-range f 0 100 } } }
}
T{ live-interval
- { vreg V int-rep 2 }
+ { vreg 2 }
{ start 30 }
{ end 60 }
{ uses V{ 30 60 } }
[ ] [
{
T{ live-interval
- { vreg V int-rep 1 }
+ { vreg 1 }
{ start 0 }
{ end 100 }
{ uses V{ 0 100 } }
{ ranges V{ T{ live-range f 0 100 } } }
}
T{ live-interval
- { vreg V int-rep 2 }
+ { vreg 2 }
{ start 30 }
{ end 200 }
{ uses V{ 30 200 } }
[
{
T{ live-interval
- { vreg V int-rep 1 }
+ { vreg 1 }
{ start 0 }
{ end 100 }
{ uses V{ 0 100 } }
{ ranges V{ T{ live-range f 0 100 } } }
}
T{ live-interval
- { vreg V int-rep 2 }
+ { vreg 2 }
{ start 30 }
{ end 100 }
{ uses V{ 30 100 } }
] must-fail
! Problem with spilling intervals with no more usages after the spill location
+H{
+ { 1 int-rep }
+ { 2 int-rep }
+ { 3 int-rep }
+ { 4 int-rep }
+ { 5 int-rep }
+} representations set
[ ] [
{
T{ live-interval
- { vreg V int-rep 1 }
+ { vreg 1 }
{ start 0 }
{ end 20 }
{ uses V{ 0 10 20 } }
{ ranges V{ T{ live-range f 0 2 } T{ live-range f 10 20 } } }
}
T{ live-interval
- { vreg V int-rep 2 }
+ { vreg 2 }
{ start 0 }
{ end 20 }
{ uses V{ 0 10 20 } }
{ ranges V{ T{ live-range f 0 2 } T{ live-range f 10 20 } } }
}
T{ live-interval
- { vreg V int-rep 3 }
+ { vreg 3 }
{ start 4 }
{ end 8 }
{ uses V{ 6 } }
{ ranges V{ T{ live-range f 4 8 } } }
}
T{ live-interval
- { vreg V int-rep 4 }
+ { vreg 4 }
{ start 4 }
{ end 8 }
{ uses V{ 8 } }
! This guy will invoke the 'spill partially available' code path
T{ live-interval
- { vreg V int-rep 5 }
+ { vreg 5 }
{ start 4 }
{ end 8 }
{ uses V{ 8 } }
check-linear-scan
] unit-test
-
! Test spill-new code path
[ ] [
{
T{ live-interval
- { vreg V int-rep 1 }
+ { vreg 1 }
{ start 0 }
{ end 10 }
{ uses V{ 0 6 10 } }
! This guy will invoke the 'spill new' code path
T{ live-interval
- { vreg V int-rep 5 }
+ { vreg 5 }
{ start 2 }
{ end 8 }
{ uses V{ 8 } }
check-linear-scan
] unit-test
-SYMBOL: available
-
-SYMBOL: taken
-
-SYMBOL: max-registers
-
-SYMBOL: max-insns
-
-SYMBOL: max-uses
-
-: not-taken ( -- n )
- available get keys dup empty? [ "Oops" throw ] when
- random
- dup taken get nth 1 + max-registers get = [
- dup available get delete-at
- ] [
- dup taken get [ 1 + ] change-nth
- ] if ;
-
-: random-live-intervals ( num-intervals max-uses max-registers max-insns -- seq )
- [
- max-insns set
- max-registers set
- max-uses set
- max-insns get [ 0 ] replicate taken set
- max-insns get [ dup ] H{ } map>assoc available set
- [
- \ live-interval new
- swap int-rep swap vreg boa >>vreg
- max-uses get random 2 max [ not-taken 2 * ] replicate natural-sort
- [ >>uses ] [ first >>start ] bi
- dup uses>> last >>end
- dup [ start>> ] [ end>> ] bi <live-range> 1vector >>ranges
- ] map
- ] with-scope ;
-
-: random-test ( num-intervals max-uses max-registers max-insns -- )
- over [ random-live-intervals ] dip int-regs associate check-linear-scan ;
-
-[ ] [ 30 2 1 60 random-test ] unit-test
-[ ] [ 60 2 2 60 random-test ] unit-test
-[ ] [ 80 2 3 200 random-test ] unit-test
-[ ] [ 70 2 5 30 random-test ] unit-test
-[ ] [ 60 2 6 30 random-test ] unit-test
-[ ] [ 1 2 10 10 random-test ] unit-test
-
-[ ] [ 10 4 2 60 random-test ] unit-test
-[ ] [ 10 20 2 400 random-test ] unit-test
-[ ] [ 10 20 4 300 random-test ] unit-test
-
-USING: math.private ;
-
-[ ] [
- [ float+ float>fixnum 3 fixnum*fast ]
- test-cfg first optimize-cfg linear-scan drop
-] unit-test
-
-: fake-live-ranges ( seq -- seq' )
- [
- clone dup [ start>> ] [ end>> ] bi <live-range> 1vector >>ranges
- ] map ;
-
-[ ] [
- {
- T{ live-interval
- { vreg V int-rep 70 }
- { start 14 }
- { end 17 }
- { uses V{ 14 15 16 17 } }
- }
- T{ live-interval
- { vreg V int-rep 67 }
- { start 13 }
- { end 14 }
- { uses V{ 13 14 } }
- }
- T{ live-interval
- { vreg V int-rep 30 }
- { start 4 }
- { end 18 }
- { uses V{ 4 12 16 17 18 } }
- }
- T{ live-interval
- { vreg V int-rep 27 }
- { start 3 }
- { end 13 }
- { uses V{ 3 7 13 } }
- }
- T{ live-interval
- { vreg V int-rep 59 }
- { start 10 }
- { end 18 }
- { uses V{ 10 11 12 18 } }
- }
- T{ live-interval
- { vreg V int-rep 60 }
- { start 12 }
- { end 17 }
- { uses V{ 12 17 } }
- }
- T{ live-interval
- { vreg V int-rep 56 }
- { start 9 }
- { end 10 }
- { uses V{ 9 10 } }
- }
- } fake-live-ranges
- { { int-regs { 0 1 2 3 } } }
- allocate-registers drop
-] unit-test
-
-[ ] [
- {
- T{ live-interval
- { vreg V int-rep 3687168 }
- { start 106 }
- { end 112 }
- { uses V{ 106 112 } }
- }
- T{ live-interval
- { vreg V int-rep 3687169 }
- { start 107 }
- { end 113 }
- { uses V{ 107 113 } }
- }
- T{ live-interval
- { vreg V int-rep 3687727 }
- { start 190 }
- { end 198 }
- { uses V{ 190 195 198 } }
- }
- T{ live-interval
- { vreg V int-rep 3686445 }
- { start 43 }
- { end 44 }
- { uses V{ 43 44 } }
- }
- T{ live-interval
- { vreg V int-rep 3686195 }
- { start 5 }
- { end 11 }
- { uses V{ 5 11 } }
- }
- T{ live-interval
- { vreg V int-rep 3686449 }
- { start 44 }
- { end 56 }
- { uses V{ 44 45 45 46 56 } }
- }
- T{ live-interval
- { vreg V int-rep 3686198 }
- { start 8 }
- { end 10 }
- { uses V{ 8 9 10 } }
- }
- T{ live-interval
- { vreg V int-rep 3686454 }
- { start 46 }
- { end 49 }
- { uses V{ 46 47 47 49 } }
- }
- T{ live-interval
- { vreg V int-rep 3686196 }
- { start 6 }
- { end 12 }
- { uses V{ 6 12 } }
- }
- T{ live-interval
- { vreg V int-rep 3686197 }
- { start 7 }
- { end 14 }
- { uses V{ 7 13 14 } }
- }
- T{ live-interval
- { vreg V int-rep 3686455 }
- { start 48 }
- { end 51 }
- { uses V{ 48 51 } }
- }
- T{ live-interval
- { vreg V int-rep 3686463 }
- { start 52 }
- { end 53 }
- { uses V{ 52 53 } }
- }
- T{ live-interval
- { vreg V int-rep 3686460 }
- { start 49 }
- { end 52 }
- { uses V{ 49 50 50 52 } }
- }
- T{ live-interval
- { vreg V int-rep 3686461 }
- { start 51 }
- { end 71 }
- { uses V{ 51 52 64 68 71 } }
- }
- T{ live-interval
- { vreg V int-rep 3686464 }
- { start 53 }
- { end 54 }
- { uses V{ 53 54 } }
- }
- T{ live-interval
- { vreg V int-rep 3686465 }
- { start 54 }
- { end 76 }
- { uses V{ 54 55 55 76 } }
- }
- T{ live-interval
- { vreg V int-rep 3686470 }
- { start 58 }
- { end 60 }
- { uses V{ 58 59 59 60 } }
- }
- T{ live-interval
- { vreg V int-rep 3686469 }
- { start 56 }
- { end 58 }
- { uses V{ 56 57 57 58 } }
- }
- T{ live-interval
- { vreg V int-rep 3686473 }
- { start 60 }
- { end 62 }
- { uses V{ 60 61 61 62 } }
- }
- T{ live-interval
- { vreg V int-rep 3686479 }
- { start 62 }
- { end 64 }
- { uses V{ 62 63 63 64 } }
- }
- T{ live-interval
- { vreg V int-rep 3686735 }
- { start 78 }
- { end 96 }
- { uses V{ 78 79 79 96 } }
- }
- T{ live-interval
- { vreg V int-rep 3686482 }
- { start 64 }
- { end 65 }
- { uses V{ 64 65 } }
- }
- T{ live-interval
- { vreg V int-rep 3686483 }
- { start 65 }
- { end 66 }
- { uses V{ 65 66 } }
- }
- T{ live-interval
- { vreg V int-rep 3687510 }
- { start 168 }
- { end 171 }
- { uses V{ 168 171 } }
- }
- T{ live-interval
- { vreg V int-rep 3687511 }
- { start 169 }
- { end 176 }
- { uses V{ 169 176 } }
- }
- T{ live-interval
- { vreg V int-rep 3686484 }
- { start 66 }
- { end 75 }
- { uses V{ 66 67 67 75 } }
- }
- T{ live-interval
- { vreg V int-rep 3687509 }
- { start 162 }
- { end 163 }
- { uses V{ 162 163 } }
- }
- T{ live-interval
- { vreg V int-rep 3686491 }
- { start 68 }
- { end 69 }
- { uses V{ 68 69 } }
- }
- T{ live-interval
- { vreg V int-rep 3687512 }
- { start 170 }
- { end 178 }
- { uses V{ 170 177 178 } }
- }
- T{ live-interval
- { vreg V int-rep 3687515 }
- { start 172 }
- { end 173 }
- { uses V{ 172 173 } }
- }
- T{ live-interval
- { vreg V int-rep 3686492 }
- { start 69 }
- { end 74 }
- { uses V{ 69 70 70 74 } }
- }
- T{ live-interval
- { vreg V int-rep 3687778 }
- { start 202 }
- { end 208 }
- { uses V{ 202 208 } }
- }
- T{ live-interval
- { vreg V int-rep 3686499 }
- { start 71 }
- { end 72 }
- { uses V{ 71 72 } }
- }
- T{ live-interval
- { vreg V int-rep 3687520 }
- { start 174 }
- { end 175 }
- { uses V{ 174 175 } }
- }
- T{ live-interval
- { vreg V int-rep 3687779 }
- { start 203 }
- { end 209 }
- { uses V{ 203 209 } }
- }
- T{ live-interval
- { vreg V int-rep 3687782 }
- { start 206 }
- { end 207 }
- { uses V{ 206 207 } }
- }
- T{ live-interval
- { vreg V int-rep 3686503 }
- { start 74 }
- { end 75 }
- { uses V{ 74 75 } }
- }
- T{ live-interval
- { vreg V int-rep 3686500 }
- { start 72 }
- { end 74 }
- { uses V{ 72 73 73 74 } }
- }
- T{ live-interval
- { vreg V int-rep 3687780 }
- { start 204 }
- { end 210 }
- { uses V{ 204 210 } }
- }
- T{ live-interval
- { vreg V int-rep 3686506 }
- { start 75 }
- { end 76 }
- { uses V{ 75 76 } }
- }
- T{ live-interval
- { vreg V int-rep 3687530 }
- { start 185 }
- { end 192 }
- { uses V{ 185 192 } }
- }
- T{ live-interval
- { vreg V int-rep 3687528 }
- { start 183 }
- { end 198 }
- { uses V{ 183 198 } }
- }
- T{ live-interval
- { vreg V int-rep 3687529 }
- { start 184 }
- { end 197 }
- { uses V{ 184 197 } }
- }
- T{ live-interval
- { vreg V int-rep 3687781 }
- { start 205 }
- { end 211 }
- { uses V{ 205 211 } }
- }
- T{ live-interval
- { vreg V int-rep 3687535 }
- { start 187 }
- { end 194 }
- { uses V{ 187 194 } }
- }
- T{ live-interval
- { vreg V int-rep 3686252 }
- { start 9 }
- { end 17 }
- { uses V{ 9 15 17 } }
- }
- T{ live-interval
- { vreg V int-rep 3686509 }
- { start 76 }
- { end 90 }
- { uses V{ 76 87 90 } }
- }
- T{ live-interval
- { vreg V int-rep 3687532 }
- { start 186 }
- { end 196 }
- { uses V{ 186 196 } }
- }
- T{ live-interval
- { vreg V int-rep 3687538 }
- { start 188 }
- { end 193 }
- { uses V{ 188 193 } }
- }
- T{ live-interval
- { vreg V int-rep 3687827 }
- { start 217 }
- { end 219 }
- { uses V{ 217 219 } }
- }
- T{ live-interval
- { vreg V int-rep 3687825 }
- { start 215 }
- { end 218 }
- { uses V{ 215 216 218 } }
- }
- T{ live-interval
- { vreg V int-rep 3687831 }
- { start 218 }
- { end 219 }
- { uses V{ 218 219 } }
- }
- T{ live-interval
- { vreg V int-rep 3686296 }
- { start 16 }
- { end 18 }
- { uses V{ 16 18 } }
- }
- T{ live-interval
- { vreg V int-rep 3686302 }
- { start 29 }
- { end 31 }
- { uses V{ 29 31 } }
- }
- T{ live-interval
- { vreg V int-rep 3687838 }
- { start 231 }
- { end 232 }
- { uses V{ 231 232 } }
- }
- T{ live-interval
- { vreg V int-rep 3686300 }
- { start 26 }
- { end 27 }
- { uses V{ 26 27 } }
- }
- T{ live-interval
- { vreg V int-rep 3686301 }
- { start 27 }
- { end 30 }
- { uses V{ 27 28 28 30 } }
- }
- T{ live-interval
- { vreg V int-rep 3686306 }
- { start 37 }
- { end 93 }
- { uses V{ 37 82 93 } }
- }
- T{ live-interval
- { vreg V int-rep 3686307 }
- { start 38 }
- { end 88 }
- { uses V{ 38 85 88 } }
- }
- T{ live-interval
- { vreg V int-rep 3687837 }
- { start 222 }
- { end 223 }
- { uses V{ 222 223 } }
- }
- T{ live-interval
- { vreg V int-rep 3686305 }
- { start 36 }
- { end 81 }
- { uses V{ 36 42 77 81 } }
- }
- T{ live-interval
- { vreg V int-rep 3686310 }
- { start 39 }
- { end 95 }
- { uses V{ 39 84 95 } }
- }
- T{ live-interval
- { vreg V int-rep 3687836 }
- { start 227 }
- { end 228 }
- { uses V{ 227 228 } }
- }
- T{ live-interval
- { vreg V int-rep 3687839 }
- { start 239 }
- { end 246 }
- { uses V{ 239 245 246 } }
- }
- T{ live-interval
- { vreg V int-rep 3687841 }
- { start 240 }
- { end 241 }
- { uses V{ 240 241 } }
- }
- T{ live-interval
- { vreg V int-rep 3687845 }
- { start 241 }
- { end 243 }
- { uses V{ 241 243 } }
- }
- T{ live-interval
- { vreg V int-rep 3686315 }
- { start 40 }
- { end 94 }
- { uses V{ 40 83 94 } }
- }
- T{ live-interval
- { vreg V int-rep 3687846 }
- { start 242 }
- { end 245 }
- { uses V{ 242 245 } }
- }
- T{ live-interval
- { vreg V int-rep 3687849 }
- { start 243 }
- { end 245 }
- { uses V{ 243 244 244 245 } }
- }
- T{ live-interval
- { vreg V int-rep 3687850 }
- { start 245 }
- { end 245 }
- { uses V{ 245 } }
- }
- T{ live-interval
- { vreg V int-rep 3687851 }
- { start 246 }
- { end 246 }
- { uses V{ 246 } }
- }
- T{ live-interval
- { vreg V int-rep 3687852 }
- { start 246 }
- { end 246 }
- { uses V{ 246 } }
- }
- T{ live-interval
- { vreg V int-rep 3687853 }
- { start 247 }
- { end 248 }
- { uses V{ 247 248 } }
- }
- T{ live-interval
- { vreg V int-rep 3687854 }
- { start 249 }
- { end 250 }
- { uses V{ 249 250 } }
- }
- T{ live-interval
- { vreg V int-rep 3687855 }
- { start 258 }
- { end 259 }
- { uses V{ 258 259 } }
- }
- T{ live-interval
- { vreg V int-rep 3687080 }
- { start 280 }
- { end 285 }
- { uses V{ 280 285 } }
- }
- T{ live-interval
- { vreg V int-rep 3687081 }
- { start 281 }
- { end 286 }
- { uses V{ 281 286 } }
- }
- T{ live-interval
- { vreg V int-rep 3687082 }
- { start 282 }
- { end 287 }
- { uses V{ 282 287 } }
- }
- T{ live-interval
- { vreg V int-rep 3687083 }
- { start 283 }
- { end 288 }
- { uses V{ 283 288 } }
- }
- T{ live-interval
- { vreg V int-rep 3687085 }
- { start 284 }
- { end 299 }
- { uses V{ 284 285 286 287 288 296 299 } }
- }
- T{ live-interval
- { vreg V int-rep 3687086 }
- { start 284 }
- { end 284 }
- { uses V{ 284 } }
- }
- T{ live-interval
- { vreg V int-rep 3687087 }
- { start 289 }
- { end 293 }
- { uses V{ 289 293 } }
- }
- T{ live-interval
- { vreg V int-rep 3687088 }
- { start 290 }
- { end 294 }
- { uses V{ 290 294 } }
- }
- T{ live-interval
- { vreg V int-rep 3687089 }
- { start 291 }
- { end 297 }
- { uses V{ 291 297 } }
- }
- T{ live-interval
- { vreg V int-rep 3687090 }
- { start 292 }
- { end 298 }
- { uses V{ 292 298 } }
- }
- T{ live-interval
- { vreg V int-rep 3687363 }
- { start 118 }
- { end 119 }
- { uses V{ 118 119 } }
- }
- T{ live-interval
- { vreg V int-rep 3686599 }
- { start 77 }
- { end 89 }
- { uses V{ 77 86 89 } }
- }
- T{ live-interval
- { vreg V int-rep 3687370 }
- { start 131 }
- { end 132 }
- { uses V{ 131 132 } }
- }
- T{ live-interval
- { vreg V int-rep 3687371 }
- { start 138 }
- { end 143 }
- { uses V{ 138 143 } }
- }
- T{ live-interval
- { vreg V int-rep 3687368 }
- { start 127 }
- { end 128 }
- { uses V{ 127 128 } }
- }
- T{ live-interval
- { vreg V int-rep 3687369 }
- { start 122 }
- { end 123 }
- { uses V{ 122 123 } }
- }
- T{ live-interval
- { vreg V int-rep 3687373 }
- { start 139 }
- { end 140 }
- { uses V{ 139 140 } }
- }
- T{ live-interval
- { vreg V int-rep 3686352 }
- { start 41 }
- { end 91 }
- { uses V{ 41 43 79 91 } }
- }
- T{ live-interval
- { vreg V int-rep 3687377 }
- { start 140 }
- { end 141 }
- { uses V{ 140 141 } }
- }
- T{ live-interval
- { vreg V int-rep 3687382 }
- { start 143 }
- { end 143 }
- { uses V{ 143 } }
- }
- T{ live-interval
- { vreg V int-rep 3687383 }
- { start 144 }
- { end 161 }
- { uses V{ 144 159 161 } }
- }
- T{ live-interval
- { vreg V int-rep 3687380 }
- { start 141 }
- { end 143 }
- { uses V{ 141 142 142 143 } }
- }
- T{ live-interval
- { vreg V int-rep 3687381 }
- { start 143 }
- { end 160 }
- { uses V{ 143 160 } }
- }
- T{ live-interval
- { vreg V int-rep 3687384 }
- { start 145 }
- { end 158 }
- { uses V{ 145 158 } }
- }
- T{ live-interval
- { vreg V int-rep 3687385 }
- { start 146 }
- { end 157 }
- { uses V{ 146 157 } }
- }
- T{ live-interval
- { vreg V int-rep 3687640 }
- { start 189 }
- { end 191 }
- { uses V{ 189 191 } }
- }
- T{ live-interval
- { vreg V int-rep 3687388 }
- { start 147 }
- { end 152 }
- { uses V{ 147 152 } }
- }
- T{ live-interval
- { vreg V int-rep 3687393 }
- { start 148 }
- { end 153 }
- { uses V{ 148 153 } }
- }
- T{ live-interval
- { vreg V int-rep 3687398 }
- { start 149 }
- { end 154 }
- { uses V{ 149 154 } }
- }
- T{ live-interval
- { vreg V int-rep 3686372 }
- { start 42 }
- { end 92 }
- { uses V{ 42 45 78 80 92 } }
- }
- T{ live-interval
- { vreg V int-rep 3687140 }
- { start 293 }
- { end 295 }
- { uses V{ 293 294 294 295 } }
- }
- T{ live-interval
- { vreg V int-rep 3687403 }
- { start 150 }
- { end 155 }
- { uses V{ 150 155 } }
- }
- T{ live-interval
- { vreg V int-rep 3687150 }
- { start 304 }
- { end 306 }
- { uses V{ 304 306 } }
- }
- T{ live-interval
- { vreg V int-rep 3687151 }
- { start 305 }
- { end 307 }
- { uses V{ 305 307 } }
- }
- T{ live-interval
- { vreg V int-rep 3687408 }
- { start 151 }
- { end 156 }
- { uses V{ 151 156 } }
- }
- T{ live-interval
- { vreg V int-rep 3687153 }
- { start 312 }
- { end 313 }
- { uses V{ 312 313 } }
- }
- T{ live-interval
- { vreg V int-rep 3686902 }
- { start 267 }
- { end 272 }
- { uses V{ 267 272 } }
- }
- T{ live-interval
- { vreg V int-rep 3686903 }
- { start 268 }
- { end 273 }
- { uses V{ 268 273 } }
- }
- T{ live-interval
- { vreg V int-rep 3686900 }
- { start 265 }
- { end 270 }
- { uses V{ 265 270 } }
- }
- T{ live-interval
- { vreg V int-rep 3686901 }
- { start 266 }
- { end 271 }
- { uses V{ 266 271 } }
- }
- T{ live-interval
- { vreg V int-rep 3687162 }
- { start 100 }
- { end 119 }
- { uses V{ 100 114 117 119 } }
- }
- T{ live-interval
- { vreg V int-rep 3687163 }
- { start 101 }
- { end 118 }
- { uses V{ 101 115 116 118 } }
- }
- T{ live-interval
- { vreg V int-rep 3686904 }
- { start 269 }
- { end 274 }
- { uses V{ 269 274 } }
- }
- T{ live-interval
- { vreg V int-rep 3687166 }
- { start 104 }
- { end 110 }
- { uses V{ 104 110 } }
- }
- T{ live-interval
- { vreg V int-rep 3687167 }
- { start 105 }
- { end 111 }
- { uses V{ 105 111 } }
- }
- T{ live-interval
- { vreg V int-rep 3687164 }
- { start 102 }
- { end 108 }
- { uses V{ 102 108 } }
- }
- T{ live-interval
- { vreg V int-rep 3687165 }
- { start 103 }
- { end 109 }
- { uses V{ 103 109 } }
- }
- } fake-live-ranges
- { { int-regs { 0 1 2 3 4 } } }
- allocate-registers drop
-] unit-test
-
-! A reduction of the above
-[ ] [
- {
- T{ live-interval
- { vreg V int-rep 6449 }
- { start 44 }
- { end 56 }
- { uses V{ 44 45 46 56 } }
- }
- T{ live-interval
- { vreg V int-rep 6454 }
- { start 46 }
- { end 49 }
- { uses V{ 46 47 49 } }
- }
- T{ live-interval
- { vreg V int-rep 6455 }
- { start 48 }
- { end 51 }
- { uses V{ 48 51 } }
- }
- T{ live-interval
- { vreg V int-rep 6460 }
- { start 49 }
- { end 52 }
- { uses V{ 49 50 52 } }
- }
- T{ live-interval
- { vreg V int-rep 6461 }
- { start 51 }
- { end 71 }
- { uses V{ 51 52 64 68 71 } }
- }
- T{ live-interval
- { vreg V int-rep 6464 }
- { start 53 }
- { end 54 }
- { uses V{ 53 54 } }
- }
- T{ live-interval
- { vreg V int-rep 6470 }
- { start 58 }
- { end 60 }
- { uses V{ 58 59 60 } }
- }
- T{ live-interval
- { vreg V int-rep 6469 }
- { start 56 }
- { end 58 }
- { uses V{ 56 57 58 } }
- }
- T{ live-interval
- { vreg V int-rep 6473 }
- { start 60 }
- { end 62 }
- { uses V{ 60 61 62 } }
- }
- T{ live-interval
- { vreg V int-rep 6479 }
- { start 62 }
- { end 64 }
- { uses V{ 62 63 64 } }
- }
- T{ live-interval
- { vreg V int-rep 6735 }
- { start 78 }
- { end 96 }
- { uses V{ 78 79 96 } }
- }
- T{ live-interval
- { vreg V int-rep 6483 }
- { start 65 }
- { end 66 }
- { uses V{ 65 66 } }
- }
- T{ live-interval
- { vreg V int-rep 7845 }
- { start 91 }
- { end 93 }
- { uses V{ 91 93 } }
- }
- T{ live-interval
- { vreg V int-rep 6372 }
- { start 42 }
- { end 92 }
- { uses V{ 42 45 78 80 92 } }
- }
- } fake-live-ranges
- { { int-regs { 0 1 2 3 } } }
- allocate-registers drop
-] unit-test
-
[ f ] [
T{ live-range f 0 10 }
T{ live-range f 20 30 }
! register-status had problems because it used map>assoc where the sequence
! had multiple keys
+H{
+ { 1 int-rep }
+ { 2 int-rep }
+ { 3 int-rep }
+ { 4 int-rep }
+} representations set
+
[ { 0 10 } ] [
H{ { int-regs { 0 1 } } } registers set
H{
{ int-regs
{
T{ live-interval
- { vreg V int-rep 1 }
+ { vreg 1 }
{ start 0 }
{ end 20 }
{ reg 0 }
}
T{ live-interval
- { vreg V int-rep 2 }
+ { vreg 2 }
{ start 4 }
{ end 40 }
{ reg 0 }
{ int-regs
{
T{ live-interval
- { vreg V int-rep 3 }
+ { vreg 3 }
{ start 0 }
{ end 40 }
{ reg 1 }
} active-intervals set
T{ live-interval
- { vreg V int-rep 4 }
+ { vreg 4 }
{ start 8 }
{ end 10 }
{ ranges V{ T{ live-range f 8 10 } } }
register-status
] unit-test
+:: test-linear-scan-on-cfg ( regs -- )
+ [
+ cfg new 0 get >>entry
+ compute-predecessors
+ dup fake-representations
+ dup { { int-regs regs } } (linear-scan)
+ cfg-changed
+ flatten-cfg 1array mr.
+ ] with-scope ;
+
! Bug in live spill slots calculation
V{ T{ ##prologue } T{ ##branch } } 0 test-bb
V{
T{ ##peek
- { dst V int-rep 703128 }
+ { dst 703128 }
{ loc D 1 }
}
T{ ##peek
- { dst V int-rep 703129 }
+ { dst 703129 }
{ loc D 0 }
}
T{ ##copy
- { dst V int-rep 703134 }
- { src V int-rep 703128 }
+ { dst 703134 }
+ { src 703128 }
}
T{ ##copy
- { dst V int-rep 703135 }
- { src V int-rep 703129 }
+ { dst 703135 }
+ { src 703129 }
}
T{ ##compare-imm-branch
- { src1 V int-rep 703128 }
+ { src1 703128 }
{ src2 5 }
{ cc cc/= }
}
V{
T{ ##copy
- { dst V int-rep 703134 }
- { src V int-rep 703129 }
+ { dst 703134 }
+ { src 703129 }
}
T{ ##copy
- { dst V int-rep 703135 }
- { src V int-rep 703128 }
+ { dst 703135 }
+ { src 703128 }
}
T{ ##branch }
} 2 test-bb
V{
T{ ##replace
- { src V int-rep 703134 }
+ { src 703134 }
{ loc D 0 }
}
T{ ##replace
- { src V int-rep 703135 }
+ { src 703135 }
{ loc D 1 }
}
T{ ##epilogue }
1 { 2 3 } edges
2 3 edge
-SYMBOL: linear-scan-result
-
-:: test-linear-scan-on-cfg ( regs -- )
- [
- cfg new 0 get >>entry
- compute-predecessors
- dup { { int-regs regs } } (linear-scan)
- cfg-changed
- flatten-cfg 1array mr.
- ] with-scope ;
-
-[ ] [ { 1 2 } test-linear-scan-on-cfg ] unit-test
-
! Bug in inactive interval handling
! [ rot dup [ -rot ] when ]
V{ T{ ##prologue } T{ ##branch } } 0 test-bb
V{
T{ ##peek
- { dst V int-rep 689473 }
+ { dst 689473 }
{ loc D 2 }
}
T{ ##peek
- { dst V int-rep 689474 }
+ { dst 689474 }
{ loc D 1 }
}
T{ ##peek
- { dst V int-rep 689475 }
+ { dst 689475 }
{ loc D 0 }
}
T{ ##compare-imm-branch
- { src1 V int-rep 689473 }
+ { src1 689473 }
{ src2 5 }
{ cc cc/= }
}
V{
T{ ##copy
- { dst V int-rep 689481 }
- { src V int-rep 689475 }
+ { dst 689481 }
+ { src 689475 }
}
T{ ##copy
- { dst V int-rep 689482 }
- { src V int-rep 689474 }
+ { dst 689482 }
+ { src 689474 }
}
T{ ##copy
- { dst V int-rep 689483 }
- { src V int-rep 689473 }
+ { dst 689483 }
+ { src 689473 }
}
T{ ##branch }
} 2 test-bb
V{
T{ ##copy
- { dst V int-rep 689481 }
- { src V int-rep 689473 }
+ { dst 689481 }
+ { src 689473 }
}
T{ ##copy
- { dst V int-rep 689482 }
- { src V int-rep 689475 }
+ { dst 689482 }
+ { src 689475 }
}
T{ ##copy
- { dst V int-rep 689483 }
- { src V int-rep 689474 }
+ { dst 689483 }
+ { src 689474 }
}
T{ ##branch }
} 3 test-bb
V{
T{ ##replace
- { src V int-rep 689481 }
+ { src 689481 }
{ loc D 0 }
}
T{ ##replace
- { src V int-rep 689482 }
+ { src 689482 }
{ loc D 1 }
}
T{ ##replace
- { src V int-rep 689483 }
+ { src 689483 }
{ loc D 2 }
}
T{ ##epilogue }
V{
T{ ##peek
- { dst V int-rep 689600 }
+ { dst 689600 }
{ loc D 1 }
}
T{ ##peek
- { dst V int-rep 689601 }
+ { dst 689601 }
{ loc D 0 }
}
T{ ##compare-imm-branch
- { src1 V int-rep 689600 }
+ { src1 689600 }
{ src2 5 }
{ cc cc/= }
}
V{
T{ ##peek
- { dst V int-rep 689604 }
+ { dst 689604 }
{ loc D 2 }
}
T{ ##copy
- { dst V int-rep 689607 }
- { src V int-rep 689604 }
+ { dst 689607 }
+ { src 689604 }
}
T{ ##copy
- { dst V int-rep 689608 }
- { src V int-rep 689600 }
+ { dst 689608 }
+ { src 689600 }
}
T{ ##copy
- { dst V int-rep 689610 }
- { src V int-rep 689601 }
+ { dst 689610 }
+ { src 689601 }
}
T{ ##branch }
} 2 test-bb
V{
T{ ##peek
- { dst V int-rep 689609 }
+ { dst 689609 }
{ loc D 2 }
}
T{ ##copy
- { dst V int-rep 689607 }
- { src V int-rep 689600 }
+ { dst 689607 }
+ { src 689600 }
}
T{ ##copy
- { dst V int-rep 689608 }
- { src V int-rep 689601 }
+ { dst 689608 }
+ { src 689601 }
}
T{ ##copy
- { dst V int-rep 689610 }
- { src V int-rep 689609 }
+ { dst 689610 }
+ { src 689609 }
}
T{ ##branch }
} 3 test-bb
V{
T{ ##replace
- { src V int-rep 689607 }
+ { src 689607 }
{ loc D 0 }
}
T{ ##replace
- { src V int-rep 689608 }
+ { src 689608 }
{ loc D 1 }
}
T{ ##replace
- { src V int-rep 689610 }
+ { src 689610 }
{ loc D 2 }
}
T{ ##epilogue }
V{
T{ ##peek
- { dst V int-rep 0 }
+ { dst 0 }
{ loc D 0 }
}
T{ ##compare-imm-branch
- { src1 V int-rep 0 }
+ { src1 0 }
{ src2 5 }
{ cc cc/= }
}
V{
T{ ##peek
- { dst V int-rep 1 }
+ { dst 1 }
{ loc D 1 }
}
T{ ##copy
- { dst V int-rep 2 }
- { src V int-rep 1 }
+ { dst 2 }
+ { src 1 }
}
T{ ##branch }
} 2 test-bb
V{
T{ ##peek
- { dst V int-rep 3 }
+ { dst 3 }
{ loc D 2 }
}
T{ ##copy
- { dst V int-rep 2 }
- { src V int-rep 3 }
+ { dst 2 }
+ { src 3 }
}
T{ ##branch }
} 3 test-bb
V{
T{ ##replace
- { src V int-rep 2 }
+ { src 2 }
{ loc D 0 }
}
T{ ##return }
! Inactive interval handling: splitting active interval
! if it fits in lifetime hole only partially
-V{ T{ ##peek f V int-rep 3 R 1 } T{ ##branch } } 0 test-bb
+V{ T{ ##peek f 3 R 1 } T{ ##branch } } 0 test-bb
V{
- T{ ##peek f V int-rep 2 R 0 }
- T{ ##compare-imm-branch f V int-rep 2 5 cc= }
+ T{ ##peek f 2 R 0 }
+ T{ ##compare-imm-branch f 2 5 cc= }
} 1 test-bb
V{
- T{ ##peek f V int-rep 0 D 0 }
+ T{ ##peek f 0 D 0 }
T{ ##branch }
} 2 test-bb
V{
- T{ ##peek f V int-rep 1 D 1 }
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##replace f V int-rep 1 D 2 }
+ T{ ##peek f 1 D 1 }
+ T{ ##peek f 0 D 0 }
+ T{ ##replace f 1 D 2 }
T{ ##branch }
} 3 test-bb
V{
- T{ ##replace f V int-rep 3 R 2 }
- T{ ##replace f V int-rep 0 D 0 }
+ T{ ##replace f 3 R 2 }
+ T{ ##replace f 0 D 0 }
T{ ##return }
} 4 test-bb
! [ _copy ] [ 3 get instructions>> second class ] unit-test
! Resolve pass; make sure the spilling is done correctly
-V{ T{ ##peek f V int-rep 3 R 1 } T{ ##branch } } 0 test-bb
+V{ T{ ##peek f 3 R 1 } T{ ##branch } } 0 test-bb
V{
- T{ ##peek f V int-rep 2 R 0 }
- T{ ##compare-imm-branch f V int-rep 2 5 cc= }
+ T{ ##peek f 2 R 0 }
+ T{ ##compare-imm-branch f 2 5 cc= }
} 1 test-bb
V{
} 2 test-bb
V{
- T{ ##replace f V int-rep 3 R 1 }
- T{ ##peek f V int-rep 1 D 1 }
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##replace f V int-rep 1 D 2 }
- T{ ##replace f V int-rep 0 D 2 }
+ T{ ##replace f 3 R 1 }
+ T{ ##peek f 1 D 1 }
+ T{ ##peek f 0 D 0 }
+ T{ ##replace f 1 D 2 }
+ T{ ##replace f 0 D 2 }
T{ ##branch }
} 3 test-bb
V{
- T{ ##replace f V int-rep 3 R 2 }
+ T{ ##replace f 3 R 2 }
T{ ##return }
} 4 test-bb
} 0 test-bb
V{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##compare-imm-branch f V int-rep 0 5 cc= }
+ T{ ##peek f 0 D 0 }
+ T{ ##compare-imm-branch f 0 5 cc= }
} 1 test-bb
V{
- T{ ##replace f V int-rep 0 D 0 }
- T{ ##peek f V int-rep 1 D 0 }
- T{ ##peek f V int-rep 2 D 0 }
- T{ ##replace f V int-rep 1 D 0 }
- T{ ##replace f V int-rep 2 D 0 }
+ T{ ##replace f 0 D 0 }
+ T{ ##peek f 1 D 0 }
+ T{ ##peek f 2 D 0 }
+ T{ ##replace f 1 D 0 }
+ T{ ##replace f 2 D 0 }
T{ ##branch }
} 2 test-bb
} 3 test-bb
V{
- T{ ##peek f V int-rep 1 D 0 }
- T{ ##compare-imm-branch f V int-rep 1 5 cc= }
+ T{ ##peek f 1 D 0 }
+ T{ ##compare-imm-branch f 1 5 cc= }
} 4 test-bb
V{
- T{ ##replace f V int-rep 0 D 0 }
+ T{ ##replace f 0 D 0 }
T{ ##return }
} 5 test-bb
V{
- T{ ##replace f V int-rep 0 D 0 }
+ T{ ##replace f 0 D 0 }
T{ ##return }
} 6 test-bb
! got fixed
V{ T{ ##branch } } 0 test-bb
V{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##peek f V int-rep 1 D 1 }
- T{ ##peek f V int-rep 2 D 2 }
- T{ ##peek f V int-rep 3 D 3 }
- T{ ##peek f V int-rep 4 D 0 }
+ T{ ##peek f 0 D 0 }
+ T{ ##peek f 1 D 1 }
+ T{ ##peek f 2 D 2 }
+ T{ ##peek f 3 D 3 }
+ T{ ##peek f 4 D 0 }
T{ ##branch }
} 1 test-bb
V{ T{ ##branch } } 2 test-bb
V{ T{ ##branch } } 3 test-bb
V{
- T{ ##replace f V int-rep 1 D 1 }
- T{ ##replace f V int-rep 2 D 2 }
- T{ ##replace f V int-rep 3 D 3 }
- T{ ##replace f V int-rep 4 D 4 }
- T{ ##replace f V int-rep 0 D 0 }
+ T{ ##replace f 1 D 1 }
+ T{ ##replace f 2 D 2 }
+ T{ ##replace f 3 D 3 }
+ T{ ##replace f 4 D 4 }
+ T{ ##replace f 0 D 0 }
T{ ##branch }
} 4 test-bb
-V{ T{ ##replace f V int-rep 0 D 0 } T{ ##branch } } 5 test-bb
+V{ T{ ##replace f 0 D 0 } T{ ##branch } } 5 test-bb
V{ T{ ##return } } 6 test-bb
V{ T{ ##branch } } 7 test-bb
V{
- T{ ##replace f V int-rep 1 D 1 }
- T{ ##replace f V int-rep 2 D 2 }
- T{ ##replace f V int-rep 3 D 3 }
- T{ ##peek f V int-rep 5 D 1 }
- T{ ##peek f V int-rep 6 D 2 }
- T{ ##peek f V int-rep 7 D 3 }
- T{ ##peek f V int-rep 8 D 4 }
- T{ ##replace f V int-rep 5 D 1 }
- T{ ##replace f V int-rep 6 D 2 }
- T{ ##replace f V int-rep 7 D 3 }
- T{ ##replace f V int-rep 8 D 4 }
+ T{ ##replace f 1 D 1 }
+ T{ ##replace f 2 D 2 }
+ T{ ##replace f 3 D 3 }
+ T{ ##peek f 5 D 1 }
+ T{ ##peek f 6 D 2 }
+ T{ ##peek f 7 D 3 }
+ T{ ##peek f 8 D 4 }
+ T{ ##replace f 5 D 1 }
+ T{ ##replace f 6 D 2 }
+ T{ ##replace f 7 D 3 }
+ T{ ##replace f 8 D 4 }
T{ ##branch }
} 8 test-bb
V{
- T{ ##replace f V int-rep 1 D 1 }
- T{ ##replace f V int-rep 2 D 2 }
- T{ ##replace f V int-rep 3 D 3 }
+ T{ ##replace f 1 D 1 }
+ T{ ##replace f 2 D 2 }
+ T{ ##replace f 3 D 3 }
T{ ##return }
} 9 test-bb
! Some random bug
V{
- T{ ##peek f V int-rep 1 D 1 }
- T{ ##peek f V int-rep 2 D 2 }
- T{ ##replace f V int-rep 1 D 1 }
- T{ ##replace f V int-rep 2 D 2 }
- T{ ##peek f V int-rep 3 D 0 }
- T{ ##peek f V int-rep 0 D 0 }
+ T{ ##peek f 1 D 1 }
+ T{ ##peek f 2 D 2 }
+ T{ ##replace f 1 D 1 }
+ T{ ##replace f 2 D 2 }
+ T{ ##peek f 3 D 0 }
+ T{ ##peek f 0 D 0 }
T{ ##branch }
} 0 test-bb
V{ T{ ##branch } } 1 test-bb
V{
- T{ ##peek f V int-rep 1 D 1 }
- T{ ##peek f V int-rep 2 D 2 }
- T{ ##replace f V int-rep 3 D 3 }
- T{ ##replace f V int-rep 1 D 1 }
- T{ ##replace f V int-rep 2 D 2 }
- T{ ##replace f V int-rep 0 D 3 }
+ T{ ##peek f 1 D 1 }
+ T{ ##peek f 2 D 2 }
+ T{ ##replace f 3 D 3 }
+ T{ ##replace f 1 D 1 }
+ T{ ##replace f 2 D 2 }
+ T{ ##replace f 0 D 3 }
T{ ##branch }
} 2 test-bb
! Spilling an interval immediately after its activated;
! and the interval does not have a use at the activation point
V{
- T{ ##peek f V int-rep 1 D 1 }
- T{ ##peek f V int-rep 2 D 2 }
- T{ ##replace f V int-rep 1 D 1 }
- T{ ##replace f V int-rep 2 D 2 }
- T{ ##peek f V int-rep 0 D 0 }
+ T{ ##peek f 1 D 1 }
+ T{ ##peek f 2 D 2 }
+ T{ ##replace f 1 D 1 }
+ T{ ##replace f 2 D 2 }
+ T{ ##peek f 0 D 0 }
T{ ##branch }
} 0 test-bb
V{ T{ ##branch } } 1 test-bb
V{
- T{ ##peek f V int-rep 1 D 1 }
+ T{ ##peek f 1 D 1 }
T{ ##branch }
} 2 test-bb
V{
- T{ ##replace f V int-rep 1 D 1 }
- T{ ##peek f V int-rep 2 D 2 }
- T{ ##replace f V int-rep 2 D 2 }
+ T{ ##replace f 1 D 1 }
+ T{ ##peek f 2 D 2 }
+ T{ ##replace f 2 D 2 }
T{ ##branch }
} 3 test-bb
V{ T{ ##branch } } 4 test-bb
V{
- T{ ##replace f V int-rep 0 D 0 }
+ T{ ##replace f 0 D 0 }
T{ ##return }
} 5 test-bb
-1 get 1vector 0 get (>>successors)
-2 get 4 get V{ } 2sequence 1 get (>>successors)
-5 get 1vector 4 get (>>successors)
-3 get 1vector 2 get (>>successors)
-5 get 1vector 3 get (>>successors)
+0 1 edge
+1 { 2 4 } edges
+4 5 edge
+2 3 edge
+3 5 edge
[ ] [ { 1 2 } test-linear-scan-on-cfg ] unit-test
V{ T{ ##prologue } T{ ##branch } } 0 test-bb
V{
- T{ ##load-immediate { dst V int-rep 61 } }
- T{ ##peek { dst V int-rep 62 } { loc D 0 } }
- T{ ##peek { dst V int-rep 64 } { loc D 1 } }
+ T{ ##load-immediate { dst 61 } }
+ T{ ##peek { dst 62 } { loc D 0 } }
+ T{ ##peek { dst 64 } { loc D 1 } }
T{ ##slot-imm
- { dst V int-rep 69 }
- { obj V int-rep 64 }
+ { dst 69 }
+ { obj 64 }
{ slot 1 }
{ tag 2 }
}
- T{ ##copy { dst V int-rep 79 } { src V int-rep 69 } }
+ T{ ##copy { dst 79 } { src 69 } }
T{ ##slot-imm
- { dst V int-rep 85 }
- { obj V int-rep 62 }
+ { dst 85 }
+ { obj 62 }
{ slot 2 }
{ tag 7 }
}
T{ ##compare-branch
- { src1 V int-rep 69 }
- { src2 V int-rep 85 }
+ { src1 69 }
+ { src2 85 }
{ cc cc> }
}
} 1 test-bb
V{
T{ ##slot-imm
- { dst V int-rep 97 }
- { obj V int-rep 62 }
+ { dst 97 }
+ { obj 62 }
{ slot 2 }
{ tag 7 }
}
- T{ ##replace { src V int-rep 79 } { loc D 3 } }
- T{ ##replace { src V int-rep 62 } { loc D 4 } }
- T{ ##replace { src V int-rep 79 } { loc D 1 } }
- T{ ##replace { src V int-rep 62 } { loc D 2 } }
- T{ ##replace { src V int-rep 61 } { loc D 5 } }
- T{ ##replace { src V int-rep 62 } { loc R 0 } }
- T{ ##replace { src V int-rep 69 } { loc R 1 } }
- T{ ##replace { src V int-rep 97 } { loc D 0 } }
+ T{ ##replace { src 79 } { loc D 3 } }
+ T{ ##replace { src 62 } { loc D 4 } }
+ T{ ##replace { src 79 } { loc D 1 } }
+ T{ ##replace { src 62 } { loc D 2 } }
+ T{ ##replace { src 61 } { loc D 5 } }
+ T{ ##replace { src 62 } { loc R 0 } }
+ T{ ##replace { src 69 } { loc R 1 } }
+ T{ ##replace { src 97 } { loc D 0 } }
T{ ##call { word resize-array } }
T{ ##branch }
} 2 test-bb
V{
- T{ ##peek { dst V int-rep 98 } { loc R 0 } }
- T{ ##peek { dst V int-rep 100 } { loc D 0 } }
+ T{ ##peek { dst 98 } { loc R 0 } }
+ T{ ##peek { dst 100 } { loc D 0 } }
T{ ##set-slot-imm
- { src V int-rep 100 }
- { obj V int-rep 98 }
+ { src 100 }
+ { obj 98 }
{ slot 2 }
{ tag 7 }
}
- T{ ##peek { dst V int-rep 108 } { loc D 2 } }
- T{ ##peek { dst V int-rep 110 } { loc D 3 } }
- T{ ##peek { dst V int-rep 112 } { loc D 0 } }
- T{ ##peek { dst V int-rep 114 } { loc D 1 } }
- T{ ##peek { dst V int-rep 116 } { loc D 4 } }
- T{ ##peek { dst V int-rep 119 } { loc R 0 } }
- T{ ##copy { dst V int-rep 109 } { src V int-rep 108 } }
- T{ ##copy { dst V int-rep 111 } { src V int-rep 110 } }
- T{ ##copy { dst V int-rep 113 } { src V int-rep 112 } }
- T{ ##copy { dst V int-rep 115 } { src V int-rep 114 } }
- T{ ##copy { dst V int-rep 117 } { src V int-rep 116 } }
- T{ ##copy { dst V int-rep 120 } { src V int-rep 119 } }
+ T{ ##peek { dst 108 } { loc D 2 } }
+ T{ ##peek { dst 110 } { loc D 3 } }
+ T{ ##peek { dst 112 } { loc D 0 } }
+ T{ ##peek { dst 114 } { loc D 1 } }
+ T{ ##peek { dst 116 } { loc D 4 } }
+ T{ ##peek { dst 119 } { loc R 0 } }
+ T{ ##copy { dst 109 } { src 108 } }
+ T{ ##copy { dst 111 } { src 110 } }
+ T{ ##copy { dst 113 } { src 112 } }
+ T{ ##copy { dst 115 } { src 114 } }
+ T{ ##copy { dst 117 } { src 116 } }
+ T{ ##copy { dst 120 } { src 119 } }
T{ ##branch }
} 3 test-bb
V{
- T{ ##copy { dst V int-rep 109 } { src V int-rep 62 } }
- T{ ##copy { dst V int-rep 111 } { src V int-rep 61 } }
- T{ ##copy { dst V int-rep 113 } { src V int-rep 62 } }
- T{ ##copy { dst V int-rep 115 } { src V int-rep 79 } }
- T{ ##copy { dst V int-rep 117 } { src V int-rep 64 } }
- T{ ##copy { dst V int-rep 120 } { src V int-rep 69 } }
+ T{ ##copy { dst 109 } { src 62 } }
+ T{ ##copy { dst 111 } { src 61 } }
+ T{ ##copy { dst 113 } { src 62 } }
+ T{ ##copy { dst 115 } { src 79 } }
+ T{ ##copy { dst 117 } { src 64 } }
+ T{ ##copy { dst 120 } { src 69 } }
T{ ##branch }
} 4 test-bb
V{
- T{ ##replace { src V int-rep 120 } { loc D 0 } }
- T{ ##replace { src V int-rep 109 } { loc D 3 } }
- T{ ##replace { src V int-rep 111 } { loc D 4 } }
- T{ ##replace { src V int-rep 113 } { loc D 1 } }
- T{ ##replace { src V int-rep 115 } { loc D 2 } }
- T{ ##replace { src V int-rep 117 } { loc D 5 } }
+ T{ ##replace { src 120 } { loc D 0 } }
+ T{ ##replace { src 109 } { loc D 3 } }
+ T{ ##replace { src 111 } { loc D 4 } }
+ T{ ##replace { src 113 } { loc D 1 } }
+ T{ ##replace { src 115 } { loc D 2 } }
+ T{ ##replace { src 117 } { loc D 5 } }
T{ ##epilogue }
T{ ##return }
} 5 test-bb
V{ T{ ##prologue } T{ ##branch } } 0 test-bb
V{
- T{ ##peek { dst V int-rep 85 } { loc D 0 } }
+ T{ ##peek { dst 85 } { loc D 0 } }
T{ ##slot-imm
- { dst V int-rep 89 }
- { obj V int-rep 85 }
+ { dst 89 }
+ { obj 85 }
{ slot 3 }
{ tag 7 }
}
- T{ ##peek { dst V int-rep 91 } { loc D 1 } }
+ T{ ##peek { dst 91 } { loc D 1 } }
T{ ##slot-imm
- { dst V int-rep 96 }
- { obj V int-rep 91 }
+ { dst 96 }
+ { obj 91 }
{ slot 1 }
{ tag 2 }
}
T{ ##add
- { dst V int-rep 109 }
- { src1 V int-rep 89 }
- { src2 V int-rep 96 }
+ { dst 109 }
+ { src1 89 }
+ { src2 96 }
}
T{ ##slot-imm
- { dst V int-rep 115 }
- { obj V int-rep 85 }
+ { dst 115 }
+ { obj 85 }
{ slot 2 }
{ tag 7 }
}
T{ ##slot-imm
- { dst V int-rep 118 }
- { obj V int-rep 115 }
+ { dst 118 }
+ { obj 115 }
{ slot 1 }
{ tag 2 }
}
T{ ##compare-branch
- { src1 V int-rep 109 }
- { src2 V int-rep 118 }
+ { src1 109 }
+ { src2 118 }
{ cc cc> }
}
} 1 test-bb
V{
T{ ##add-imm
- { dst V int-rep 128 }
- { src1 V int-rep 109 }
+ { dst 128 }
+ { src1 109 }
{ src2 8 }
}
- T{ ##load-immediate { dst V int-rep 129 } { val 24 } }
+ T{ ##load-immediate { dst 129 } { val 24 } }
T{ ##inc-d { n 4 } }
T{ ##inc-r { n 1 } }
- T{ ##replace { src V int-rep 109 } { loc D 2 } }
- T{ ##replace { src V int-rep 85 } { loc D 3 } }
- T{ ##replace { src V int-rep 128 } { loc D 0 } }
- T{ ##replace { src V int-rep 85 } { loc D 1 } }
- T{ ##replace { src V int-rep 89 } { loc D 4 } }
- T{ ##replace { src V int-rep 96 } { loc R 0 } }
- T{ ##replace { src V int-rep 129 } { loc R 0 } }
+ T{ ##replace { src 109 } { loc D 2 } }
+ T{ ##replace { src 85 } { loc D 3 } }
+ T{ ##replace { src 128 } { loc D 0 } }
+ T{ ##replace { src 85 } { loc D 1 } }
+ T{ ##replace { src 89 } { loc D 4 } }
+ T{ ##replace { src 96 } { loc R 0 } }
+ T{ ##replace { src 129 } { loc R 0 } }
T{ ##branch }
} 2 test-bb
V{
- T{ ##peek { dst V int-rep 134 } { loc D 1 } }
+ T{ ##peek { dst 134 } { loc D 1 } }
T{ ##slot-imm
- { dst V int-rep 140 }
- { obj V int-rep 134 }
+ { dst 140 }
+ { obj 134 }
{ slot 2 }
{ tag 7 }
}
T{ ##inc-d { n 1 } }
T{ ##inc-r { n 1 } }
- T{ ##replace { src V int-rep 140 } { loc D 0 } }
- T{ ##replace { src V int-rep 134 } { loc R 0 } }
+ T{ ##replace { src 140 } { loc D 0 } }
+ T{ ##replace { src 134 } { loc R 0 } }
T{ ##call { word resize-array } }
T{ ##branch }
} 3 test-bb
V{
- T{ ##peek { dst V int-rep 141 } { loc R 0 } }
- T{ ##peek { dst V int-rep 143 } { loc D 0 } }
+ T{ ##peek { dst 141 } { loc R 0 } }
+ T{ ##peek { dst 143 } { loc D 0 } }
T{ ##set-slot-imm
- { src V int-rep 143 }
- { obj V int-rep 141 }
+ { src 143 }
+ { obj 141 }
{ slot 2 }
{ tag 7 }
}
T{ ##write-barrier
- { src V int-rep 141 }
- { card# V int-rep 145 }
- { table V int-rep 146 }
+ { src 141 }
+ { card# 145 }
+ { table 146 }
}
T{ ##inc-d { n -1 } }
T{ ##inc-r { n -1 } }
- T{ ##peek { dst V int-rep 156 } { loc D 2 } }
- T{ ##peek { dst V int-rep 158 } { loc D 3 } }
- T{ ##peek { dst V int-rep 160 } { loc D 0 } }
- T{ ##peek { dst V int-rep 162 } { loc D 1 } }
- T{ ##peek { dst V int-rep 164 } { loc D 4 } }
- T{ ##peek { dst V int-rep 167 } { loc R 0 } }
- T{ ##copy { dst V int-rep 157 } { src V int-rep 156 } }
- T{ ##copy { dst V int-rep 159 } { src V int-rep 158 } }
- T{ ##copy { dst V int-rep 161 } { src V int-rep 160 } }
- T{ ##copy { dst V int-rep 163 } { src V int-rep 162 } }
- T{ ##copy { dst V int-rep 165 } { src V int-rep 164 } }
- T{ ##copy { dst V int-rep 168 } { src V int-rep 167 } }
+ T{ ##peek { dst 156 } { loc D 2 } }
+ T{ ##peek { dst 158 } { loc D 3 } }
+ T{ ##peek { dst 160 } { loc D 0 } }
+ T{ ##peek { dst 162 } { loc D 1 } }
+ T{ ##peek { dst 164 } { loc D 4 } }
+ T{ ##peek { dst 167 } { loc R 0 } }
+ T{ ##copy { dst 157 } { src 156 } }
+ T{ ##copy { dst 159 } { src 158 } }
+ T{ ##copy { dst 161 } { src 160 } }
+ T{ ##copy { dst 163 } { src 162 } }
+ T{ ##copy { dst 165 } { src 164 } }
+ T{ ##copy { dst 168 } { src 167 } }
T{ ##branch }
} 4 test-bb
V{
T{ ##inc-d { n 3 } }
T{ ##inc-r { n 1 } }
- T{ ##copy { dst V int-rep 157 } { src V int-rep 85 } }
- T{ ##copy { dst V int-rep 159 } { src V int-rep 89 } }
- T{ ##copy { dst V int-rep 161 } { src V int-rep 85 } }
- T{ ##copy { dst V int-rep 163 } { src V int-rep 109 } }
- T{ ##copy { dst V int-rep 165 } { src V int-rep 91 } }
- T{ ##copy { dst V int-rep 168 } { src V int-rep 96 } }
+ T{ ##copy { dst 157 } { src 85 } }
+ T{ ##copy { dst 159 } { src 89 } }
+ T{ ##copy { dst 161 } { src 85 } }
+ T{ ##copy { dst 163 } { src 109 } }
+ T{ ##copy { dst 165 } { src 91 } }
+ T{ ##copy { dst 168 } { src 96 } }
T{ ##branch }
} 5 test-bb
V{
T{ ##set-slot-imm
- { src V int-rep 163 }
- { obj V int-rep 161 }
+ { src 163 }
+ { obj 161 }
{ slot 3 }
{ tag 7 }
}
T{ ##inc-d { n 1 } }
T{ ##inc-r { n -1 } }
- T{ ##replace { src V int-rep 168 } { loc D 0 } }
- T{ ##replace { src V int-rep 157 } { loc D 3 } }
- T{ ##replace { src V int-rep 159 } { loc D 4 } }
- T{ ##replace { src V int-rep 161 } { loc D 1 } }
- T{ ##replace { src V int-rep 163 } { loc D 2 } }
- T{ ##replace { src V int-rep 165 } { loc D 5 } }
+ T{ ##replace { src 168 } { loc D 0 } }
+ T{ ##replace { src 157 } { loc D 3 } }
+ T{ ##replace { src 159 } { loc D 4 } }
+ T{ ##replace { src 161 } { loc D 1 } }
+ T{ ##replace { src 163 } { loc D 2 } }
+ T{ ##replace { src 165 } { loc D 5 } }
T{ ##epilogue }
T{ ##return }
} 6 test-bb
V{ T{ ##branch } } 0 test-bb
V{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##compare-imm-branch f V int-rep 0 5 cc= }
+ T{ ##peek f 0 D 0 }
+ T{ ##compare-imm-branch f 0 5 cc= }
} 1 test-bb
V{ T{ ##branch } } 2 test-bb
V{
- T{ ##peek f V int-rep 1 D 0 }
- T{ ##peek f V int-rep 2 D 0 }
- T{ ##replace f V int-rep 1 D 0 }
- T{ ##replace f V int-rep 2 D 0 }
+ T{ ##peek f 1 D 0 }
+ T{ ##peek f 2 D 0 }
+ T{ ##replace f 1 D 0 }
+ T{ ##replace f 2 D 0 }
T{ ##branch }
} 3 test-bb
V{
- T{ ##replace f V int-rep 0 D 0 }
+ T{ ##replace f 0 D 0 }
T{ ##return }
} 4 test-bb
V{ T{ ##branch } } 0 test-bb
V{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##compare-imm-branch f V int-rep 0 5 cc= }
+ T{ ##peek f 0 D 0 }
+ T{ ##compare-imm-branch f 0 5 cc= }
} 1 test-bb
V{
- T{ ##peek f V int-rep 1 D 0 }
- T{ ##peek f V int-rep 2 D 0 }
- T{ ##replace f V int-rep 1 D 0 }
- T{ ##replace f V int-rep 2 D 0 }
- T{ ##replace f V int-rep 0 D 0 }
+ T{ ##peek f 1 D 0 }
+ T{ ##peek f 2 D 0 }
+ T{ ##replace f 1 D 0 }
+ T{ ##replace f 2 D 0 }
+ T{ ##replace f 0 D 0 }
T{ ##branch }
} 2 test-bb
} 3 test-bb
V{
- T{ ##replace f V int-rep 0 D 0 }
+ T{ ##replace f 0 D 0 }
T{ ##return }
} 4 test-bb
[ 0 ] [ 4 get instructions>> [ _reload? ] count ] unit-test
-! GC check tests
-
-! Spill slot liveness was computed incorrectly, leading to a FEP
-! early in bootstrap on x86-32
-[ t ] [
- [
- T{ basic-block
- { id 12345 }
- { instructions
- V{
- T{ ##gc f V int-rep 6 V int-rep 7 }
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##peek f V int-rep 1 D 1 }
- T{ ##peek f V int-rep 2 D 2 }
- T{ ##peek f V int-rep 3 D 3 }
- T{ ##peek f V int-rep 4 D 4 }
- T{ ##peek f V int-rep 5 D 5 }
- T{ ##replace f V int-rep 0 D 1 }
- T{ ##replace f V int-rep 1 D 2 }
- T{ ##replace f V int-rep 2 D 3 }
- T{ ##replace f V int-rep 3 D 4 }
- T{ ##replace f V int-rep 4 D 5 }
- T{ ##replace f V int-rep 5 D 0 }
- }
- }
- } cfg new over >>entry
- { { int-regs V{ 0 1 2 3 } } } (linear-scan)
- instructions>> first
- tagged-values>> assoc-empty?
- ] with-scope
-] unit-test
-
V{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##peek f V int-rep 1 D 1 }
- T{ ##replace f V int-rep 1 D 1 }
+ T{ ##peek f 0 D 0 }
+ T{ ##peek f 1 D 1 }
+ T{ ##replace f 1 D 1 }
T{ ##branch }
} 0 test-bb
V{
- T{ ##gc f V int-rep 2 V int-rep 3 }
+ T{ ##gc f 2 3 }
T{ ##branch }
} 1 test-bb
V{
- T{ ##replace f V int-rep 0 D 0 }
+ T{ ##replace f 0 D 0 }
T{ ##return }
} 2 test-bb
[ { 3 } ] [ 1 get instructions>> first tagged-values>> ] unit-test
-
-
V{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##peek f V int-rep 1 D 1 }
- T{ ##compare-imm-branch f V int-rep 1 5 cc= }
+ T{ ##peek f 0 D 0 }
+ T{ ##peek f 1 D 1 }
+ T{ ##compare-imm-branch f 1 5 cc= }
} 0 test-bb
V{
- T{ ##gc f V int-rep 2 V int-rep 3 }
- T{ ##replace f V int-rep 0 D 0 }
+ T{ ##gc f 2 3 }
+ T{ ##replace f 0 D 0 }
T{ ##return }
} 1 test-bb
compiler.cfg
compiler.cfg.rpo
compiler.cfg.liveness
+compiler.cfg.registers
compiler.cfg.instructions
compiler.cfg.linear-scan.numbering
compiler.cfg.linear-scan.live-intervals
make math sequences hashtables
compiler.cfg.rpo
compiler.cfg.liveness
+compiler.cfg.registers
compiler.cfg.utilities
compiler.cfg.instructions
compiler.cfg.parallel-copy
:: resolve-value-data-flow ( bb to vreg -- )
vreg bb vreg-at-end
vreg to vreg-at-start
- 2dup = [ 2drop ] [ vreg rep>> add-mapping ] if ;
+ 2dup = [ 2drop ] [ vreg rep-of add-mapping ] if ;
: compute-mappings ( bb to -- mappings )
dup live-in dup assoc-empty? [ 3drop f ] [
! Sanity check...
V{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##replace f V int-rep 0 D 0 }
- T{ ##replace f V int-rep 1 D 1 }
- T{ ##peek f V int-rep 1 D 1 }
+ T{ ##peek f 0 D 0 }
+ T{ ##replace f 0 D 0 }
+ T{ ##replace f 1 D 1 }
+ T{ ##peek f 1 D 1 }
T{ ##branch }
} 1 test-bb
V{
- T{ ##replace f V int-rep 2 D 0 }
+ T{ ##replace f 2 D 0 }
T{ ##branch }
} 2 test-bb
V{
- T{ ##replace f V int-rep 3 D 0 }
+ T{ ##replace f 3 D 0 }
T{ ##return }
} 3 test-bb
[
H{
- { V int-rep 1 V int-rep 1 }
- { V int-rep 2 V int-rep 2 }
- { V int-rep 3 V int-rep 3 }
+ { 1 1 }
+ { 2 2 }
+ { 3 3 }
}
]
[ 1 get live-in ]
! Tricky case; defs must be killed before uses
V{
- T{ ##peek f V int-rep 0 D 0 }
+ T{ ##peek f 0 D 0 }
T{ ##branch }
} 1 test-bb
V{
- T{ ##add-imm f V int-rep 0 V int-rep 0 10 }
+ T{ ##add-imm f 0 0 10 }
T{ ##return }
} 2 test-bb
test-liveness
-[ H{ { V int-rep 0 V int-rep 0 } } ] [ 2 get live-in ] unit-test
\ No newline at end of file
+[ H{ { 0 0 } } ] [ 2 get live-in ] unit-test
\ No newline at end of file
! Copyright (C) 2009 Slava Pestov.
! See http://factorcode.org/license.txt for BSD license.
-USING: kernel namespaces compiler.cfg compiler.cfg.linearization
-compiler.cfg.gc-checks compiler.cfg.linear-scan
-compiler.cfg.build-stack-frame ;
+USING: kernel namespaces accessors compiler.cfg compiler.cfg.registers
+compiler.cfg.linearization compiler.cfg.gc-checks
+compiler.cfg.linear-scan compiler.cfg.build-stack-frame ;
IN: compiler.cfg.mr
: build-mr ( cfg -- mr )
dup cfg [
+ cfg get reps>> representations set
insert-gc-checks
linear-scan
flatten-cfg
[
{
- T{ ##copy f V int-rep 4 V int-rep 2 int-rep }
- T{ ##copy f V int-rep 2 V int-rep 1 int-rep }
- T{ ##copy f V int-rep 1 V int-rep 4 int-rep }
+ T{ ##copy f 4 2 any-rep }
+ T{ ##copy f 2 1 any-rep }
+ T{ ##copy f 1 4 any-rep }
}
] [
H{
- { V int-rep 1 V int-rep 2 }
- { V int-rep 2 V int-rep 1 }
+ { 1 2 }
+ { 2 1 }
} test-parallel-copy
] unit-test
[
{
- T{ ##copy f V int-rep 1 V int-rep 2 int-rep }
- T{ ##copy f V int-rep 3 V int-rep 4 int-rep }
+ T{ ##copy f 1 2 any-rep }
+ T{ ##copy f 3 4 any-rep }
}
] [
H{
- { V int-rep 1 V int-rep 2 }
- { V int-rep 3 V int-rep 4 }
+ { 1 2 }
+ { 3 4 }
} test-parallel-copy
] unit-test
[
{
- T{ ##copy f V int-rep 1 V int-rep 3 int-rep }
- T{ ##copy f V int-rep 2 V int-rep 1 int-rep }
+ T{ ##copy f 1 3 any-rep }
+ T{ ##copy f 2 1 any-rep }
}
] [
H{
- { V int-rep 1 V int-rep 3 }
- { V int-rep 2 V int-rep 3 }
+ { 1 3 }
+ { 2 3 }
} test-parallel-copy
] unit-test
[
{
- T{ ##copy f V int-rep 4 V int-rep 3 int-rep }
- T{ ##copy f V int-rep 3 V int-rep 2 int-rep }
- T{ ##copy f V int-rep 2 V int-rep 1 int-rep }
- T{ ##copy f V int-rep 1 V int-rep 4 int-rep }
+ T{ ##copy f 4 3 any-rep }
+ T{ ##copy f 3 2 any-rep }
+ T{ ##copy f 2 1 any-rep }
+ T{ ##copy f 1 4 any-rep }
}
] [
{
- { V int-rep 2 V int-rep 1 }
- { V int-rep 3 V int-rep 2 }
- { V int-rep 1 V int-rep 3 }
- { V int-rep 4 V int-rep 3 }
+ { 2 1 }
+ { 3 2 }
+ { 1 3 }
+ { 4 3 }
} test-parallel-copy
] unit-test
\ No newline at end of file
! Copyright (C) 2009 Slava Pestov.
! See http://factorcode.org/license.txt for BSD license.
-USING: assocs cpu.architecture compiler.cfg.hats
+USING: assocs cpu.architecture compiler.cfg.registers
compiler.cfg.instructions deques dlists fry kernel locals namespaces
sequences hashtables ;
IN: compiler.cfg.parallel-copy
] slurp-deque
] with-scope ; inline
-: parallel-copy ( mapping -- ) i [ int-rep ##copy ] parallel-mapping ;
\ No newline at end of file
+: parallel-copy ( mapping -- )
+ next-vreg [ any-rep ##copy ] parallel-mapping ;
\ No newline at end of file
! Copyright (C) 2008, 2009 Slava Pestov.
! See http://factorcode.org/license.txt for BSD license.
-USING: accessors namespaces kernel arrays parser math math.order ;
+USING: accessors namespaces kernel parser assocs ;
IN: compiler.cfg.registers
-! Virtual registers, used by CFG and machine IRs
-TUPLE: vreg rep { n fixnum read-only } ;
+! Virtual registers, used by CFG and machine IRs, are just integers
+SYMBOL: vreg-counter
-M: vreg equal? over vreg? [ [ n>> ] bi@ eq? ] [ 2drop f ] if ;
+: next-vreg ( -- vreg )
+ ! This word cannot be called AFTER representation selection has run;
+ ! use next-vreg-rep in that case
+ \ vreg-counter counter ;
-M: vreg hashcode* nip n>> ;
+SYMBOL: representations
-SYMBOL: vreg-counter
+ERROR: bad-vreg vreg ;
+
+: rep-of ( vreg -- rep )
+ ! This word cannot be called BEFORE representation selection has run;
+ ! use any-rep for ##copy instructions and so on
+ representations get ?at [ bad-vreg ] unless ;
+
+: set-rep-of ( rep vreg -- )
+ representations get set-at ;
-: next-vreg ( rep -- vreg ) \ vreg-counter counter vreg boa ;
+: next-vreg-rep ( rep -- vreg )
+ ! This word cannot be called BEFORE representation selection has run;
+ ! use next-vreg in that case
+ next-vreg [ set-rep-of ] keep ;
! Stack locations -- 'n' is an index starting from the top of the stack
! going down. So 0 is the top of the stack, 1 is what would be the top
TUPLE: rs-loc < loc ;
C: <rs-loc> rs-loc
-SYNTAX: V scan-word scan-word vreg boa parsed ;
SYNTAX: D scan-word <ds-loc> parsed ;
SYNTAX: R scan-word <rs-loc> parsed ;
: rename-value ( vreg -- vreg' )
renamings get ?at drop ;
-: fresh-value ( vreg -- vreg' )
- rep>> next-vreg ;
-
-RENAMING: rename [ rename-value ] [ rename-value ] [ fresh-value ]
+RENAMING: rename [ rename-value ] [ rename-value ] [ drop next-vreg ]
! Copyright (C) 2009 Slava Pestov.
! See http://factorcode.org/license.txt for BSD license.
USING: kernel accessors sequences arrays fry namespaces
-cpu.architecture compiler.cfg compiler.cfg.rpo
+cpu.architecture compiler.cfg.utilities compiler.cfg compiler.cfg.rpo
compiler.cfg.instructions compiler.cfg.def-use ;
IN: compiler.cfg.representations.preferred
: with-vreg-reps ( cfg vreg-quot: ( vreg rep -- ) -- )
'[
[ basic-block set ] [
- instructions>> [
- dup ##phi? [ drop ] [
- _ [ each-def-rep ] [ each-use-rep ] [ each-temp-rep ] 2tri
- ] if
- ] each
+ [
+ _
+ [ each-def-rep ]
+ [ each-use-rep ]
+ [ each-temp-rep ] 2tri
+ ] each-non-phi
] bi
] each-basic-block ; inline
[ { double-float-rep double-float-rep } ] [
T{ ##add-float
- { dst V double-float-rep 5 }
- { src1 V double-float-rep 3 }
- { src2 V double-float-rep 4 }
+ { dst 5 }
+ { src1 3 }
+ { src2 4 }
} uses-vreg-reps
] unit-test
[ double-float-rep ] [
T{ ##alien-double
- { dst V double-float-rep 5 }
- { src V int-rep 3 }
+ { dst 5 }
+ { src 3 }
} defs-vreg-rep
] unit-test
\ No newline at end of file
! Copyright (C) 2009 Slava Pestov
! See http://factorcode.org/license.txt for BSD license.
USING: kernel fry accessors sequences assocs sets namespaces
-arrays combinators make locals cpu.architecture compiler.utilities
+arrays combinators make locals deques dlists
+cpu.architecture compiler.utilities
compiler.cfg
compiler.cfg.rpo
-compiler.cfg.hats
compiler.cfg.registers
compiler.cfg.instructions
compiler.cfg.def-use
compiler.cfg.representations.preferred ;
IN: compiler.cfg.representations
-! Virtual register representation selection.
-! Still needs a loop nesting heuristic
+! Virtual register representation selection. Predecessors and loops
+! must be computed first.
+
+<PRIVATE
! For every vreg, compute possible representations.
SYMBOL: possibilities
H{ } clone [ '[ swap _ conjoin-at ] with-vreg-reps ] keep
[ keys ] assoc-map possibilities set ;
+! Compute vregs which must remain tagged for their lifetime.
+SYMBOL: always-boxed
+
+:: (compute-always-boxed) ( vreg rep assoc -- )
+ rep int-rep eq? [
+ int-rep vreg assoc set-at
+ ] when ;
+
+: compute-always-boxed ( cfg -- assoc )
+ H{ } clone [
+ '[
+ [
+ [ _ (compute-always-boxed) ] each-def-rep
+ ] each-non-phi
+ ] each-basic-block
+ ] keep ;
+
! For every vreg, compute the cost of keeping it in every possible
! representation.
[ '[ _ _ maybe-increase-cost ] ]
2bi each ;
-! For every vreg, compute preferred representation, that minimizes costs.
-SYMBOL: preferred
+: compute-costs ( cfg -- costs )
+ init-costs [ representation-cost ] with-vreg-reps costs get ;
-: minimize-costs ( -- )
- costs get [ >alist alist-min first ] assoc-map preferred set ;
+! For every vreg, compute preferred representation, that minimizes costs.
+: minimize-costs ( costs -- representations )
+ [ >alist alist-min first ] assoc-map ;
-: compute-costs ( cfg -- )
- init-costs
- [ representation-cost ] with-vreg-reps
- minimize-costs ;
+: compute-representations ( cfg -- )
+ [ compute-costs minimize-costs ]
+ [ compute-always-boxed ]
+ bi assoc-union
+ representations set ;
! Insert conversions. This introduces new temporaries, so we need
! to rename opearands too.
{ { int-rep int-rep } [ int-rep ##copy ] }
{ { double-float-rep double-float-rep } [ double-float-rep ##copy ] }
{ { double-float-rep int-rep } [ ##unbox-float ] }
- { { int-rep double-float-rep } [ i ##box-float ] }
+ { { int-rep double-float-rep } [ int-rep next-vreg-rep ##box-float ] }
} case ;
:: emit-def-conversion ( dst preferred required -- new-dst' )
! but the register has preferred representation 'preferred', then
! we rename the instruction's definition to a new register, which
! becomes the input of a conversion instruction.
- dst required next-vreg [ preferred required emit-conversion ] keep ;
+ dst required next-vreg-rep [ preferred required emit-conversion ] keep ;
:: emit-use-conversion ( src preferred required -- new-src' )
! If an instruction uses a register with representation 'required',
! but the register has preferred representation 'preferred', then
! we rename the instruction's input to a new register, which
! becomes the output of a conversion instruction.
- required next-vreg [ src required preferred emit-conversion ] keep ;
+ required next-vreg-rep [ src required preferred emit-conversion ] keep ;
SYMBOLS: renaming-set needs-renaming? ;
2array renaming-set get push needs-renaming? on ;
:: (compute-renaming-set) ( vreg required quot: ( vreg preferred required -- ) -- )
- vreg preferred get at :> preferred
+ vreg rep-of :> preferred
preferred required eq?
[ vreg no-renaming ]
[ vreg vreg preferred required quot call record-renaming ] if ; inline
GENERIC: conversions-for-insn ( insn -- )
-! Inserting conversions for a phi is done in compiler.cfg.cssa
-M: ##phi conversions-for-insn , ;
+SYMBOL: phi-mappings
+
+! compiler.cfg.cssa inserts conversions which convert phi inputs into
+! the representation of the output. However, we still have to do some
+! processing here, because if the only node that uses the output of
+! the phi instruction is another phi instruction then this phi node's
+! output won't have a representation assigned.
+M: ##phi conversions-for-insn
+ [ , ] [ [ inputs>> values ] [ dst>> ] bi phi-mappings get set-at ] bi ;
M: vreg-insn conversions-for-insn
[ compute-renaming-set ] [ perform-renaming ] bi ;
] change-instructions drop
] if ;
+! If the output of a phi instruction is only used as the input to another
+! phi instruction, then we want to use the same representation for both
+! if possible.
+SYMBOL: work-list
+
+: add-to-work-list ( vregs -- )
+ work-list get push-all-front ;
+
+: rep-assigned ( vregs -- vregs' )
+ representations get '[ _ key? ] filter ;
+
+: rep-not-assigned ( vregs -- vregs' )
+ representations get '[ _ key? not ] filter ;
+
+: add-ready-phis ( -- )
+ phi-mappings get keys rep-assigned add-to-work-list ;
+
+: process-phi-mapping ( dst -- )
+ ! If dst = phi(src1,src2,...) and dst's representation has been
+ ! determined, assign that representation to each one of src1,...
+ ! that does not have a representation yet, and process those, too.
+ dup phi-mappings get at* [
+ [ rep-of ] [ rep-not-assigned ] bi*
+ [ [ set-rep-of ] with each ] [ add-to-work-list ] bi
+ ] [ 2drop ] if ;
+
+: remaining-phi-mappings ( -- )
+ phi-mappings get keys rep-not-assigned
+ [ [ int-rep ] dip set-rep-of ] each ;
+
+: process-phi-mappings ( -- )
+ <hashed-dlist> work-list set
+ add-ready-phis
+ work-list get [ process-phi-mapping ] slurp-deque
+ remaining-phi-mappings ;
+
: insert-conversions ( cfg -- )
- [ conversions-for-block ] each-basic-block ;
+ H{ } clone phi-mappings set
+ [ conversions-for-block ] each-basic-block
+ process-phi-mappings ;
+
+PRIVATE>
: select-representations ( cfg -- cfg' )
{
[ compute-possibilities ]
- [ compute-costs ]
+ [ compute-representations ]
[ insert-conversions ]
- [ preferred get [ >>rep drop ] assoc-each ]
- } cleave ;
\ No newline at end of file
+ [ ]
+ } cleave
+ representations get cfg get (>>reps) ;
\ No newline at end of file
reset-counters
V{
- T{ ##load-immediate f V int-rep 1 100 }
- T{ ##add-imm f V int-rep 2 V int-rep 1 50 }
- T{ ##add-imm f V int-rep 2 V int-rep 2 10 }
+ T{ ##load-immediate f 1 100 }
+ T{ ##add-imm f 2 1 50 }
+ T{ ##add-imm f 2 2 10 }
T{ ##branch }
} 0 test-bb
V{
- T{ ##load-immediate f V int-rep 3 3 }
+ T{ ##load-immediate f 3 3 }
T{ ##branch }
} 1 test-bb
V{
- T{ ##load-immediate f V int-rep 3 4 }
+ T{ ##load-immediate f 3 4 }
T{ ##branch }
} 2 test-bb
V{
- T{ ##replace f V int-rep 3 D 0 }
+ T{ ##replace f 3 D 0 }
T{ ##return }
} 3 test-bb
[
V{
- T{ ##load-immediate f V int-rep 1 100 }
- T{ ##add-imm f V int-rep 2 V int-rep 1 50 }
- T{ ##add-imm f V int-rep 3 V int-rep 2 10 }
+ T{ ##load-immediate f 1 100 }
+ T{ ##add-imm f 2 1 50 }
+ T{ ##add-imm f 3 2 10 }
T{ ##branch }
}
] [ 0 get instructions>> ] unit-test
[
V{
- T{ ##load-immediate f V int-rep 4 3 }
+ T{ ##load-immediate f 4 3 }
T{ ##branch }
}
] [ 1 get instructions>> ] unit-test
[
V{
- T{ ##load-immediate f V int-rep 5 4 }
+ T{ ##load-immediate f 5 4 }
T{ ##branch }
}
] [ 2 get instructions>> ] unit-test
[
V{
- T{ ##phi f V int-rep 6 H{ { 1 V int-rep 4 } { 2 V int-rep 5 } } }
- T{ ##replace f V int-rep 6 D 0 }
+ T{ ##phi f 6 H{ { 1 4 } { 2 5 } } }
+ T{ ##replace f 6 D 0 }
T{ ##return }
}
] [
V{ } 0 test-bb
V{ } 1 test-bb
-V{ T{ ##peek f V int-rep 0 D 0 } } 2 test-bb
-V{ T{ ##peek f V int-rep 0 D 0 } } 3 test-bb
-V{ T{ ##replace f V int-rep 0 D 0 } } 4 test-bb
+V{ T{ ##peek f 0 D 0 } } 2 test-bb
+V{ T{ ##peek f 0 D 0 } } 3 test-bb
+V{ T{ ##replace f 0 D 0 } } 4 test-bb
V{ } 5 test-bb
V{ } 6 test-bb
[
V{
- T{ ##phi f V int-rep 3 H{ { 2 V int-rep 1 } { 3 V int-rep 2 } } }
- T{ ##replace f V int-rep 3 D 0 }
+ T{ ##phi f 3 H{ { 2 1 } { 3 2 } } }
+ T{ ##replace f 3 D 0 }
}
] [
4 get instructions>>
H{ } clone stacks set ;
: gen-name ( vreg -- vreg' )
- [ fresh-value dup ] keep
+ [ next-vreg dup ] dip
dup pushed get 2dup key?
[ 2drop stacks get at set-last ]
[ conjoin stacks get push-at ]
compiler.cfg.representations ;
IN: compiler.cfg.ssa.cssa
-! Convert SSA to conventional SSA.
+! Convert SSA to conventional SSA. This pass runs after representation
+! selection, so it must keep track of representations when introducing
+! new values.
:: insert-copy ( bb src rep -- bb dst )
- rep next-vreg :> dst
- bb [ dst src rep src rep>> emit-conversion ] add-instructions
+ rep next-vreg-rep :> dst
+ bb [ dst src rep src rep-of emit-conversion ] add-instructions
bb dst ;
: convert-phi ( ##phi -- )
- dup dst>> rep>> '[ [ _ insert-copy ] assoc-map ] change-inputs drop ;
+ dup dst>> rep-of '[ [ _ insert-copy ] assoc-map ] change-inputs drop ;
: construct-cssa ( cfg -- )
[ [ convert-phi ] each-phi ] each-basic-block ;
\ No newline at end of file
: eliminate-copy ( vreg1 vreg2 -- )
[ leader ] bi@
2dup eq? [ 2drop ] [
- [ [ rep>> ] bi@ assert= ]
[ update-leaders ]
[ merge-classes ]
- 2tri
+ 2bi
] if ;
: introduce-vreg ( vreg -- )
compute-live-ranges ;
V{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##peek f V int-rep 2 D 0 }
- T{ ##copy f V int-rep 1 V int-rep 0 }
- T{ ##copy f V int-rep 3 V int-rep 2 }
+ T{ ##peek f 0 D 0 }
+ T{ ##peek f 2 D 0 }
+ T{ ##copy f 1 0 }
+ T{ ##copy f 3 2 }
T{ ##branch }
} 0 test-bb
V{
- T{ ##peek f V int-rep 4 D 0 }
- T{ ##peek f V int-rep 5 D 0 }
- T{ ##replace f V int-rep 3 D 0 }
- T{ ##peek f V int-rep 6 D 0 }
- T{ ##replace f V int-rep 5 D 0 }
+ T{ ##peek f 4 D 0 }
+ T{ ##peek f 5 D 0 }
+ T{ ##replace f 3 D 0 }
+ T{ ##peek f 6 D 0 }
+ T{ ##replace f 5 D 0 }
T{ ##return }
} 1 test-bb
[ ] [ test-interference ] unit-test
-[ f ] [ V int-rep 0 V int-rep 1 vregs-interfere? ] unit-test
-[ f ] [ V int-rep 1 V int-rep 0 vregs-interfere? ] unit-test
-[ f ] [ V int-rep 2 V int-rep 3 vregs-interfere? ] unit-test
-[ f ] [ V int-rep 3 V int-rep 2 vregs-interfere? ] unit-test
-[ t ] [ V int-rep 0 V int-rep 2 vregs-interfere? ] unit-test
-[ t ] [ V int-rep 2 V int-rep 0 vregs-interfere? ] unit-test
-[ f ] [ V int-rep 1 V int-rep 3 vregs-interfere? ] unit-test
-[ f ] [ V int-rep 3 V int-rep 1 vregs-interfere? ] unit-test
-[ t ] [ V int-rep 3 V int-rep 4 vregs-interfere? ] unit-test
-[ t ] [ V int-rep 4 V int-rep 3 vregs-interfere? ] unit-test
-[ t ] [ V int-rep 3 V int-rep 5 vregs-interfere? ] unit-test
-[ t ] [ V int-rep 5 V int-rep 3 vregs-interfere? ] unit-test
-[ f ] [ V int-rep 3 V int-rep 6 vregs-interfere? ] unit-test
-[ f ] [ V int-rep 6 V int-rep 3 vregs-interfere? ] unit-test
\ No newline at end of file
+[ f ] [ 0 1 vregs-interfere? ] unit-test
+[ f ] [ 1 0 vregs-interfere? ] unit-test
+[ f ] [ 2 3 vregs-interfere? ] unit-test
+[ f ] [ 3 2 vregs-interfere? ] unit-test
+[ t ] [ 0 2 vregs-interfere? ] unit-test
+[ t ] [ 2 0 vregs-interfere? ] unit-test
+[ f ] [ 1 3 vregs-interfere? ] unit-test
+[ f ] [ 3 1 vregs-interfere? ] unit-test
+[ t ] [ 3 4 vregs-interfere? ] unit-test
+[ t ] [ 4 3 vregs-interfere? ] unit-test
+[ t ] [ 3 5 vregs-interfere? ] unit-test
+[ t ] [ 5 3 vregs-interfere? ] unit-test
+[ f ] [ 3 6 vregs-interfere? ] unit-test
+[ f ] [ 6 3 vregs-interfere? ] unit-test
\ No newline at end of file
SYMBOL: locs>vregs
-: loc>vreg ( loc -- vreg ) locs>vregs get [ drop i ] cache ;
+: loc>vreg ( loc -- vreg ) locs>vregs get [ drop next-vreg ] cache ;
: vreg>loc ( vreg -- loc/f ) locs>vregs get value-at ;
TUPLE: current-height
} 0 test-bb
V{
- T{ ##replace f V int-rep 0 D 0 }
- T{ ##replace f V int-rep 0 D 1 }
- T{ ##replace f V int-rep 0 D 2 }
+ T{ ##replace f 0 D 0 }
+ T{ ##replace f 0 D 1 }
+ T{ ##replace f 0 D 2 }
T{ ##inc-r f 1 }
} 1 test-bb
V{
- T{ ##peek f V int-rep 0 D 0 }
+ T{ ##peek f 0 D 0 }
T{ ##inc-d f 1 }
} 2 test-bb
IN: compiler.cfg.two-operand.tests
-USING: compiler.cfg.two-operand compiler.cfg.instructions
+USING: kernel compiler.cfg.two-operand compiler.cfg.instructions
compiler.cfg.registers cpu.architecture namespaces tools.test ;
3 vreg-counter set-global
[
V{
- T{ ##copy f V int-rep 1 V int-rep 2 int-rep }
- T{ ##sub f V int-rep 1 V int-rep 1 V int-rep 3 }
+ T{ ##copy f 1 2 int-rep }
+ T{ ##sub f 1 1 3 }
}
] [
+ H{
+ { 1 int-rep }
+ { 2 int-rep }
+ { 3 int-rep }
+ } clone representations set
{
- T{ ##sub f V int-rep 1 V int-rep 2 V int-rep 3 }
+ T{ ##sub f 1 2 3 }
} (convert-two-operand)
] unit-test
[
V{
- T{ ##copy f V double-float-rep 1 V double-float-rep 2 double-float-rep }
- T{ ##sub-float f V double-float-rep 1 V double-float-rep 1 V double-float-rep 3 }
+ T{ ##copy f 1 2 double-float-rep }
+ T{ ##sub-float f 1 1 3 }
}
] [
+ H{
+ { 1 double-float-rep }
+ { 2 double-float-rep }
+ { 3 double-float-rep }
+ } clone representations set
{
- T{ ##sub-float f V double-float-rep 1 V double-float-rep 2 V double-float-rep 3 }
+ T{ ##sub-float f 1 2 3 }
} (convert-two-operand)
] unit-test
GENERIC: convert-two-operand* ( insn -- )
: emit-copy ( dst src -- )
- dup rep>> ##copy ; inline
+ dup rep-of ##copy ; inline
M: two-operand-insn convert-two-operand*
[ [ dst>> ] [ src1>> ] bi emit-copy ]
[ instructions>> ] dip
'[ dup ##phi? [ @ t ] [ drop f ] if ] all? drop ; inline
+: each-non-phi ( bb quot: ( insn -- ) -- )
+ [ instructions>> ] dip
+ '[ dup ##phi? [ drop ] _ if ] each ; inline
+
: predecessor ( bb -- pred )
predecessors>> first ; inline
fry kernel layouts math namespaces sequences cpu.architecture
math.bitwise math.order classes vectors
compiler.cfg
-compiler.cfg.hats
+compiler.cfg.registers
compiler.cfg.comparisons
compiler.cfg.instructions
compiler.cfg.value-numbering.expressions
M: ##compare-imm rewrite-tagged-comparison
[ dst>> ] [ (rewrite-tagged-comparison) ] bi
- i \ ##compare-imm new-insn ;
+ next-vreg \ ##compare-imm new-insn ;
: rewrite-redundant-comparison? ( insn -- ? )
{
: rewrite-redundant-comparison ( insn -- insn' )
[ cc>> ] [ dst>> ] [ src1>> vreg>expr dup op>> ] tri {
- { \ ##compare [ >compare-expr< i \ ##compare new-insn ] }
- { \ ##compare-imm [ >compare-imm-expr< i \ ##compare-imm new-insn ] }
- { \ ##compare-float [ >compare-expr< i \ ##compare-float new-insn ] }
+ { \ ##compare [ >compare-expr< next-vreg \ ##compare new-insn ] }
+ { \ ##compare-imm [ >compare-imm-expr< next-vreg \ ##compare-imm new-insn ] }
+ { \ ##compare-float [ >compare-expr< next-vreg \ ##compare-float new-insn ] }
} case
swap cc= eq? [ [ negate-cc ] change-cc ] when ;
] dip
swap-compare
[ vreg>constant ] dip
- i \ ##compare-imm new-insn ; inline
+ next-vreg \ ##compare-imm new-insn ; inline
: >boolean-insn ( insn ? -- insn' )
[ dst>> ] dip
-IN: compiler.cfg.value-numbering.tests
USING: compiler.cfg.value-numbering compiler.cfg.instructions
compiler.cfg.registers compiler.cfg.debugger compiler.cfg.comparisons
cpu.architecture tools.test kernel math combinators.short-circuit
-accessors sequences compiler.cfg.predecessors locals
-compiler.cfg.dce compiler.cfg.ssa.destruction
-compiler.cfg assocs vectors arrays layouts namespaces ;
+accessors sequences compiler.cfg.predecessors locals compiler.cfg.dce
+compiler.cfg.ssa.destruction compiler.cfg.loop-detection
+compiler.cfg.representations compiler.cfg assocs vectors arrays
+layouts namespaces ;
+IN: compiler.cfg.value-numbering.tests
: trim-temps ( insns -- insns )
[
! Folding constants together
[
{
- T{ ##load-reference f V int-rep 0 0.0 }
- T{ ##load-reference f V int-rep 1 -0.0 }
- T{ ##replace f V int-rep 0 D 0 }
- T{ ##replace f V int-rep 1 D 1 }
+ T{ ##load-reference f 0 0.0 }
+ T{ ##load-reference f 1 -0.0 }
+ T{ ##replace f 0 D 0 }
+ T{ ##replace f 1 D 1 }
}
] [
{
- T{ ##load-reference f V int-rep 0 0.0 }
- T{ ##load-reference f V int-rep 1 -0.0 }
- T{ ##replace f V int-rep 0 D 0 }
- T{ ##replace f V int-rep 1 D 1 }
+ T{ ##load-reference f 0 0.0 }
+ T{ ##load-reference f 1 -0.0 }
+ T{ ##replace f 0 D 0 }
+ T{ ##replace f 1 D 1 }
} value-numbering-step
] unit-test
[
{
- T{ ##load-reference f V int-rep 0 0.0 }
- T{ ##copy f V int-rep 1 V int-rep 0 int-rep }
- T{ ##replace f V int-rep 0 D 0 }
- T{ ##replace f V int-rep 1 D 1 }
+ T{ ##load-reference f 0 0.0 }
+ T{ ##copy f 1 0 any-rep }
+ T{ ##replace f 0 D 0 }
+ T{ ##replace f 1 D 1 }
}
] [
{
- T{ ##load-reference f V int-rep 0 0.0 }
- T{ ##load-reference f V int-rep 1 0.0 }
- T{ ##replace f V int-rep 0 D 0 }
- T{ ##replace f V int-rep 1 D 1 }
+ T{ ##load-reference f 0 0.0 }
+ T{ ##load-reference f 1 0.0 }
+ T{ ##replace f 0 D 0 }
+ T{ ##replace f 1 D 1 }
} value-numbering-step
] unit-test
[
{
- T{ ##load-reference f V int-rep 0 t }
- T{ ##copy f V int-rep 1 V int-rep 0 int-rep }
- T{ ##replace f V int-rep 0 D 0 }
- T{ ##replace f V int-rep 1 D 1 }
+ T{ ##load-reference f 0 t }
+ T{ ##copy f 1 0 any-rep }
+ T{ ##replace f 0 D 0 }
+ T{ ##replace f 1 D 1 }
}
] [
{
- T{ ##load-reference f V int-rep 0 t }
- T{ ##load-reference f V int-rep 1 t }
- T{ ##replace f V int-rep 0 D 0 }
- T{ ##replace f V int-rep 1 D 1 }
+ T{ ##load-reference f 0 t }
+ T{ ##load-reference f 1 t }
+ T{ ##replace f 0 D 0 }
+ T{ ##replace f 1 D 1 }
} value-numbering-step
] unit-test
! Compare propagation
[
{
- T{ ##load-reference f V int-rep 1 + }
- T{ ##peek f V int-rep 2 D 0 }
- T{ ##compare f V int-rep 4 V int-rep 2 V int-rep 1 cc> }
- T{ ##copy f V int-rep 6 V int-rep 4 int-rep }
- T{ ##replace f V int-rep 6 D 0 }
+ T{ ##load-reference f 1 + }
+ T{ ##peek f 2 D 0 }
+ T{ ##compare f 4 2 1 cc> }
+ T{ ##copy f 6 4 any-rep }
+ T{ ##replace f 6 D 0 }
}
] [
{
- T{ ##load-reference f V int-rep 1 + }
- T{ ##peek f V int-rep 2 D 0 }
- T{ ##compare f V int-rep 4 V int-rep 2 V int-rep 1 cc> }
- T{ ##compare-imm f V int-rep 6 V int-rep 4 5 cc/= }
- T{ ##replace f V int-rep 6 D 0 }
+ T{ ##load-reference f 1 + }
+ T{ ##peek f 2 D 0 }
+ T{ ##compare f 4 2 1 cc> }
+ T{ ##compare-imm f 6 4 5 cc/= }
+ T{ ##replace f 6 D 0 }
} value-numbering-step trim-temps
] unit-test
[
{
- T{ ##load-reference f V int-rep 1 + }
- T{ ##peek f V int-rep 2 D 0 }
- T{ ##compare f V int-rep 4 V int-rep 2 V int-rep 1 cc<= }
- T{ ##compare f V int-rep 6 V int-rep 2 V int-rep 1 cc> }
- T{ ##replace f V int-rep 6 D 0 }
+ T{ ##load-reference f 1 + }
+ T{ ##peek f 2 D 0 }
+ T{ ##compare f 4 2 1 cc<= }
+ T{ ##compare f 6 2 1 cc> }
+ T{ ##replace f 6 D 0 }
}
] [
{
- T{ ##load-reference f V int-rep 1 + }
- T{ ##peek f V int-rep 2 D 0 }
- T{ ##compare f V int-rep 4 V int-rep 2 V int-rep 1 cc<= }
- T{ ##compare-imm f V int-rep 6 V int-rep 4 5 cc= }
- T{ ##replace f V int-rep 6 D 0 }
+ T{ ##load-reference f 1 + }
+ T{ ##peek f 2 D 0 }
+ T{ ##compare f 4 2 1 cc<= }
+ T{ ##compare-imm f 6 4 5 cc= }
+ T{ ##replace f 6 D 0 }
} value-numbering-step trim-temps
] unit-test
[
{
- T{ ##peek f V int-rep 8 D 0 }
- T{ ##peek f V int-rep 9 D -1 }
- T{ ##unbox-float f V double-float-rep 10 V int-rep 8 }
- T{ ##unbox-float f V double-float-rep 11 V int-rep 9 }
- T{ ##compare-float f V int-rep 12 V double-float-rep 10 V double-float-rep 11 cc< }
- T{ ##compare-float f V int-rep 14 V double-float-rep 10 V double-float-rep 11 cc>= }
- T{ ##replace f V int-rep 14 D 0 }
+ T{ ##peek f 8 D 0 }
+ T{ ##peek f 9 D -1 }
+ T{ ##unbox-float f 10 8 }
+ T{ ##unbox-float f 11 9 }
+ T{ ##compare-float f 12 10 11 cc< }
+ T{ ##compare-float f 14 10 11 cc>= }
+ T{ ##replace f 14 D 0 }
}
] [
{
- T{ ##peek f V int-rep 8 D 0 }
- T{ ##peek f V int-rep 9 D -1 }
- T{ ##unbox-float f V double-float-rep 10 V int-rep 8 }
- T{ ##unbox-float f V double-float-rep 11 V int-rep 9 }
- T{ ##compare-float f V int-rep 12 V double-float-rep 10 V double-float-rep 11 cc< }
- T{ ##compare-imm f V int-rep 14 V int-rep 12 5 cc= }
- T{ ##replace f V int-rep 14 D 0 }
+ T{ ##peek f 8 D 0 }
+ T{ ##peek f 9 D -1 }
+ T{ ##unbox-float f 10 8 }
+ T{ ##unbox-float f 11 9 }
+ T{ ##compare-float f 12 10 11 cc< }
+ T{ ##compare-imm f 14 12 5 cc= }
+ T{ ##replace f 14 D 0 }
} value-numbering-step trim-temps
] unit-test
[
{
- T{ ##peek f V int-rep 29 D -1 }
- T{ ##peek f V int-rep 30 D -2 }
- T{ ##compare f V int-rep 33 V int-rep 29 V int-rep 30 cc<= }
- T{ ##compare-branch f V int-rep 29 V int-rep 30 cc<= }
+ T{ ##peek f 29 D -1 }
+ T{ ##peek f 30 D -2 }
+ T{ ##compare f 33 29 30 cc<= }
+ T{ ##compare-branch f 29 30 cc<= }
}
] [
{
- T{ ##peek f V int-rep 29 D -1 }
- T{ ##peek f V int-rep 30 D -2 }
- T{ ##compare f V int-rep 33 V int-rep 29 V int-rep 30 cc<= }
- T{ ##compare-imm-branch f V int-rep 33 5 cc/= }
+ T{ ##peek f 29 D -1 }
+ T{ ##peek f 30 D -2 }
+ T{ ##compare f 33 29 30 cc<= }
+ T{ ##compare-imm-branch f 33 5 cc/= }
} value-numbering-step trim-temps
] unit-test
! Immediate operand conversion
[
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 100 }
- T{ ##add-imm f V int-rep 2 V int-rep 0 100 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 100 }
+ T{ ##add-imm f 2 0 100 }
}
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 100 }
- T{ ##add f V int-rep 2 V int-rep 0 V int-rep 1 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 100 }
+ T{ ##add f 2 0 1 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 100 }
- T{ ##add-imm f V int-rep 2 V int-rep 0 100 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 100 }
+ T{ ##add-imm f 2 0 100 }
}
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 100 }
- T{ ##add f V int-rep 2 V int-rep 1 V int-rep 0 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 100 }
+ T{ ##add f 2 1 0 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 100 }
- T{ ##add-imm f V int-rep 2 V int-rep 0 -100 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 100 }
+ T{ ##add-imm f 2 0 -100 }
}
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 100 }
- T{ ##sub f V int-rep 2 V int-rep 0 V int-rep 1 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 100 }
+ T{ ##sub f 2 0 1 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 0 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 0 }
}
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##sub f V int-rep 1 V int-rep 0 V int-rep 0 }
+ T{ ##peek f 0 D 0 }
+ T{ ##sub f 1 0 0 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 100 }
- T{ ##mul-imm f V int-rep 2 V int-rep 0 100 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 100 }
+ T{ ##mul-imm f 2 0 100 }
}
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 100 }
- T{ ##mul f V int-rep 2 V int-rep 0 V int-rep 1 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 100 }
+ T{ ##mul f 2 0 1 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 100 }
- T{ ##mul-imm f V int-rep 2 V int-rep 0 100 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 100 }
+ T{ ##mul-imm f 2 0 100 }
}
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 100 }
- T{ ##mul f V int-rep 2 V int-rep 1 V int-rep 0 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 100 }
+ T{ ##mul f 2 1 0 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-rep 1 D 0 }
- T{ ##shl-imm f V int-rep 2 V int-rep 1 3 }
+ T{ ##peek f 1 D 0 }
+ T{ ##shl-imm f 2 1 3 }
}
] [
{
- T{ ##peek f V int-rep 1 D 0 }
- T{ ##mul-imm f V int-rep 2 V int-rep 1 8 }
+ T{ ##peek f 1 D 0 }
+ T{ ##mul-imm f 2 1 8 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 100 }
- T{ ##and-imm f V int-rep 2 V int-rep 0 100 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 100 }
+ T{ ##and-imm f 2 0 100 }
}
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 100 }
- T{ ##and f V int-rep 2 V int-rep 0 V int-rep 1 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 100 }
+ T{ ##and f 2 0 1 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 100 }
- T{ ##and-imm f V int-rep 2 V int-rep 0 100 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 100 }
+ T{ ##and-imm f 2 0 100 }
}
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 100 }
- T{ ##and f V int-rep 2 V int-rep 1 V int-rep 0 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 100 }
+ T{ ##and f 2 1 0 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 100 }
- T{ ##or-imm f V int-rep 2 V int-rep 0 100 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 100 }
+ T{ ##or-imm f 2 0 100 }
}
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 100 }
- T{ ##or f V int-rep 2 V int-rep 0 V int-rep 1 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 100 }
+ T{ ##or f 2 0 1 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 100 }
- T{ ##or-imm f V int-rep 2 V int-rep 0 100 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 100 }
+ T{ ##or-imm f 2 0 100 }
}
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 100 }
- T{ ##or f V int-rep 2 V int-rep 1 V int-rep 0 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 100 }
+ T{ ##or f 2 1 0 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 100 }
- T{ ##xor-imm f V int-rep 2 V int-rep 0 100 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 100 }
+ T{ ##xor-imm f 2 0 100 }
}
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 100 }
- T{ ##xor f V int-rep 2 V int-rep 0 V int-rep 1 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 100 }
+ T{ ##xor f 2 0 1 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 100 }
- T{ ##xor-imm f V int-rep 2 V int-rep 0 100 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 100 }
+ T{ ##xor-imm f 2 0 100 }
}
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 100 }
- T{ ##xor f V int-rep 2 V int-rep 1 V int-rep 0 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 100 }
+ T{ ##xor f 2 1 0 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 100 }
- T{ ##compare-imm f V int-rep 2 V int-rep 0 100 cc<= }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 100 }
+ T{ ##compare-imm f 2 0 100 cc<= }
}
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 100 }
- T{ ##compare f V int-rep 2 V int-rep 0 V int-rep 1 cc<= }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 100 }
+ T{ ##compare f 2 0 1 cc<= }
} value-numbering-step trim-temps
] unit-test
[
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 100 }
- T{ ##compare-imm f V int-rep 2 V int-rep 0 100 cc>= }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 100 }
+ T{ ##compare-imm f 2 0 100 cc>= }
}
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 100 }
- T{ ##compare f V int-rep 2 V int-rep 1 V int-rep 0 cc<= }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 100 }
+ T{ ##compare f 2 1 0 cc<= }
} value-numbering-step trim-temps
] unit-test
[
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 100 }
- T{ ##compare-imm-branch f V int-rep 0 100 cc<= }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 100 }
+ T{ ##compare-imm-branch f 0 100 cc<= }
}
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 100 }
- T{ ##compare-branch f V int-rep 0 V int-rep 1 cc<= }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 100 }
+ T{ ##compare-branch f 0 1 cc<= }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 100 }
- T{ ##compare-imm-branch f V int-rep 0 100 cc>= }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 100 }
+ T{ ##compare-imm-branch f 0 100 cc>= }
}
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 100 }
- T{ ##compare-branch f V int-rep 1 V int-rep 0 cc<= }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 100 }
+ T{ ##compare-branch f 1 0 cc<= }
} value-numbering-step trim-temps
] unit-test
! Reassociation
[
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 100 }
- T{ ##add-imm f V int-rep 2 V int-rep 0 100 }
- T{ ##load-immediate f V int-rep 3 50 }
- T{ ##add-imm f V int-rep 4 V int-rep 0 150 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 100 }
+ T{ ##add-imm f 2 0 100 }
+ T{ ##load-immediate f 3 50 }
+ T{ ##add-imm f 4 0 150 }
}
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 100 }
- T{ ##add f V int-rep 2 V int-rep 0 V int-rep 1 }
- T{ ##load-immediate f V int-rep 3 50 }
- T{ ##add f V int-rep 4 V int-rep 2 V int-rep 3 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 100 }
+ T{ ##add f 2 0 1 }
+ T{ ##load-immediate f 3 50 }
+ T{ ##add f 4 2 3 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 100 }
- T{ ##add-imm f V int-rep 2 V int-rep 0 100 }
- T{ ##load-immediate f V int-rep 3 50 }
- T{ ##add-imm f V int-rep 4 V int-rep 0 150 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 100 }
+ T{ ##add-imm f 2 0 100 }
+ T{ ##load-immediate f 3 50 }
+ T{ ##add-imm f 4 0 150 }
}
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 100 }
- T{ ##add f V int-rep 2 V int-rep 1 V int-rep 0 }
- T{ ##load-immediate f V int-rep 3 50 }
- T{ ##add f V int-rep 4 V int-rep 3 V int-rep 2 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 100 }
+ T{ ##add f 2 1 0 }
+ T{ ##load-immediate f 3 50 }
+ T{ ##add f 4 3 2 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 100 }
- T{ ##add-imm f V int-rep 2 V int-rep 0 100 }
- T{ ##load-immediate f V int-rep 3 50 }
- T{ ##add-imm f V int-rep 4 V int-rep 0 50 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 100 }
+ T{ ##add-imm f 2 0 100 }
+ T{ ##load-immediate f 3 50 }
+ T{ ##add-imm f 4 0 50 }
}
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 100 }
- T{ ##add f V int-rep 2 V int-rep 0 V int-rep 1 }
- T{ ##load-immediate f V int-rep 3 50 }
- T{ ##sub f V int-rep 4 V int-rep 2 V int-rep 3 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 100 }
+ T{ ##add f 2 0 1 }
+ T{ ##load-immediate f 3 50 }
+ T{ ##sub f 4 2 3 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 100 }
- T{ ##add-imm f V int-rep 2 V int-rep 0 -100 }
- T{ ##load-immediate f V int-rep 3 50 }
- T{ ##add-imm f V int-rep 4 V int-rep 0 -150 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 100 }
+ T{ ##add-imm f 2 0 -100 }
+ T{ ##load-immediate f 3 50 }
+ T{ ##add-imm f 4 0 -150 }
}
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 100 }
- T{ ##sub f V int-rep 2 V int-rep 0 V int-rep 1 }
- T{ ##load-immediate f V int-rep 3 50 }
- T{ ##sub f V int-rep 4 V int-rep 2 V int-rep 3 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 100 }
+ T{ ##sub f 2 0 1 }
+ T{ ##load-immediate f 3 50 }
+ T{ ##sub f 4 2 3 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 100 }
- T{ ##mul-imm f V int-rep 2 V int-rep 0 100 }
- T{ ##load-immediate f V int-rep 3 50 }
- T{ ##mul-imm f V int-rep 4 V int-rep 0 5000 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 100 }
+ T{ ##mul-imm f 2 0 100 }
+ T{ ##load-immediate f 3 50 }
+ T{ ##mul-imm f 4 0 5000 }
}
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 100 }
- T{ ##mul f V int-rep 2 V int-rep 0 V int-rep 1 }
- T{ ##load-immediate f V int-rep 3 50 }
- T{ ##mul f V int-rep 4 V int-rep 2 V int-rep 3 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 100 }
+ T{ ##mul f 2 0 1 }
+ T{ ##load-immediate f 3 50 }
+ T{ ##mul f 4 2 3 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 100 }
- T{ ##mul-imm f V int-rep 2 V int-rep 0 100 }
- T{ ##load-immediate f V int-rep 3 50 }
- T{ ##mul-imm f V int-rep 4 V int-rep 0 5000 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 100 }
+ T{ ##mul-imm f 2 0 100 }
+ T{ ##load-immediate f 3 50 }
+ T{ ##mul-imm f 4 0 5000 }
}
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 100 }
- T{ ##mul f V int-rep 2 V int-rep 1 V int-rep 0 }
- T{ ##load-immediate f V int-rep 3 50 }
- T{ ##mul f V int-rep 4 V int-rep 3 V int-rep 2 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 100 }
+ T{ ##mul f 2 1 0 }
+ T{ ##load-immediate f 3 50 }
+ T{ ##mul f 4 3 2 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 100 }
- T{ ##and-imm f V int-rep 2 V int-rep 0 100 }
- T{ ##load-immediate f V int-rep 3 50 }
- T{ ##and-imm f V int-rep 4 V int-rep 0 32 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 100 }
+ T{ ##and-imm f 2 0 100 }
+ T{ ##load-immediate f 3 50 }
+ T{ ##and-imm f 4 0 32 }
}
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 100 }
- T{ ##and f V int-rep 2 V int-rep 0 V int-rep 1 }
- T{ ##load-immediate f V int-rep 3 50 }
- T{ ##and f V int-rep 4 V int-rep 2 V int-rep 3 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 100 }
+ T{ ##and f 2 0 1 }
+ T{ ##load-immediate f 3 50 }
+ T{ ##and f 4 2 3 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 100 }
- T{ ##and-imm f V int-rep 2 V int-rep 0 100 }
- T{ ##load-immediate f V int-rep 3 50 }
- T{ ##and-imm f V int-rep 4 V int-rep 0 32 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 100 }
+ T{ ##and-imm f 2 0 100 }
+ T{ ##load-immediate f 3 50 }
+ T{ ##and-imm f 4 0 32 }
}
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 100 }
- T{ ##and f V int-rep 2 V int-rep 1 V int-rep 0 }
- T{ ##load-immediate f V int-rep 3 50 }
- T{ ##and f V int-rep 4 V int-rep 3 V int-rep 2 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 100 }
+ T{ ##and f 2 1 0 }
+ T{ ##load-immediate f 3 50 }
+ T{ ##and f 4 3 2 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 100 }
- T{ ##or-imm f V int-rep 2 V int-rep 0 100 }
- T{ ##load-immediate f V int-rep 3 50 }
- T{ ##or-imm f V int-rep 4 V int-rep 0 118 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 100 }
+ T{ ##or-imm f 2 0 100 }
+ T{ ##load-immediate f 3 50 }
+ T{ ##or-imm f 4 0 118 }
}
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 100 }
- T{ ##or f V int-rep 2 V int-rep 0 V int-rep 1 }
- T{ ##load-immediate f V int-rep 3 50 }
- T{ ##or f V int-rep 4 V int-rep 2 V int-rep 3 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 100 }
+ T{ ##or f 2 0 1 }
+ T{ ##load-immediate f 3 50 }
+ T{ ##or f 4 2 3 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 100 }
- T{ ##or-imm f V int-rep 2 V int-rep 0 100 }
- T{ ##load-immediate f V int-rep 3 50 }
- T{ ##or-imm f V int-rep 4 V int-rep 0 118 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 100 }
+ T{ ##or-imm f 2 0 100 }
+ T{ ##load-immediate f 3 50 }
+ T{ ##or-imm f 4 0 118 }
}
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 100 }
- T{ ##or f V int-rep 2 V int-rep 1 V int-rep 0 }
- T{ ##load-immediate f V int-rep 3 50 }
- T{ ##or f V int-rep 4 V int-rep 3 V int-rep 2 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 100 }
+ T{ ##or f 2 1 0 }
+ T{ ##load-immediate f 3 50 }
+ T{ ##or f 4 3 2 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 100 }
- T{ ##xor-imm f V int-rep 2 V int-rep 0 100 }
- T{ ##load-immediate f V int-rep 3 50 }
- T{ ##xor-imm f V int-rep 4 V int-rep 0 86 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 100 }
+ T{ ##xor-imm f 2 0 100 }
+ T{ ##load-immediate f 3 50 }
+ T{ ##xor-imm f 4 0 86 }
}
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 100 }
- T{ ##xor f V int-rep 2 V int-rep 0 V int-rep 1 }
- T{ ##load-immediate f V int-rep 3 50 }
- T{ ##xor f V int-rep 4 V int-rep 2 V int-rep 3 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 100 }
+ T{ ##xor f 2 0 1 }
+ T{ ##load-immediate f 3 50 }
+ T{ ##xor f 4 2 3 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 100 }
- T{ ##xor-imm f V int-rep 2 V int-rep 0 100 }
- T{ ##load-immediate f V int-rep 3 50 }
- T{ ##xor-imm f V int-rep 4 V int-rep 0 86 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 100 }
+ T{ ##xor-imm f 2 0 100 }
+ T{ ##load-immediate f 3 50 }
+ T{ ##xor-imm f 4 0 86 }
}
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 100 }
- T{ ##xor f V int-rep 2 V int-rep 1 V int-rep 0 }
- T{ ##load-immediate f V int-rep 3 50 }
- T{ ##xor f V int-rep 4 V int-rep 3 V int-rep 2 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 100 }
+ T{ ##xor f 2 1 0 }
+ T{ ##load-immediate f 3 50 }
+ T{ ##xor f 4 3 2 }
} value-numbering-step
] unit-test
! Simplification
[
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##peek f V int-rep 1 D 1 }
- T{ ##load-immediate f V int-rep 2 0 }
- T{ ##copy f V int-rep 3 V int-rep 0 int-rep }
- T{ ##replace f V int-rep 3 D 0 }
+ T{ ##peek f 0 D 0 }
+ T{ ##peek f 1 D 1 }
+ T{ ##load-immediate f 2 0 }
+ T{ ##copy f 3 0 any-rep }
+ T{ ##replace f 3 D 0 }
}
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##peek f V int-rep 1 D 1 }
- T{ ##sub f V int-rep 2 V int-rep 1 V int-rep 1 }
- T{ ##add f V int-rep 3 V int-rep 0 V int-rep 2 }
- T{ ##replace f V int-rep 3 D 0 }
+ T{ ##peek f 0 D 0 }
+ T{ ##peek f 1 D 1 }
+ T{ ##sub f 2 1 1 }
+ T{ ##add f 3 0 2 }
+ T{ ##replace f 3 D 0 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##peek f V int-rep 1 D 1 }
- T{ ##load-immediate f V int-rep 2 0 }
- T{ ##copy f V int-rep 3 V int-rep 0 int-rep }
- T{ ##replace f V int-rep 3 D 0 }
+ T{ ##peek f 0 D 0 }
+ T{ ##peek f 1 D 1 }
+ T{ ##load-immediate f 2 0 }
+ T{ ##copy f 3 0 any-rep }
+ T{ ##replace f 3 D 0 }
}
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##peek f V int-rep 1 D 1 }
- T{ ##sub f V int-rep 2 V int-rep 1 V int-rep 1 }
- T{ ##sub f V int-rep 3 V int-rep 0 V int-rep 2 }
- T{ ##replace f V int-rep 3 D 0 }
+ T{ ##peek f 0 D 0 }
+ T{ ##peek f 1 D 1 }
+ T{ ##sub f 2 1 1 }
+ T{ ##sub f 3 0 2 }
+ T{ ##replace f 3 D 0 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##peek f V int-rep 1 D 1 }
- T{ ##load-immediate f V int-rep 2 0 }
- T{ ##copy f V int-rep 3 V int-rep 0 int-rep }
- T{ ##replace f V int-rep 3 D 0 }
+ T{ ##peek f 0 D 0 }
+ T{ ##peek f 1 D 1 }
+ T{ ##load-immediate f 2 0 }
+ T{ ##copy f 3 0 any-rep }
+ T{ ##replace f 3 D 0 }
}
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##peek f V int-rep 1 D 1 }
- T{ ##sub f V int-rep 2 V int-rep 1 V int-rep 1 }
- T{ ##or f V int-rep 3 V int-rep 0 V int-rep 2 }
- T{ ##replace f V int-rep 3 D 0 }
+ T{ ##peek f 0 D 0 }
+ T{ ##peek f 1 D 1 }
+ T{ ##sub f 2 1 1 }
+ T{ ##or f 3 0 2 }
+ T{ ##replace f 3 D 0 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##peek f V int-rep 1 D 1 }
- T{ ##load-immediate f V int-rep 2 0 }
- T{ ##copy f V int-rep 3 V int-rep 0 int-rep }
- T{ ##replace f V int-rep 3 D 0 }
+ T{ ##peek f 0 D 0 }
+ T{ ##peek f 1 D 1 }
+ T{ ##load-immediate f 2 0 }
+ T{ ##copy f 3 0 any-rep }
+ T{ ##replace f 3 D 0 }
}
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##peek f V int-rep 1 D 1 }
- T{ ##sub f V int-rep 2 V int-rep 1 V int-rep 1 }
- T{ ##xor f V int-rep 3 V int-rep 0 V int-rep 2 }
- T{ ##replace f V int-rep 3 D 0 }
+ T{ ##peek f 0 D 0 }
+ T{ ##peek f 1 D 1 }
+ T{ ##sub f 2 1 1 }
+ T{ ##xor f 3 0 2 }
+ T{ ##replace f 3 D 0 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 1 }
- T{ ##copy f V int-rep 2 V int-rep 0 int-rep }
- T{ ##replace f V int-rep 2 D 0 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 1 }
+ T{ ##copy f 2 0 any-rep }
+ T{ ##replace f 2 D 0 }
}
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 1 }
- T{ ##mul f V int-rep 2 V int-rep 0 V int-rep 1 }
- T{ ##replace f V int-rep 2 D 0 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 1 }
+ T{ ##mul f 2 0 1 }
+ T{ ##replace f 2 D 0 }
} value-numbering-step
] unit-test
! Constant folding
[
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 1 }
- T{ ##load-immediate f V int-rep 2 3 }
- T{ ##load-immediate f V int-rep 3 4 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 1 }
+ T{ ##load-immediate f 2 3 }
+ T{ ##load-immediate f 3 4 }
}
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 1 }
- T{ ##load-immediate f V int-rep 2 3 }
- T{ ##add f V int-rep 3 V int-rep 1 V int-rep 2 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 1 }
+ T{ ##load-immediate f 2 3 }
+ T{ ##add f 3 1 2 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 1 }
- T{ ##load-immediate f V int-rep 2 3 }
- T{ ##load-immediate f V int-rep 3 -2 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 1 }
+ T{ ##load-immediate f 2 3 }
+ T{ ##load-immediate f 3 -2 }
}
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 1 }
- T{ ##load-immediate f V int-rep 2 3 }
- T{ ##sub f V int-rep 3 V int-rep 1 V int-rep 2 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 1 }
+ T{ ##load-immediate f 2 3 }
+ T{ ##sub f 3 1 2 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 2 }
- T{ ##load-immediate f V int-rep 2 3 }
- T{ ##load-immediate f V int-rep 3 6 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 2 }
+ T{ ##load-immediate f 2 3 }
+ T{ ##load-immediate f 3 6 }
}
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 2 }
- T{ ##load-immediate f V int-rep 2 3 }
- T{ ##mul f V int-rep 3 V int-rep 1 V int-rep 2 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 2 }
+ T{ ##load-immediate f 2 3 }
+ T{ ##mul f 3 1 2 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 2 }
- T{ ##load-immediate f V int-rep 2 1 }
- T{ ##load-immediate f V int-rep 3 0 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 2 }
+ T{ ##load-immediate f 2 1 }
+ T{ ##load-immediate f 3 0 }
}
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 2 }
- T{ ##load-immediate f V int-rep 2 1 }
- T{ ##and f V int-rep 3 V int-rep 1 V int-rep 2 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 2 }
+ T{ ##load-immediate f 2 1 }
+ T{ ##and f 3 1 2 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 2 }
- T{ ##load-immediate f V int-rep 2 1 }
- T{ ##load-immediate f V int-rep 3 3 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 2 }
+ T{ ##load-immediate f 2 1 }
+ T{ ##load-immediate f 3 3 }
}
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 2 }
- T{ ##load-immediate f V int-rep 2 1 }
- T{ ##or f V int-rep 3 V int-rep 1 V int-rep 2 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 2 }
+ T{ ##load-immediate f 2 1 }
+ T{ ##or f 3 1 2 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 2 }
- T{ ##load-immediate f V int-rep 2 3 }
- T{ ##load-immediate f V int-rep 3 1 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 2 }
+ T{ ##load-immediate f 2 3 }
+ T{ ##load-immediate f 3 1 }
}
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 2 }
- T{ ##load-immediate f V int-rep 2 3 }
- T{ ##xor f V int-rep 3 V int-rep 1 V int-rep 2 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 2 }
+ T{ ##load-immediate f 2 3 }
+ T{ ##xor f 3 1 2 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 1 }
- T{ ##load-immediate f V int-rep 3 8 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 1 }
+ T{ ##load-immediate f 3 8 }
}
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 1 }
- T{ ##shl-imm f V int-rep 3 V int-rep 1 3 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 1 }
+ T{ ##shl-imm f 3 1 3 }
} value-numbering-step
] unit-test
cell 8 = [
[
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 -1 }
- T{ ##load-immediate f V int-rep 3 HEX: ffffffffffff }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 -1 }
+ T{ ##load-immediate f 3 HEX: ffffffffffff }
}
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 -1 }
- T{ ##shr-imm f V int-rep 3 V int-rep 1 16 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 -1 }
+ T{ ##shr-imm f 3 1 16 }
} value-numbering-step
] unit-test
] when
[
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 -8 }
- T{ ##load-immediate f V int-rep 3 -4 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 -8 }
+ T{ ##load-immediate f 3 -4 }
}
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 -8 }
- T{ ##sar-imm f V int-rep 3 V int-rep 1 1 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 -8 }
+ T{ ##sar-imm f 3 1 1 }
} value-numbering-step
] unit-test
cell 8 = [
[
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 65536 }
- T{ ##load-immediate f V int-rep 2 140737488355328 }
- T{ ##add f V int-rep 3 V int-rep 0 V int-rep 2 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 65536 }
+ T{ ##load-immediate f 2 140737488355328 }
+ T{ ##add f 3 0 2 }
}
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 65536 }
- T{ ##shl-imm f V int-rep 2 V int-rep 1 31 }
- T{ ##add f V int-rep 3 V int-rep 0 V int-rep 2 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 65536 }
+ T{ ##shl-imm f 2 1 31 }
+ T{ ##add f 3 0 2 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 2 140737488355328 }
- T{ ##add f V int-rep 3 V int-rep 0 V int-rep 2 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 2 140737488355328 }
+ T{ ##add f 3 0 2 }
}
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 2 140737488355328 }
- T{ ##add f V int-rep 3 V int-rep 0 V int-rep 2 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 2 140737488355328 }
+ T{ ##add f 3 0 2 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 2 2147483647 }
- T{ ##add-imm f V int-rep 3 V int-rep 0 2147483647 }
- T{ ##add-imm f V int-rep 4 V int-rep 3 2147483647 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 2 2147483647 }
+ T{ ##add-imm f 3 0 2147483647 }
+ T{ ##add-imm f 4 3 2147483647 }
}
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 2 2147483647 }
- T{ ##add f V int-rep 3 V int-rep 0 V int-rep 2 }
- T{ ##add f V int-rep 4 V int-rep 3 V int-rep 2 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 2 2147483647 }
+ T{ ##add f 3 0 2 }
+ T{ ##add f 4 3 2 }
} value-numbering-step
] unit-test
] when
! Branch folding
[
{
- T{ ##load-immediate f V int-rep 1 1 }
- T{ ##load-immediate f V int-rep 2 2 }
- T{ ##load-immediate f V int-rep 3 5 }
+ T{ ##load-immediate f 1 1 }
+ T{ ##load-immediate f 2 2 }
+ T{ ##load-immediate f 3 5 }
}
] [
{
- T{ ##load-immediate f V int-rep 1 1 }
- T{ ##load-immediate f V int-rep 2 2 }
- T{ ##compare f V int-rep 3 V int-rep 1 V int-rep 2 cc= }
+ T{ ##load-immediate f 1 1 }
+ T{ ##load-immediate f 2 2 }
+ T{ ##compare f 3 1 2 cc= }
} value-numbering-step
] unit-test
[
{
- T{ ##load-immediate f V int-rep 1 1 }
- T{ ##load-immediate f V int-rep 2 2 }
- T{ ##load-reference f V int-rep 3 t }
+ T{ ##load-immediate f 1 1 }
+ T{ ##load-immediate f 2 2 }
+ T{ ##load-reference f 3 t }
}
] [
{
- T{ ##load-immediate f V int-rep 1 1 }
- T{ ##load-immediate f V int-rep 2 2 }
- T{ ##compare f V int-rep 3 V int-rep 1 V int-rep 2 cc/= }
+ T{ ##load-immediate f 1 1 }
+ T{ ##load-immediate f 2 2 }
+ T{ ##compare f 3 1 2 cc/= }
} value-numbering-step
] unit-test
[
{
- T{ ##load-immediate f V int-rep 1 1 }
- T{ ##load-immediate f V int-rep 2 2 }
- T{ ##load-reference f V int-rep 3 t }
+ T{ ##load-immediate f 1 1 }
+ T{ ##load-immediate f 2 2 }
+ T{ ##load-reference f 3 t }
}
] [
{
- T{ ##load-immediate f V int-rep 1 1 }
- T{ ##load-immediate f V int-rep 2 2 }
- T{ ##compare f V int-rep 3 V int-rep 1 V int-rep 2 cc< }
+ T{ ##load-immediate f 1 1 }
+ T{ ##load-immediate f 2 2 }
+ T{ ##compare f 3 1 2 cc< }
} value-numbering-step
] unit-test
[
{
- T{ ##load-immediate f V int-rep 1 1 }
- T{ ##load-immediate f V int-rep 2 2 }
- T{ ##load-immediate f V int-rep 3 5 }
+ T{ ##load-immediate f 1 1 }
+ T{ ##load-immediate f 2 2 }
+ T{ ##load-immediate f 3 5 }
}
] [
{
- T{ ##load-immediate f V int-rep 1 1 }
- T{ ##load-immediate f V int-rep 2 2 }
- T{ ##compare f V int-rep 3 V int-rep 2 V int-rep 1 cc< }
+ T{ ##load-immediate f 1 1 }
+ T{ ##load-immediate f 2 2 }
+ T{ ##compare f 3 2 1 cc< }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 5 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 5 }
}
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##compare f V int-rep 1 V int-rep 0 V int-rep 0 cc< }
+ T{ ##peek f 0 D 0 }
+ T{ ##compare f 1 0 0 cc< }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-reference f V int-rep 1 t }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-reference f 1 t }
}
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##compare f V int-rep 1 V int-rep 0 V int-rep 0 cc<= }
+ T{ ##peek f 0 D 0 }
+ T{ ##compare f 1 0 0 cc<= }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 5 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 5 }
}
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##compare f V int-rep 1 V int-rep 0 V int-rep 0 cc> }
+ T{ ##peek f 0 D 0 }
+ T{ ##compare f 1 0 0 cc> }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-reference f V int-rep 1 t }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-reference f 1 t }
}
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##compare f V int-rep 1 V int-rep 0 V int-rep 0 cc>= }
+ T{ ##peek f 0 D 0 }
+ T{ ##compare f 1 0 0 cc>= }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-immediate f V int-rep 1 5 }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-immediate f 1 5 }
}
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##compare f V int-rep 1 V int-rep 0 V int-rep 0 cc/= }
+ T{ ##peek f 0 D 0 }
+ T{ ##compare f 1 0 0 cc/= }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-reference f V int-rep 1 t }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-reference f 1 t }
}
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##compare f V int-rep 1 V int-rep 0 V int-rep 0 cc= }
+ T{ ##peek f 0 D 0 }
+ T{ ##compare f 1 0 0 cc= }
} value-numbering-step
] unit-test
[
{
- T{ ##load-immediate f V int-rep 1 1 }
- T{ ##load-immediate f V int-rep 2 2 }
+ T{ ##load-immediate f 1 1 }
+ T{ ##load-immediate f 2 2 }
T{ ##branch }
}
1
] [
{
- T{ ##load-immediate f V int-rep 1 1 }
- T{ ##load-immediate f V int-rep 2 2 }
- T{ ##compare-branch f V int-rep 1 V int-rep 2 cc= }
+ T{ ##load-immediate f 1 1 }
+ T{ ##load-immediate f 2 2 }
+ T{ ##compare-branch f 1 2 cc= }
} test-branch-folding
] unit-test
[
{
- T{ ##load-immediate f V int-rep 1 1 }
- T{ ##load-immediate f V int-rep 2 2 }
+ T{ ##load-immediate f 1 1 }
+ T{ ##load-immediate f 2 2 }
T{ ##branch }
}
0
] [
{
- T{ ##load-immediate f V int-rep 1 1 }
- T{ ##load-immediate f V int-rep 2 2 }
- T{ ##compare-branch f V int-rep 1 V int-rep 2 cc/= }
+ T{ ##load-immediate f 1 1 }
+ T{ ##load-immediate f 2 2 }
+ T{ ##compare-branch f 1 2 cc/= }
} test-branch-folding
] unit-test
[
{
- T{ ##load-immediate f V int-rep 1 1 }
- T{ ##load-immediate f V int-rep 2 2 }
+ T{ ##load-immediate f 1 1 }
+ T{ ##load-immediate f 2 2 }
T{ ##branch }
}
0
] [
{
- T{ ##load-immediate f V int-rep 1 1 }
- T{ ##load-immediate f V int-rep 2 2 }
- T{ ##compare-branch f V int-rep 1 V int-rep 2 cc< }
+ T{ ##load-immediate f 1 1 }
+ T{ ##load-immediate f 2 2 }
+ T{ ##compare-branch f 1 2 cc< }
} test-branch-folding
] unit-test
[
{
- T{ ##load-immediate f V int-rep 1 1 }
- T{ ##load-immediate f V int-rep 2 2 }
+ T{ ##load-immediate f 1 1 }
+ T{ ##load-immediate f 2 2 }
T{ ##branch }
}
1
] [
{
- T{ ##load-immediate f V int-rep 1 1 }
- T{ ##load-immediate f V int-rep 2 2 }
- T{ ##compare-branch f V int-rep 2 V int-rep 1 cc< }
+ T{ ##load-immediate f 1 1 }
+ T{ ##load-immediate f 2 2 }
+ T{ ##compare-branch f 2 1 cc< }
} test-branch-folding
] unit-test
[
{
- T{ ##peek f V int-rep 0 D 0 }
+ T{ ##peek f 0 D 0 }
T{ ##branch }
}
1
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##compare-branch f V int-rep 0 V int-rep 0 cc< }
+ T{ ##peek f 0 D 0 }
+ T{ ##compare-branch f 0 0 cc< }
} test-branch-folding
] unit-test
[
{
- T{ ##peek f V int-rep 0 D 0 }
+ T{ ##peek f 0 D 0 }
T{ ##branch }
}
0
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##compare-branch f V int-rep 0 V int-rep 0 cc<= }
+ T{ ##peek f 0 D 0 }
+ T{ ##compare-branch f 0 0 cc<= }
} test-branch-folding
] unit-test
[
{
- T{ ##peek f V int-rep 0 D 0 }
+ T{ ##peek f 0 D 0 }
T{ ##branch }
}
1
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##compare-branch f V int-rep 0 V int-rep 0 cc> }
+ T{ ##peek f 0 D 0 }
+ T{ ##compare-branch f 0 0 cc> }
} test-branch-folding
] unit-test
[
{
- T{ ##peek f V int-rep 0 D 0 }
+ T{ ##peek f 0 D 0 }
T{ ##branch }
}
0
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##compare-branch f V int-rep 0 V int-rep 0 cc>= }
+ T{ ##peek f 0 D 0 }
+ T{ ##compare-branch f 0 0 cc>= }
} test-branch-folding
] unit-test
[
{
- T{ ##peek f V int-rep 0 D 0 }
+ T{ ##peek f 0 D 0 }
T{ ##branch }
}
0
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##compare-branch f V int-rep 0 V int-rep 0 cc= }
+ T{ ##peek f 0 D 0 }
+ T{ ##compare-branch f 0 0 cc= }
} test-branch-folding
] unit-test
[
{
- T{ ##peek f V int-rep 0 D 0 }
+ T{ ##peek f 0 D 0 }
T{ ##branch }
}
1
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##compare-branch f V int-rep 0 V int-rep 0 cc/= }
+ T{ ##peek f 0 D 0 }
+ T{ ##compare-branch f 0 0 cc/= }
} test-branch-folding
] unit-test
[
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##load-reference f V int-rep 1 t }
+ T{ ##peek f 0 D 0 }
+ T{ ##load-reference f 1 t }
T{ ##branch }
}
0
] [
{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##compare f V int-rep 1 V int-rep 0 V int-rep 0 cc<= }
- T{ ##compare-imm-branch f V int-rep 1 5 cc/= }
+ T{ ##peek f 0 D 0 }
+ T{ ##compare f 1 0 0 cc<= }
+ T{ ##compare-imm-branch f 1 5 cc/= }
} test-branch-folding
] unit-test
V{ T{ ##branch } } 0 test-bb
V{
- T{ ##peek f V int-rep 0 D 0 }
- T{ ##compare-branch f V int-rep 0 V int-rep 0 cc< }
+ T{ ##peek f 0 D 0 }
+ T{ ##compare-branch f 0 0 cc< }
} 1 test-bb
V{
- T{ ##load-immediate f V int-rep 1 1 }
+ T{ ##load-immediate f 1 1 }
T{ ##branch }
} 2 test-bb
V{
- T{ ##load-immediate f V int-rep 2 2 }
+ T{ ##load-immediate f 2 2 }
T{ ##branch }
} 3 test-bb
V{
- T{ ##phi f V int-rep 3 H{ { 2 V int-rep 1 } { 3 V int-rep 2 } } }
- T{ ##replace f V int-rep 3 D 0 }
+ T{ ##phi f 3 H{ { 2 1 } { 3 2 } } }
+ T{ ##replace f 3 D 0 }
T{ ##return }
} 4 test-bb
test-diamond
[ ] [
- cfg new 0 get >>entry
+ cfg new 0 get >>entry dup cfg set
value-numbering
compute-predecessors
+ detect-loops
+ select-representations
destruct-ssa drop
] unit-test
[ 2 ] [ 4 get instructions>> length ] unit-test
V{
- T{ ##peek f V int-rep 0 D 0 }
+ T{ ##peek f 0 D 0 }
T{ ##branch }
} 0 test-bb
V{
- T{ ##peek f V int-rep 1 D 1 }
- T{ ##compare-branch f V int-rep 1 V int-rep 1 cc< }
+ T{ ##peek f 1 D 1 }
+ T{ ##compare-branch f 1 1 cc< }
} 1 test-bb
V{
- T{ ##copy f V int-rep 2 V int-rep 0 int-rep }
+ T{ ##copy f 2 0 any-rep }
T{ ##branch }
} 2 test-bb
V{
- T{ ##phi f V int-rep 3 V{ } }
+ T{ ##phi f 3 V{ } }
T{ ##branch }
} 3 test-bb
V{
- T{ ##replace f V int-rep 3 D 0 }
+ T{ ##replace f 3 D 0 }
T{ ##return }
} 4 test-bb
-1 get V int-rep 1 2array
-2 get V int-rep 0 2array 2array 3 get instructions>> first (>>inputs)
+1 get 1 2array
+2 get 0 2array 2array 3 get instructions>> first (>>inputs)
test-diamond
V{ T{ ##prologue } T{ ##branch } } 0 test-bb
V{
- T{ ##peek { dst V int-rep 15 } { loc D 0 } }
- T{ ##copy { dst V int-rep 16 } { src V int-rep 15 } { rep int-rep } }
- T{ ##copy { dst V int-rep 17 } { src V int-rep 15 } { rep int-rep } }
- T{ ##copy { dst V int-rep 18 } { src V int-rep 15 } { rep int-rep } }
- T{ ##copy { dst V int-rep 19 } { src V int-rep 15 } { rep int-rep } }
+ T{ ##peek { dst 15 } { loc D 0 } }
+ T{ ##copy { dst 16 } { src 15 } { rep any-rep } }
+ T{ ##copy { dst 17 } { src 15 } { rep any-rep } }
+ T{ ##copy { dst 18 } { src 15 } { rep any-rep } }
+ T{ ##copy { dst 19 } { src 15 } { rep any-rep } }
T{ ##compare
- { dst V int-rep 20 }
- { src1 V int-rep 18 }
- { src2 V int-rep 19 }
+ { dst 20 }
+ { src1 18 }
+ { src2 19 }
{ cc cc= }
- { temp V int-rep 22 }
+ { temp 22 }
}
- T{ ##copy { dst V int-rep 21 } { src V int-rep 20 } { rep int-rep } }
+ T{ ##copy { dst 21 } { src 20 } { rep any-rep } }
T{ ##compare-imm-branch
- { src1 V int-rep 21 }
+ { src1 21 }
{ src2 5 }
{ cc cc/= }
}
} 1 test-bb
V{
- T{ ##copy { dst V int-rep 23 } { src V int-rep 15 } { rep int-rep } }
- T{ ##copy { dst V int-rep 24 } { src V int-rep 15 } { rep int-rep } }
- T{ ##load-reference { dst V int-rep 25 } { obj t } }
+ T{ ##copy { dst 23 } { src 15 } { rep any-rep } }
+ T{ ##copy { dst 24 } { src 15 } { rep any-rep } }
+ T{ ##load-reference { dst 25 } { obj t } }
T{ ##branch }
} 2 test-bb
V{
- T{ ##replace { src V int-rep 25 } { loc D 0 } }
+ T{ ##replace { src 25 } { loc D 0 } }
T{ ##epilogue }
T{ ##return }
} 3 test-bb
V{
- T{ ##copy { dst V int-rep 26 } { src V int-rep 15 } { rep int-rep } }
- T{ ##copy { dst V int-rep 27 } { src V int-rep 15 } { rep int-rep } }
+ T{ ##copy { dst 26 } { src 15 } { rep any-rep } }
+ T{ ##copy { dst 27 } { src 15 } { rep any-rep } }
T{ ##add
- { dst V int-rep 28 }
- { src1 V int-rep 26 }
- { src2 V int-rep 27 }
+ { dst 28 }
+ { src1 26 }
+ { src2 27 }
}
T{ ##branch }
} 4 test-bb
V{
- T{ ##replace { src V int-rep 28 } { loc D 0 } }
+ T{ ##replace { src 28 } { loc D 0 } }
T{ ##epilogue }
T{ ##return }
} 5 test-bb
! See http://factorcode.org/license.txt for BSD license.
USING: namespaces assocs kernel accessors
sorting sets sequences
+cpu.architecture
compiler.cfg
compiler.cfg.rpo
compiler.cfg.instructions
! Local value numbering. Predecessors must be recomputed after this
: >copy ( insn -- insn/##copy )
dup dst>> dup vreg>vn vn>vreg
- 2dup eq? [ 2drop ] [ dup rep>> \ ##copy new-insn nip ] if ;
+ 2dup eq? [ 2drop ] [ any-rep \ ##copy new-insn nip ] if ;
: rewrite-loop ( insn -- insn' )
dup rewrite [ rewrite-loop ] [ ] ?if ;
[
V{
- T{ ##peek f V int-regs 4 D 0 f }
- T{ ##allot f V int-regs 7 24 array V int-regs 8 f }
- T{ ##load-immediate f V int-regs 9 8 f }
- T{ ##set-slot-imm f V int-regs 9 V int-regs 7 1 3 f }
- T{ ##set-slot-imm f V int-regs 4 V int-regs 7 2 3 f }
- T{ ##replace f V int-regs 7 D 0 f }
+ T{ ##peek f 4 D 0 f }
+ T{ ##allot f 7 24 array 8 f }
+ T{ ##load-immediate f 9 8 f }
+ T{ ##set-slot-imm f 9 7 1 3 f }
+ T{ ##set-slot-imm f 4 7 2 3 f }
+ T{ ##replace f 7 D 0 f }
T{ ##branch }
}
] [
{
- T{ ##peek f V int-regs 4 D 0 }
- T{ ##allot f V int-regs 7 24 array V int-regs 8 }
- T{ ##load-immediate f V int-regs 9 8 }
- T{ ##set-slot-imm f V int-regs 9 V int-regs 7 1 3 }
- T{ ##write-barrier f V int-regs 7 V int-regs 10 V int-regs 11 }
- T{ ##set-slot-imm f V int-regs 4 V int-regs 7 2 3 }
- T{ ##write-barrier f V int-regs 7 V int-regs 12 V int-regs 13 }
- T{ ##replace f V int-regs 7 D 0 }
+ T{ ##peek f 4 D 0 }
+ T{ ##allot f 7 24 array 8 }
+ T{ ##load-immediate f 9 8 }
+ T{ ##set-slot-imm f 9 7 1 3 }
+ T{ ##write-barrier f 7 10 11 }
+ T{ ##set-slot-imm f 4 7 2 3 }
+ T{ ##write-barrier f 7 12 13 }
+ T{ ##replace f 7 D 0 }
} test-write-barrier
] unit-test
[
V{
- T{ ##load-immediate f V int-regs 4 24 }
- T{ ##peek f V int-regs 5 D -1 }
- T{ ##peek f V int-regs 6 D -2 }
- T{ ##set-slot-imm f V int-regs 5 V int-regs 6 3 2 }
- T{ ##write-barrier f V int-regs 6 V int-regs 7 V int-regs 8 }
+ T{ ##load-immediate f 4 24 }
+ T{ ##peek f 5 D -1 }
+ T{ ##peek f 6 D -2 }
+ T{ ##set-slot-imm f 5 6 3 2 }
+ T{ ##write-barrier f 6 7 8 }
T{ ##branch }
}
] [
{
- T{ ##load-immediate f V int-regs 4 24 }
- T{ ##peek f V int-regs 5 D -1 }
- T{ ##peek f V int-regs 6 D -2 }
- T{ ##set-slot-imm f V int-regs 5 V int-regs 6 3 2 }
- T{ ##write-barrier f V int-regs 6 V int-regs 7 V int-regs 8 }
+ T{ ##load-immediate f 4 24 }
+ T{ ##peek f 5 D -1 }
+ T{ ##peek f 6 D -2 }
+ T{ ##set-slot-imm f 5 6 3 2 }
+ T{ ##write-barrier f 6 7 8 }
} test-write-barrier
] unit-test
[
V{
- T{ ##peek f V int-regs 19 D -3 }
- T{ ##peek f V int-regs 22 D -2 }
- T{ ##set-slot-imm f V int-regs 22 V int-regs 19 3 2 }
- T{ ##write-barrier f V int-regs 19 V int-regs 24 V int-regs 25 }
- T{ ##peek f V int-regs 28 D -1 }
- T{ ##set-slot-imm f V int-regs 28 V int-regs 19 4 2 }
+ T{ ##peek f 19 D -3 }
+ T{ ##peek f 22 D -2 }
+ T{ ##set-slot-imm f 22 19 3 2 }
+ T{ ##write-barrier f 19 24 25 }
+ T{ ##peek f 28 D -1 }
+ T{ ##set-slot-imm f 28 19 4 2 }
T{ ##branch }
}
] [
{
- T{ ##peek f V int-regs 19 D -3 }
- T{ ##peek f V int-regs 22 D -2 }
- T{ ##set-slot-imm f V int-regs 22 V int-regs 19 3 2 }
- T{ ##write-barrier f V int-regs 19 V int-regs 24 V int-regs 25 }
- T{ ##peek f V int-regs 28 D -1 }
- T{ ##set-slot-imm f V int-regs 28 V int-regs 19 4 2 }
- T{ ##write-barrier f V int-regs 19 V int-regs 30 V int-regs 3 }
+ T{ ##peek f 19 D -3 }
+ T{ ##peek f 22 D -2 }
+ T{ ##set-slot-imm f 22 19 3 2 }
+ T{ ##write-barrier f 19 24 25 }
+ T{ ##peek f 28 D -1 }
+ T{ ##set-slot-imm f 28 19 4 2 }
+ T{ ##write-barrier f 19 30 3 }
} test-write-barrier
] unit-test
[ associate >alist modify-code-heap ] keep ;
: compile-test-cfg ( -- word )
- cfg new
- 0 get >>entry
+ cfg new 0 get >>entry
+ dup fake-representations representations get >>reps
compile-cfg ;
: compile-test-bb ( insns -- result )
V{ T{ ##prologue } T{ ##branch } } 0 test-bb
V{
T{ ##inc-d f 1 }
- T{ ##replace f V int-rep 0 D 0 }
+ T{ ##replace f 0 D 0 }
T{ ##branch }
} [ clone ] map append 1 test-bb
V{
! loading immediates
[ f ] [
V{
- T{ ##load-immediate f V int-rep 0 5 }
+ T{ ##load-immediate f 0 5 }
} compile-test-bb
] unit-test
[ "hello" ] [
V{
- T{ ##load-reference f V int-rep 0 "hello" }
+ T{ ##load-reference f 0 "hello" }
} compile-test-bb
] unit-test
! one of the sources
[ t ] [
V{
- T{ ##load-immediate f V int-rep 1 $[ 2 cell log2 shift ] }
- T{ ##load-reference f V int-rep 0 { t f t } }
- T{ ##slot f V int-rep 0 V int-rep 0 V int-rep 1 $[ array tag-number ] V int-rep 2 }
+ T{ ##load-immediate f 1 $[ 2 cell log2 shift ] }
+ T{ ##load-reference f 0 { t f t } }
+ T{ ##slot f 0 0 1 $[ array tag-number ] 2 }
} compile-test-bb
] unit-test
[ t ] [
V{
- T{ ##load-reference f V int-rep 0 { t f t } }
- T{ ##slot-imm f V int-rep 0 V int-rep 0 2 $[ array tag-number ] V int-rep 2 }
+ T{ ##load-reference f 0 { t f t } }
+ T{ ##slot-imm f 0 0 2 $[ array tag-number ] 2 }
} compile-test-bb
] unit-test
[ t ] [
V{
- T{ ##load-immediate f V int-rep 1 $[ 2 cell log2 shift ] }
- T{ ##load-reference f V int-rep 0 { t f t } }
- T{ ##set-slot f V int-rep 0 V int-rep 0 V int-rep 1 $[ array tag-number ] V int-rep 2 }
+ T{ ##load-immediate f 1 $[ 2 cell log2 shift ] }
+ T{ ##load-reference f 0 { t f t } }
+ T{ ##set-slot f 0 0 1 $[ array tag-number ] 2 }
} compile-test-bb
dup first eq?
] unit-test
[ t ] [
V{
- T{ ##load-reference f V int-rep 0 { t f t } }
- T{ ##set-slot-imm f V int-rep 0 V int-rep 0 2 $[ array tag-number ] }
+ T{ ##load-reference f 0 { t f t } }
+ T{ ##set-slot-imm f 0 0 2 $[ array tag-number ] }
} compile-test-bb
dup first eq?
] unit-test
[ 8 ] [
V{
- T{ ##load-immediate f V int-rep 0 4 }
- T{ ##shl f V int-rep 0 V int-rep 0 V int-rep 0 }
+ T{ ##load-immediate f 0 4 }
+ T{ ##shl f 0 0 0 }
} compile-test-bb
] unit-test
[ 4 ] [
V{
- T{ ##load-immediate f V int-rep 0 4 }
- T{ ##shl-imm f V int-rep 0 V int-rep 0 3 }
+ T{ ##load-immediate f 0 4 }
+ T{ ##shl-imm f 0 0 3 }
} compile-test-bb
] unit-test
[ 31 ] [
V{
- T{ ##load-reference f V int-rep 1 B{ 31 67 52 } }
- T{ ##unbox-any-c-ptr f V int-rep 0 V int-rep 1 V int-rep 2 }
- T{ ##alien-unsigned-1 f V int-rep 0 V int-rep 0 }
- T{ ##shl-imm f V int-rep 0 V int-rep 0 3 }
+ T{ ##load-reference f 1 B{ 31 67 52 } }
+ T{ ##unbox-any-c-ptr f 0 1 2 }
+ T{ ##alien-unsigned-1 f 0 0 }
+ T{ ##shl-imm f 0 0 3 }
} compile-test-bb
] unit-test
[ CHAR: l ] [
V{
- T{ ##load-reference f V int-rep 0 "hello world" }
- T{ ##load-immediate f V int-rep 1 3 }
- T{ ##string-nth f V int-rep 0 V int-rep 0 V int-rep 1 V int-rep 2 }
- T{ ##shl-imm f V int-rep 0 V int-rep 0 3 }
+ T{ ##load-reference f 0 "hello world" }
+ T{ ##load-immediate f 1 3 }
+ T{ ##string-nth f 0 0 1 2 }
+ T{ ##shl-imm f 0 0 3 }
} compile-test-bb
] unit-test
[ 1 ] [
V{
- T{ ##load-immediate f V int-rep 0 16 }
- T{ ##add-imm f V int-rep 0 V int-rep 0 -8 }
+ T{ ##load-immediate f 0 16 }
+ T{ ##add-imm f 0 0 -8 }
} compile-test-bb
] unit-test
[ 100 ] [
V{
- T{ ##load-immediate f V int-rep 0 100 }
- T{ ##integer>bignum f V int-rep 0 V int-rep 0 V int-rep 1 }
+ T{ ##load-immediate f 0 100 }
+ T{ ##integer>bignum f 0 0 1 }
} compile-test-bb
] unit-test
[ 1 ] [
V{
- T{ ##load-reference f V int-rep 0 ALIEN: 8 }
- T{ ##unbox-any-c-ptr f V int-rep 0 V int-rep 0 V int-rep 1 }
+ T{ ##load-reference f 0 ALIEN: 8 }
+ T{ ##unbox-any-c-ptr f 0 0 1 }
} compile-test-bb
] unit-test
! Representations -- these are like low-level types
-! Integer registers can contain data with one of these two representations
+! Unknown representation; this is used for ##copy instructions which
+! get eliminated later
+SINGLETON: any-rep
+
+! Integer registers can contain data with one of these three representations
+! tagged-rep: tagged pointer or fixnum
+! int-rep: untagged fixnum, not a pointer
SINGLETONS: tagged-rep int-rep ;
! Floating point registers can contain data with
! one of these representations
SINGLETONS: single-float-rep double-float-rep ;
-UNION: representation tagged-rep int-rep single-float-rep double-float-rep ;
+UNION: representation any-rep tagged-rep int-rep single-float-rep double-float-rep ;
! Register classes
SINGLETONS: int-regs float-regs ;
projects / factor.git / commitdiff