1 USING: accessors arrays classes compiler.cfg
2 compiler.cfg.debugger compiler.cfg.instructions
3 compiler.cfg.linear-scan.debugger
4 compiler.cfg.linear-scan.live-intervals
5 compiler.cfg.linear-scan.numbering
6 compiler.cfg.linear-scan.resolve compiler.cfg.predecessors
7 compiler.cfg.registers compiler.cfg.rpo cpu.architecture kernel
8 namespaces tools.test vectors ;
9 IN: compiler.cfg.linear-scan.resolve.tests
12 { 3 4 } V{ 1 2 } clone [ { 5 6 } 3append-here ] keep >array
16 T{ ##peek f V int-regs 0 D 0 }
21 T{ ##replace f V int-regs 0 D 1 }
25 1 get 1vector 0 get (>>successors)
29 dup reverse-post-order number-instructions
32 CONSTANT: test-live-interval-1
37 { ranges V{ T{ live-range f 0 2 } T{ live-range f 4 6 } } }
43 test-live-interval-1 0 get spill-to
47 test-live-interval-1 1 get spill-to
50 CONSTANT: test-live-interval-2
55 { ranges V{ T{ live-range f 0 2 } T{ live-range f 4 6 } } }
61 test-live-interval-2 0 get reload-from
65 test-live-interval-2 1 get reload-from
70 T{ _copy { dst 5 } { src 4 } { class int-regs } }
71 T{ _spill { src 1 } { class int-regs } { n spill-temp } }
72 T{ _copy { dst 1 } { src 0 } { class int-regs } }
73 T{ _reload { dst 0 } { class int-regs } { n spill-temp } }
74 T{ _spill { src 1 } { class float-regs } { n spill-temp } }
75 T{ _copy { dst 1 } { src 0 } { class float-regs } }
76 T{ _reload { dst 0 } { class float-regs } { n spill-temp } }
80 T{ register->register { from 0 } { to 1 } { reg-class int-regs } }
81 T{ register->register { from 1 } { to 0 } { reg-class int-regs } }
82 T{ register->register { from 0 } { to 1 } { reg-class float-regs } }
83 T{ register->register { from 1 } { to 0 } { reg-class float-regs } }
84 T{ register->register { from 4 } { to 5 } { reg-class int-regs } }
85 } mapping-instructions
90 T{ _spill { src 2 } { class int-regs } { n spill-temp } }
91 T{ _copy { dst 2 } { src 1 } { class int-regs } }
92 T{ _copy { dst 1 } { src 0 } { class int-regs } }
93 T{ _reload { dst 0 } { class int-regs } { n spill-temp } }
97 T{ register->register { from 0 } { to 1 } { reg-class int-regs } }
98 T{ register->register { from 1 } { to 2 } { reg-class int-regs } }
99 T{ register->register { from 2 } { to 0 } { reg-class int-regs } }
100 } mapping-instructions
105 T{ _spill { src 0 } { class int-regs } { n spill-temp } }
106 T{ _copy { dst 0 } { src 2 } { class int-regs } }
107 T{ _copy { dst 2 } { src 1 } { class int-regs } }
108 T{ _reload { dst 1 } { class int-regs } { n spill-temp } }
112 T{ register->register { from 1 } { to 2 } { reg-class int-regs } }
113 T{ register->register { from 2 } { to 0 } { reg-class int-regs } }
114 T{ register->register { from 0 } { to 1 } { reg-class int-regs } }
115 } mapping-instructions
120 T{ _copy { dst 1 } { src 0 } { class int-regs } }
121 T{ _copy { dst 2 } { src 0 } { class int-regs } }
125 T{ register->register { from 0 } { to 1 } { reg-class int-regs } }
126 T{ register->register { from 0 } { to 2 } { reg-class int-regs } }
127 } mapping-instructions
134 T{ register->register { from 4 } { to 4 } { reg-class int-regs } }
135 } mapping-instructions
140 T{ _spill { src 3 } { class int-regs } { n 4 } }
141 T{ _reload { dst 2 } { class int-regs } { n 1 } }
145 T{ register->memory { from 3 } { to 4 } { reg-class int-regs } }
146 T{ memory->register { from 1 } { to 2 } { reg-class int-regs } }
147 } mapping-instructions
153 T{ _copy { dst 1 } { src 0 } { class int-regs } }
154 T{ _copy { dst 2 } { src 0 } { class int-regs } }
155 T{ _copy { dst 0 } { src 3 } { class int-regs } }
159 T{ register->register { from 0 } { to 1 } { reg-class int-regs } }
160 T{ register->register { from 3 } { to 0 } { reg-class int-regs } }
161 T{ register->register { from 0 } { to 2 } { reg-class int-regs } }
162 } mapping-instructions
167 T{ _copy { dst 1 } { src 0 } { class int-regs } }
168 T{ _copy { dst 2 } { src 0 } { class int-regs } }
169 T{ _spill { src 4 } { class int-regs } { n spill-temp } }
170 T{ _copy { dst 4 } { src 0 } { class int-regs } }
171 T{ _copy { dst 0 } { src 3 } { class int-regs } }
172 T{ _reload { dst 3 } { class int-regs } { n spill-temp } }
176 T{ register->register { from 0 } { to 1 } { reg-class int-regs } }
177 T{ register->register { from 0 } { to 2 } { reg-class int-regs } }
178 T{ register->register { from 3 } { to 0 } { reg-class int-regs } }
179 T{ register->register { from 4 } { to 3 } { reg-class int-regs } }
180 T{ register->register { from 0 } { to 4 } { reg-class int-regs } }
181 } mapping-instructions
186 T{ _copy { dst 2 } { src 0 } { class int-regs } }
187 T{ _copy { dst 9 } { src 1 } { class int-regs } }
188 T{ _copy { dst 1 } { src 0 } { class int-regs } }
189 T{ _spill { src 4 } { class int-regs } { n spill-temp } }
190 T{ _copy { dst 4 } { src 0 } { class int-regs } }
191 T{ _copy { dst 0 } { src 3 } { class int-regs } }
192 T{ _reload { dst 3 } { class int-regs } { n spill-temp } }
196 T{ register->register { from 0 } { to 1 } { reg-class int-regs } }
197 T{ register->register { from 0 } { to 2 } { reg-class int-regs } }
198 T{ register->register { from 1 } { to 9 } { reg-class int-regs } }
199 T{ register->register { from 3 } { to 0 } { reg-class int-regs } }
200 T{ register->register { from 4 } { to 3 } { reg-class int-regs } }
201 T{ register->register { from 0 } { to 4 } { reg-class int-regs } }
202 } mapping-instructions