1 USING: accessors arrays classes compiler.cfg
2 compiler.cfg.instructions compiler.cfg.linear-scan.debugger
3 compiler.cfg.linear-scan.live-intervals
4 compiler.cfg.linear-scan.numbering
5 compiler.cfg.linear-scan.resolve compiler.cfg.predecessors
6 compiler.cfg.registers compiler.cfg.rpo cpu.architecture kernel
7 multiline namespaces tools.test vectors ;
8 IN: compiler.cfg.linear-scan.resolve.tests
11 { 3 4 } V{ 1 2 } clone [ { 5 6 } 3append-here ] keep >array
15 T{ ##peek f V int-regs 0 D 0 }
20 T{ ##replace f V int-regs 0 D 1 }
24 1 get 1vector 0 get (>>successors)
28 dup reverse-post-order number-instructions
31 CONSTANT: test-live-interval-1
36 { ranges V{ T{ live-range f 0 2 } T{ live-range f 4 6 } } }
42 0 get test-live-interval-1 spill-to
46 1 get test-live-interval-1 spill-to
49 CONSTANT: test-live-interval-2
54 { ranges V{ T{ live-range f 0 2 } T{ live-range f 4 6 } } }
60 0 get test-live-interval-2 reload-from
64 1 get test-live-interval-2 reload-from
69 T{ register->register { from 1 } { to 2 } { reg-class int-regs } }
70 T{ register->register { from 0 } { to 1 } { reg-class int-regs } }
74 T{ register->register { from 0 } { to 1 } { reg-class int-regs } }
75 T{ register->register { from 1 } { to 2 } { reg-class int-regs } }
81 T{ register->register { from 2 } { to 3 } { reg-class int-regs } }
82 T{ register->register { from 1 } { to 2 } { reg-class int-regs } }
83 T{ register->register { from 0 } { to 1 } { reg-class int-regs } }
87 T{ register->register { from 2 } { to 3 } { reg-class int-regs } }
88 T{ register->register { from 1 } { to 2 } { reg-class int-regs } }
89 T{ register->register { from 0 } { to 1 } { reg-class int-regs } }
95 T{ register->register { from 2 } { to 3 } { reg-class int-regs } }
96 T{ register->register { from 1 } { to 2 } { reg-class int-regs } }
97 T{ register->register { from 0 } { to 1 } { reg-class int-regs } }
101 T{ register->register { from 1 } { to 2 } { reg-class int-regs } }
102 T{ register->register { from 2 } { to 3 } { reg-class int-regs } }
103 T{ register->register { from 0 } { to 1 } { reg-class int-regs } }
109 T{ register->register { from 2 } { to 3 } { reg-class int-regs } }
110 T{ register->register { from 1 } { to 2 } { reg-class int-regs } }
111 T{ register->register { from 0 } { to 1 } { reg-class int-regs } }
115 T{ register->register { from 1 } { to 2 } { reg-class int-regs } }
116 T{ register->register { from 2 } { to 3 } { reg-class int-regs } }
117 T{ register->register { from 0 } { to 1 } { reg-class int-regs } }
123 T{ register->register { from 2 } { to 3 } { reg-class int-regs } }
124 T{ register->memory { from 1 } { to 2 } { reg-class int-regs } }
125 T{ register->register { from 0 } { to 1 } { reg-class int-regs } }
129 T{ register->memory { from 1 } { to 2 } { reg-class int-regs } }
130 T{ register->register { from 2 } { to 3 } { reg-class int-regs } }
131 T{ register->register { from 0 } { to 1 } { reg-class int-regs } }
137 T{ _copy { dst 5 } { src 4 } { class int-regs } }
138 T{ _spill { src 1 } { class int-regs } { n 6 } }
139 T{ _copy { dst 1 } { src 0 } { class int-regs } }
140 T{ _reload { dst 0 } { class int-regs } { n 6 } }
141 T{ _spill { src 1 } { class float-regs } { n 7 } }
142 T{ _copy { dst 1 } { src 0 } { class float-regs } }
143 T{ _reload { dst 0 } { class float-regs } { n 7 } }
147 T{ register->register { from 0 } { to 1 } { reg-class int-regs } }
148 T{ register->register { from 1 } { to 0 } { reg-class int-regs } }
149 T{ register->register { from 0 } { to 1 } { reg-class float-regs } }
150 T{ register->register { from 1 } { to 0 } { reg-class float-regs } }
151 T{ register->register { from 4 } { to 5 } { reg-class int-regs } }
152 } mapping-instructions
157 T{ _spill { src 1 } { class int-regs } { n 3 } }
158 T{ _copy { dst 1 } { src 0 } { class int-regs } }
159 T{ _copy { dst 0 } { src 2 } { class int-regs } }
160 T{ _reload { dst 2 } { class int-regs } { n 3 } }
164 T{ register->register { from 0 } { to 1 } { reg-class int-regs } }
165 T{ register->register { from 1 } { to 2 } { reg-class int-regs } }
166 T{ register->register { from 2 } { to 0 } { reg-class int-regs } }
167 } mapping-instructions
172 T{ _spill { src 1 } { class int-regs } { n 3 } }
173 T{ _copy { dst 1 } { src 0 } { class int-regs } }
174 T{ _copy { dst 0 } { src 2 } { class int-regs } }
175 T{ _reload { dst 2 } { class int-regs } { n 3 } }
179 T{ register->register { from 1 } { to 2 } { reg-class int-regs } }
180 T{ register->register { from 2 } { to 0 } { reg-class int-regs } }
181 T{ register->register { from 0 } { to 1 } { reg-class int-regs } }
182 } mapping-instructions
187 T{ _copy { dst 1 } { src 0 } { class int-regs } }
188 T{ _copy { dst 2 } { src 0 } { class int-regs } }
192 T{ register->register { from 0 } { to 1 } { reg-class int-regs } }
193 T{ register->register { from 0 } { to 2 } { reg-class int-regs } }
194 } mapping-instructions
201 T{ register->register { from 4 } { to 4 } { reg-class int-regs } }
202 } mapping-instructions
206 { T{ _spill { src 4 } { class int-regs } { n 4 } } }
209 T{ register->memory { from 4 } { to 4 } { reg-class int-regs } }
210 } mapping-instructions