1 ! Copyright (C) 2020 Doug Coleman.
2 ! See http://factorcode.org/license.txt for BSD license.
3 USING: accessors combinators cpu.arm.assembler.opcodes io.binary
4 kernel make math math.bitwise namespaces sequences ;
7 ! pre-index mode: computed addres is the base-register + offset
9 ! post-index mode: computed address is the base-register
11 ! in both modes, the base-register is updated
13 ERROR: arm64-encoding-imm original n-bits-requested truncated ;
14 : ?bits ( x n -- x ) 2dup bits dup reach = [ 2drop ] [ arm64-encoding-imm ] if ; inline
16 ! : ip ( -- address ) arm64-assembler get ip>> ;
19 [ [ 2 bits ] [ -2 shift 19 ?bits ] bi ] dip ADR-encode ;
21 : ADRP ( imm21 Rd -- )
22 [ [ 2 bits ] [ -2 shift 19 ?bits ] bi ] dip ADRP-encode ;
24 : LDR-pre ( imm9 Rn Rt -- ) LDRpre64-encode ;
25 : LDR-post ( imm9 Rn Rt -- ) LDRpost64-encode ;
26 : LDR-uoff ( imm12 Rn Rt -- ) [ 8 / ] 2dip LDRuoff64-encode ;
28 : MOVwi64 ( imm Rt -- ) [ 0 ] 2dip MOVwi64-encode ;
29 : MOVr64 ( Rn Rd -- ) MOVr64-encode ;
31 : RET ( register/f -- ) X30 or RET-encode ;
33 ! stp x29, x30, [sp,#-16]!
34 ! -16 SP X30 X29 STP-pre
35 : STP-pre ( offset register-offset register-mid register -- )
36 [ 8 / 7 bits ] 3dip swapd STPpre64-encode ;
38 : STP-post ( offset register-offset register-mid register -- )
39 [ 8 / 7 bits ] 3dip swapd STPpost64-encode ;
41 : STP-signed-offset ( offset register-offset register-mid register -- )
42 [ 8 / 7 bits ] 3dip swapd STPsoff64-encode ;
44 ! Some instructions allow an immediate literal of n bits
45 ! or n bits shifted. This means there are invalid immediate
46 ! values, e.g. imm12 of 1, 4096, but not 4097
47 ERROR: imm-out-of-range imm n ;
48 : imm-lower? ( imm n -- ? )
49 on-bits unmask 0 > not ;
51 : imm-upper? ( imm n -- ? )
52 [ on-bits ] [ shift ] bi unmask 0 > not ;
54 : prepare-split-imm ( imm n -- imm upper? )
56 { [ 2dup imm-lower? ] [ drop f ] }
57 { [ 2dup imm-upper? ] [ drop t ] }
61 : ADDi32 ( imm12 Rn Rd -- )
62 [ 12 prepare-split-imm 1 0 ? swap ] 2dip
65 : ADDi64 ( imm12 Rn Rd -- )
66 [ 12 prepare-split-imm 1 0 ? swap ] 2dip
69 : SUBi32 ( imm12 Rn Rd -- )
70 [ 12 prepare-split-imm 1 0 ? swap ] 2dip
73 : SUBi64 ( imm12 Rn Rd -- )
74 [ 12 prepare-split-imm 1 0 ? swap ] 2dip
77 : CMPi32 ( imm12 Rd -- )
78 [ 12 prepare-split-imm 1 0 ? swap ] dip
81 : CMPi64 ( imm12 Rd -- )
82 [ 12 prepare-split-imm 1 0 ? swap ] dip
85 : STRuoff32 ( imm12 Rn Rt -- )
86 [ -2 shift ] 2dip STRuoff32-encode ;
88 : STRuoff64 ( imm12 Rn Rt -- )
89 [ -3 shift ] 2dip STRuoff64-encode ;
91 : STRr64 ( Rm Rn Rt -- )
92 [ 0 0 ] 2dip STRr64-encode ;
94 : ASRi32 ( imm6 Rn Rd -- ) [ 6 ?bits ] 2dip ASRi32-encode ;
95 : ASRi64 ( imm6 Rn Rd -- ) [ 6 ?bits ] 2dip ASRi64-encode ;
96 : LSLi32 ( imm6 Rn Rd -- ) [ 6 ?bits ] 2dip LSLi32-encode ;
97 : LSLi64 ( imm6 Rn Rd -- ) [ 6 ?bits ] 2dip LSLi64-encode ;
98 : LSRi32 ( imm6 Rn Rd -- ) [ 6 ?bits ] 2dip LSRi32-encode ;
99 : LSRi64 ( imm6 Rn Rd -- ) [ 6 ?bits ] 2dip LSRi64-encode ;
101 : SVC ( imm16 -- ) 16 ?bits SVC-encode ;
103 : with-output-variable ( value variable quot -- value )
104 over [ get ] curry compose with-variable ; inline
106 : ADC32 ( Rm Rn Rd -- ) ADC32-encode ;
107 : ADCS32 ( Rm Rn Rd -- ) ADCS32-encode ;
108 : ADC64 ( Rm Rn Rd -- ) ADC64-encode ;
109 : ADCS64 ( Rm Rn Rd -- ) ADCS64-encode ;
111 : BRK ( imm16 -- ) 16 ?bits BRK-encode ;
112 : HLT ( imm16 -- ) 16 ?bits HLT-encode ;
114 : CBNZ ( imm19 Rt -- ) [ 19 ?bits ] dip CBNZ64-encode ;
115 ! cond4 is EQ NE CS HS CC LO MI PL VS VC HI LS GE LT GT LE AL NV
116 : CSEL ( Rm Rn Rd cond4 -- ) -rot CSEL64-encode ;
117 : CSET ( Rd cond4 -- ) swap CSET64-encode ;
118 : CSETM ( Rd cond4 -- ) swap CSETM64-encode ;
120 ! B but that is breakpoint
121 : Br ( imm26 -- ) 26 ?bits B-encode ;
122 : B.cond ( imm19 cond4 -- ) [ 19 ?bits ] dip B.cond-encode ;
123 ! : BL ( offset -- ) ip - 4 / BL-encode ;
124 : BL ( offset -- ) BL-encode ;
125 : BR ( Rn -- ) BR-encode ;
126 : BLR ( Rn -- ) BLR-encode ;