1 <?xml version="1.0"?>
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3 <!-- VHDL mode, contributed by Dante Fabrizio and Nitsan Vardi -->
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5 <!DOCTYPE MODE SYSTEM "xmode.dtd">
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9 <PROPERTY NAME="label" VALUE="VHDL" />
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10 <PROPERTY NAME="lineComment" VALUE="--" />
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12 <RULES ESCAPE="\" IGNORE_CASE="TRUE">
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13 <SPAN TYPE="LITERAL1" NO_LINE_BREAK="TRUE">
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18 <SEQ TYPE="NULL">'event</SEQ>
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20 <SPAN TYPE="LITERAL1" NO_LINE_BREAK="TRUE">
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25 <EOL_SPAN TYPE="COMMENT1">--</EOL_SPAN>
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26 <SEQ TYPE="OPERATOR">=</SEQ>
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27 <SEQ TYPE="OPERATOR">/=</SEQ>
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28 <SEQ TYPE="OPERATOR">!</SEQ>
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29 <SEQ TYPE="OPERATOR">:</SEQ>
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30 <SEQ TYPE="OPERATOR">>=</SEQ>
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31 <SEQ TYPE="OPERATOR">></SEQ>
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32 <SEQ TYPE="OPERATOR"><=</SEQ>
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33 <SEQ TYPE="OPERATOR"><</SEQ>
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34 <SEQ TYPE="OPERATOR">+</SEQ>
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35 <SEQ TYPE="OPERATOR">-</SEQ>
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36 <SEQ TYPE="OPERATOR">/</SEQ>
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37 <SEQ TYPE="OPERATOR">*</SEQ>
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39 <SEQ TYPE="OPERATOR">**</SEQ>
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40 <SEQ TYPE="OPERATOR">%</SEQ>
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41 <SEQ TYPE="OPERATOR">&</SEQ>
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42 <SEQ TYPE="OPERATOR">|</SEQ>
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43 <SEQ TYPE="OPERATOR">^</SEQ>
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45 <MARK_PREVIOUS TYPE="LABEL" MATCH_TYPE="OPERATOR"
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46 AT_LINE_START="FALSE">: </MARK_PREVIOUS>
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49 <KEYWORD1>architecture</KEYWORD1>
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50 <KEYWORD1>alias</KEYWORD1>
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51 <KEYWORD1>assert</KEYWORD1>
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52 <KEYWORD1>entity</KEYWORD1>
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53 <KEYWORD1>process</KEYWORD1>
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54 <KEYWORD1>variable</KEYWORD1>
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55 <KEYWORD1>signal</KEYWORD1>
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56 <KEYWORD1>function</KEYWORD1>
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57 <KEYWORD1>generic</KEYWORD1>
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75 <KEYWORD1>catch</KEYWORD1>
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77 <KEYWORD1>default</KEYWORD1>
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78 <KEYWORD1>do</KEYWORD1>
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79 <KEYWORD1>else</KEYWORD1>
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80 <KEYWORD1>elsif</KEYWORD1>
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81 <KEYWORD1>when</KEYWORD1>
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82 <KEYWORD1>then</KEYWORD1>
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83 <KEYWORD1>downto</KEYWORD1>
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84 <KEYWORD1>upto</KEYWORD1>
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86 <KEYWORD1>for</KEYWORD1>
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87 <KEYWORD1>if</KEYWORD1>
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89 <KEYWORD1>instanceof</KEYWORD1>
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90 <KEYWORD1>return</KEYWORD1>
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91 <KEYWORD1>static</KEYWORD1>
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92 <KEYWORD1>switch</KEYWORD1>
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93 <KEYWORD1>type</KEYWORD1>
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94 <KEYWORD1>while</KEYWORD1>
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95 <KEYWORD1>others</KEYWORD1>
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97 <KEYWORD1>record</KEYWORD1>
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101 <KEYWORD2>package</KEYWORD2>
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102 <KEYWORD2>import</KEYWORD2>
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103 <KEYWORD2>std_logic</KEYWORD2>
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104 <KEYWORD2>std_ulogic</KEYWORD2>
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105 <KEYWORD2>std_logic_vector</KEYWORD2>
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106 <KEYWORD2>std_ulogic_vector</KEYWORD2>
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107 <KEYWORD2>integer</KEYWORD2>
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108 <KEYWORD2>natural</KEYWORD2>
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109 <KEYWORD2>bit</KEYWORD2>
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110 <KEYWORD2>bit_vector</KEYWORD2>
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113 <OPERATOR>or</OPERATOR>
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114 <OPERATOR>nor</OPERATOR>
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115 <OPERATOR>not</OPERATOR>
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116 <OPERATOR>nand</OPERATOR>
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117 <OPERATOR>and</OPERATOR>
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118 <OPERATOR>xnor</OPERATOR>
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119 <OPERATOR>sll</OPERATOR>
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120 <OPERATOR>srl</OPERATOR>
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121 <OPERATOR>sla</OPERATOR>
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122 <OPERATOR>sra</OPERATOR>
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123 <OPERATOR>rol</OPERATOR>
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124 <OPERATOR>ror</OPERATOR>
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125 <OPERATOR>or</OPERATOR>
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126 <OPERATOR>or</OPERATOR>
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127 <OPERATOR>mod</OPERATOR>
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128 <OPERATOR>rem</OPERATOR>
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129 <OPERATOR>abs</OPERATOR>
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131 <KEYWORD3>EVENT</KEYWORD3>
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132 <KEYWORD3>BASE</KEYWORD3>
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133 <KEYWORD3>LEFT</KEYWORD3>
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134 <KEYWORD3>RIGHT</KEYWORD3>
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135 <KEYWORD3>LOW</KEYWORD3>
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136 <KEYWORD3>HIGH</KEYWORD3>
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137 <KEYWORD3>ASCENDING</KEYWORD3>
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138 <KEYWORD3>IMAGE</KEYWORD3>
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139 <KEYWORD3>VALUE</KEYWORD3>
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140 <KEYWORD3>POS</KEYWORD3>
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141 <KEYWORD3>VAL</KEYWORD3>
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142 <KEYWORD3>SUCC</KEYWORD3>
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143 <KEYWORD3>VAL</KEYWORD3>
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144 <KEYWORD3>POS</KEYWORD3>
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145 <KEYWORD3>PRED</KEYWORD3>
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146 <KEYWORD3>VAL</KEYWORD3>
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147 <KEYWORD3>POS</KEYWORD3>
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148 <KEYWORD3>LEFTOF</KEYWORD3>
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149 <KEYWORD3>RIGHTOF</KEYWORD3>
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150 <KEYWORD3>LEFT</KEYWORD3>
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151 <KEYWORD3>RIGHT</KEYWORD3>
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152 <KEYWORD3>LOW</KEYWORD3>
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153 <KEYWORD3>HIGH</KEYWORD3>
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154 <KEYWORD3>RANGE</KEYWORD3>
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155 <KEYWORD3>REVERSE</KEYWORD3>
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156 <KEYWORD3>LENGTH</KEYWORD3>
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157 <KEYWORD3>ASCENDING</KEYWORD3>
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158 <KEYWORD3>DELAYED</KEYWORD3>
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161 <KEYWORD3>TRANSACTION</KEYWORD3>
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162 <KEYWORD3>EVENT</KEYWORD3>
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165 <KEYWORD3>LAST</KEYWORD3>
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168 <KEYWORD3>DRIVING</KEYWORD3>
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169 <KEYWORD3>SIMPLE</KEYWORD3>
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170 <KEYWORD3>INSTANCE</KEYWORD3>
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171 <KEYWORD3>PATH</KEYWORD3>
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173 <FUNCTION>rising_edge</FUNCTION>
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174 <FUNCTION>shift_left</FUNCTION>
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175 <FUNCTION>shift_right</FUNCTION>
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176 <FUNCTION>rotate_left</FUNCTION>
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177 <FUNCTION>rotate_right</FUNCTION>
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178 <FUNCTION>resize</FUNCTION>
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179 <FUNCTION>std_match</FUNCTION>
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180 <FUNCTION>to_integer</FUNCTION>
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181 <FUNCTION>to_unsigned</FUNCTION>
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182 <FUNCTION>to_signed</FUNCTION>
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183 <FUNCTION>unsigned</FUNCTION>
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184 <FUNCTION>signed</FUNCTION>
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185 <FUNCTION>to_bit</FUNCTION>
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186 <FUNCTION>to_bitvector</FUNCTION>
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187 <FUNCTION>to_stdulogic</FUNCTION>
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188 <FUNCTION>to_stdlogicvector</FUNCTION>
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189 <FUNCTION>to_stdulogicvector</FUNCTION>
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191 <LITERAL2>false</LITERAL2>
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192 <LITERAL2>true</LITERAL2>
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projects / factor.git / blob