Add: cpu.arm.64

diff --git a/basis/cpu/arm/64/64.factor b/basis/cpu/arm/64/64.factor
index 450c8dc8d8c45bb185a9f186050a4c70162b43cf..3b88a59afc09e9eeef98ee2b53a36630c9e72ffd 100644 (file)
--- a/basis/cpu/arm/64/64.factor
+++ b/basis/cpu/arm/64/64.factor
@@ -1,7 +1,364 @@
-! Copyright (C) 2020 Doug Coleman.
+! Copyright (C) 2023 Giftpflanze.
 ! See https://factorcode.org/license.txt for BSD license.
-USING: cpu.arm cpu.arm.assembler.opcodes system ;
+USING: accessors assocs compiler.cfg compiler.cfg.comparisons
+compiler.cfg.instructions compiler.cfg.intrinsics continuations
+cpu.architecture cpu.arm cpu.arm.assembler cpu.arm.assembler.64
+cpu.arm.assembler.opcodes generalizations kernel math math.order
+sequences system words.symbol ;
+FROM: cpu.arm.assembler => S D ;
 IN: cpu.arm.64
 
-M: arm.64 ds-reg X5 ;
-M: arm.64 rs-reg X6 ;
+M: arm.64 frame-reg X29 ;
+: vm-reg ( -- reg ) X28 ; inline
+M: arm.64 ds-reg X27 ;
+M: arm.64 rs-reg X26 ;
+
+! M: arm.64 vm-stack-space 0 ;
+
+M: arm.64 %load-immediate ( reg val -- )
+    [ XZR MOVr ] [
+        { 0 1 2 3 } [
+            tuck -8 * shift 0xffff bitand
+        ] with map>alist [ nip 0 = ] assoc-reject
+        unclip
+        overd first2 rot MOVZ
+        [ first2 rot MOVK ] with each
+    ] if-zero ;
+
+M: arm.64 %load-reference ( reg obj -- )
+    ! [ swap 0 MOV rc-absolute-cell rel-literal ]
+    ! [ \ f type-number MOV ] if* ;
+    2drop ;
+
+M: arm.64 %load-float 2drop ;
+M: arm.64 %load-double 2drop ;
+M: arm.64 %load-vector 3drop ;
+
+M: arm.64 complex-addressing? eh? ; ! x86: t
+M: arm.64 dummy-fp-params? f ; ! x86.64.windows: t
+M: arm.64 dummy-int-params? f ; ! ppc.64.linux: t
+M: arm.64 dummy-stack-params? f ; ! ppc.64.linux: t
+M: arm.64 float-right-align-on-stack? f ; ! ppc.64.linux: t
+M: arm.64 fused-unboxing? eh? ; ! x86: t
+M: arm.64 integer-float-needs-stack-frame? f ; ! x86.sse: f
+M: arm.64 long-long-odd-register? f ; ! ppc.32: t
+M: arm.64 long-long-on-stack? f ; ! x86.32: t
+M: arm.64 return-struct-in-registers? drop eh? ;
+M: arm.64 struct-return-on-stack? f ; ! x86.32.not-linux: t
+M: arm.64 test-instruction? t ; ! t
+M: arm.64 value-struct? drop eh? ;
+
+M: arm.64 %add rot ADDr ;
+M: arm.64 %add-imm spin ADDi ;
+M: arm.64 %sub spin SUBr ;
+M: arm.64 %sub-imm spin SUBi ;
+M: arm.64 %mul rot MUL ;
+
+M: arm.64 %mul-imm
+    XZR X9 ADDi
+    X9 rot MUL ;
+
+M: arm.64 %neg swap NEG ;
+
+M: arm.64 %min
+    2dup CMPr
+    rot LT CSEL ;
+
+M: arm.64 %max
+    2dup CMPr
+    rot GT CSEL ;
+
+M: arm.64 %log2
+    over CLZ
+    63 over dup SUBi
+    dup NEG ;
+
+M: arm.64 %bit-count
+    D0 XD FMOVgen
+    D0 D0 8B CNT
+    D0 D0 8B ADDV
+    D0 swap DX FMOVgen ;
+
+M: arm.64 %bit-test
+    [ 2^ swap TSTi ] dip
+    swap dup EQ CSEL ;
+
+M: arm.64 %and rot ANDr ;
+M: arm.64 %and-imm spin ANDi ;
+M: arm.64 %not swap MVN ;
+M: arm.64 %or rot ORRr ;
+M: arm.64 %or-imm spin ORRi ;
+M: arm.64 %sar spin ASRr ;
+M: arm.64 %sar-imm spin ASRi ;
+M: arm.64 %shl spin LSLr ;
+M: arm.64 %shl-imm spin LSLi ;
+M: arm.64 %shr spin LSRr ;
+M: arm.64 %shr-imm spin LSRi ;
+M: arm.64 %xor rot EORr ;
+M: arm.64 %xor-imm spin EORi ;
+
+M: arm.64 %copy ( dst src rep -- )
+    2over eq? [ 3drop ] [
+        ! [ [ ?spill-slot ] bi@ ] dip
+        ! 2over [ register? ] both? [ copy-register* ] [ copy-memory* ] if
+        3drop
+    ] if ;
+
+: fixnum-overflow ( label dst src1 src2 cc quot -- )
+    [ call ] curry dip {
+        { cc-o VS }
+        { cc/o VC }
+    } at B.cond ; inline
+
+M: arm.64 %fixnum-add [ rot ADDr ] fixnum-overflow ;
+M: arm.64 %fixnum-sub [ spin SUBr ] fixnum-overflow ;
+M: arm.64 %fixnum-mul [ rot MUL ] fixnum-overflow ;
+
+M: arm.64 %add-float rot D FADDs ;
+M: arm.64 %sub-float spin D FSUBs ;
+M: arm.64 %mul-float rot D FMULs ;
+M: arm.64 %div-float spin D FDIVs ;
+M: arm.64 %min-float rot D FMINs ;
+M: arm.64 %max-float rot D FMAXs ;
+M: arm.64 %sqrt swap D FSQRTs ;
+
+M: arm.64 %single>double-float swap S D FCVT ;
+M: arm.64 %double>single-float swap D S FCVT ;
+
+M: arm.64 %integer>float swap D SCVTFsi ;
+M: arm.64 %float>integer swap D FCVTZSsi ;
+
+M: arm.64 %zero-vector 2drop ;
+M: arm.64 %fill-vector 2drop ;
+M: arm.64 %gather-vector-2 4drop ;
+M: arm.64 %gather-int-vector-2 4drop ;
+M: arm.64 %gather-vector-4 6 ndrop ;
+M: arm.64 %gather-int-vector-4 6 ndrop ;
+M: arm.64 %select-vector 4drop ;
+M: arm.64 %shuffle-vector 4drop ;
+M: arm.64 %shuffle-vector-imm 4drop ;
+M: arm.64 %shuffle-vector-halves-imm 5drop ;
+M: arm.64 %tail>head-vector 3drop ;
+M: arm.64 %merge-vector-head 4drop ;
+M: arm.64 %merge-vector-tail 4drop ;
+M: arm.64 %float-pack-vector 3drop ;
+M: arm.64 %signed-pack-vector 4drop ;
+M: arm.64 %unsigned-pack-vector 4drop ;
+M: arm.64 %unpack-vector-head 3drop ;
+M: arm.64 %unpack-vector-tail 3drop ;
+M: arm.64 %integer>float-vector 3drop ;
+M: arm.64 %float>integer-vector 3drop ;
+M: arm.64 %compare-vector 5drop ;
+M: arm.64 %move-vector-mask 3drop ;
+M: arm.64 %test-vector 5drop ;
+M: arm.64 %test-vector-branch 5drop ;
+M: arm.64 %add-vector 4drop ;
+M: arm.64 %saturated-add-vector 4drop ;
+M: arm.64 %add-sub-vector 4drop ;
+M: arm.64 %sub-vector 4drop ;
+M: arm.64 %saturated-sub-vector 4drop ;
+M: arm.64 %mul-vector 4drop ;
+M: arm.64 %mul-high-vector 4drop ;
+M: arm.64 %mul-horizontal-add-vector 4drop ;
+M: arm.64 %saturated-mul-vector 4drop ;
+M: arm.64 %div-vector 4drop ;
+M: arm.64 %min-vector 4drop ;
+M: arm.64 %max-vector 4drop ;
+M: arm.64 %avg-vector 4drop ;
+M: arm.64 %dot-vector 4drop ;
+M: arm.64 %sad-vector 4drop ;
+M: arm.64 %sqrt-vector 3drop ;
+M: arm.64 %horizontal-add-vector 4drop ;
+M: arm.64 %horizontal-sub-vector 4drop ;
+M: arm.64 %abs-vector 3drop ;
+M: arm.64 %and-vector 4drop ;
+M: arm.64 %andn-vector 4drop ;
+M: arm.64 %or-vector 4drop ;
+M: arm.64 %xor-vector 4drop ;
+M: arm.64 %not-vector 3drop ;
+M: arm.64 %shl-vector 4drop ;
+M: arm.64 %shr-vector 4drop ;
+M: arm.64 %shl-vector-imm 4drop ;
+M: arm.64 %shr-vector-imm 4drop ;
+M: arm.64 %horizontal-shl-vector-imm 4drop ;
+M: arm.64 %horizontal-shr-vector-imm 4drop ;
+
+M: arm.64 %integer>scalar 3drop ;
+M: arm.64 %scalar>integer 3drop ;
+M: arm.64 %vector>scalar 3drop ;
+M: arm.64 %scalar>vector 3drop ;
+
+M: arm.64 %zero-vector-reps f ;
+M: arm.64 %fill-vector-reps f ;
+M: arm.64 %gather-vector-2-reps f ;
+M: arm.64 %gather-int-vector-2-reps f ;
+M: arm.64 %gather-vector-4-reps f ;
+M: arm.64 %gather-int-vector-4-reps f ;
+M: arm.64 %select-vector-reps f ;
+M: arm.64 %alien-vector-reps f ;
+M: arm.64 %shuffle-vector-reps f ;
+M: arm.64 %shuffle-vector-imm-reps f ;
+M: arm.64 %shuffle-vector-halves-imm-reps f ;
+M: arm.64 %merge-vector-reps f ;
+M: arm.64 %float-pack-vector-reps f ;
+M: arm.64 %signed-pack-vector-reps f ;
+M: arm.64 %unsigned-pack-vector-reps f ;
+M: arm.64 %unpack-vector-head-reps f ;
+M: arm.64 %unpack-vector-tail-reps f ;
+M: arm.64 %integer>float-vector-reps f ;
+M: arm.64 %float>integer-vector-reps f ;
+M: arm.64 %compare-vector-reps drop f ;
+M: arm.64 %compare-vector-ccs nip eh? ;
+M: arm.64 %move-vector-mask-reps f ;
+M: arm.64 %test-vector-reps f ;
+M: arm.64 %add-vector-reps f ;
+M: arm.64 %saturated-add-vector-reps f ;
+M: arm.64 %add-sub-vector-reps f ;
+M: arm.64 %sub-vector-reps f ;
+M: arm.64 %saturated-sub-vector-reps f ;
+M: arm.64 %mul-vector-reps f ;
+M: arm.64 %mul-high-vector-reps f ;
+M: arm.64 %mul-horizontal-add-vector-reps f ;
+M: arm.64 %saturated-mul-vector-reps f ;
+M: arm.64 %div-vector-reps f ;
+M: arm.64 %min-vector-reps f ;
+M: arm.64 %max-vector-reps f ;
+M: arm.64 %avg-vector-reps f ;
+M: arm.64 %dot-vector-reps f ;
+M: arm.64 %sad-vector-reps f ;
+M: arm.64 %sqrt-vector-reps f ;
+M: arm.64 %horizontal-add-vector-reps f ;
+M: arm.64 %horizontal-sub-vector-reps f ;
+M: arm.64 %abs-vector-reps f ;
+M: arm.64 %and-vector-reps f ;
+M: arm.64 %andn-vector-reps f ;
+M: arm.64 %or-vector-reps f ;
+M: arm.64 %xor-vector-reps f ;
+M: arm.64 %not-vector-reps f ;
+M: arm.64 %shl-vector-reps f ;
+M: arm.64 %shr-vector-reps f ;
+M: arm.64 %shl-vector-imm-reps f ;
+M: arm.64 %shr-vector-imm-reps f ;
+M: arm.64 %horizontal-shl-vector-imm-reps f ;
+M: arm.64 %horizontal-shr-vector-imm-reps f ;
+
+M: arm.64 %unbox-alien 2drop ;
+M: arm.64 %unbox-any-c-ptr 2drop ;
+M: arm.64 %box-alien 3drop ;
+M: arm.64 %box-displaced-alien 5drop ;
+
+M: arm.64 %convert-integer 3drop ;
+
+M: arm.64 %load-memory 7 ndrop ;
+M: arm.64 %load-memory-imm 5drop ;
+M: arm.64 %store-memory 7 ndrop ;
+M: arm.64 %store-memory-imm 5drop ;
+
+M: arm.64 %alien-global 3drop ;
+M: arm.64 %vm-field 2drop ;
+M: arm.64 %set-vm-field 2drop ;
+
+M: arm.64 %allot 4drop ;
+M: arm.64 %write-barrier 6 ndrop ;
+M: arm.64 %write-barrier-imm 5drop ;
+
+M: arm.64 stack-frame-size ;
+M: arm.64 %call drop ;
+M: arm.64 %epilogue drop ;
+M: arm.64 %jump drop ;
+M: arm.64 %jump-label drop ;
+M: arm.64 %prologue drop ;
+M: arm.64 %return f RET ;
+M: arm.64 %safepoint ;
+
+M: arm.64 %compare 5drop ;
+M: arm.64 %compare-imm 5drop ;
+M: arm.64 %compare-integer-imm 5drop ;
+M: arm.64 %test 5drop ;
+M: arm.64 %test-imm 5drop ;
+M: arm.64 %compare-float-ordered 5drop ;
+M: arm.64 %compare-float-unordered 5drop ;
+
+M: arm.64 %compare-branch 4drop ;
+M: arm.64 %compare-imm-branch 4drop ;
+M: arm.64 %compare-integer-imm-branch 4drop ;
+M: arm.64 %test-branch 4drop ;
+M: arm.64 %test-imm-branch 4drop ;
+M: arm.64 %compare-float-ordered-branch 4drop ;
+M: arm.64 %compare-float-unordered-branch 4drop ;
+
+M: arm.64 %dispatch 2drop ;
+
+M: arm.64 %c-invoke 3drop ;
+
+M: arm.64 %call-gc drop ;
+M: arm.64 %check-nursery-branch 5drop ;
+
+M: arm.64 %clear drop ;
+M: arm.64 %peek 2drop ;
+M: arm.64 %replace 2drop ;
+M: arm.64 %replace-imm 2drop ;
+M: arm.64 %inc drop ;
+
+M: arm.64 machine-registers {
+    {
+        int-regs {
+            X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
+            X19 X20 X21 X22 X23 X24
+        }
+    }
+    {
+        float-regs
+        {
+            V0 V1 V2 V3 V4 V5 V6 V7
+            V16 V17 V18 V19 V20 V21 V22 V23 V24 V25 V26 V27 V28
+            V29 V30 V31
+        }
+    }
+} ;
+M: arm.64 param-regs drop {
+    { int-regs { X0 X1 X2 X3 X4 X5 X6 X7 X8 } }
+    { float-regs { V0 V1 V2 V3 V4 V5 V6 V7 } }
+} ;
+M: arm.64 return-regs {
+    { int-regs { X0 X1 X2 X3 X4 X5 X6 X7 X8 } }
+    { float-regs { V0 V1 V2 V3 V4 V5 V6 V7 } }
+} ;
+
+M: arm.64 %set-slot 5drop ;
+M: arm.64 %set-slot-imm 4drop ;
+M: arm.64 %slot 5drop ;
+M: arm.64 %slot-imm 4drop ;
+
+M: arm.64 %spill 3drop ;
+M: arm.64 %reload 3drop ;
+M: arm.64 gc-root-offset ;
+
+M: arm.64 immediate-arithmetic? -2147483648 2147483647 between? ;
+M: arm.64 immediate-bitwise?
+    [ encode-bitmask drop t ] [ 2drop f ] recover ;
+M: arm.64 immediate-comparand? drop eh? ;
+M: arm.64 immediate-store? drop eh? ;
+
+M: arm.64 %unbox 4drop ;
+M: arm.64 %unbox-long-long 4drop ;
+M: arm.64 %local-allot 4drop ;
+M: arm.64 %box 5drop ;
+M: arm.64 %box-long-long 5drop ;
+M: arm.64 %save-context 2drop ;
+
+M: arm.64 %alien-invoke 10 ndrop ;
+M: arm.64 %alien-indirect 9 ndrop ;
+M: arm.64 %alien-assembly 8 ndrop ;
+M: arm.64 %callback-inputs 2drop ;
+M: arm.64 %callback-outputs drop ;
+M: arm.64 stack-cleanup 2drop ;
+M: arm.64 enable-cpu-features
+    enable-min/max
+    enable-log2
+    enable-bit-test
+    enable-alien-4-intrinsics
+    enable-float-min/max
+    enable-bit-count
+    enable-float-intrinsics
+    enable-fsqrt ;

diff --git a/basis/cpu/arm/64/authors.txt b/basis/cpu/arm/64/authors.txt
index 7c1b2f22790bfdca05f14a555a40b7eaa3ce2abd..305077512dbb91d74794a4df2b60080838123d8d 100644 (file)
--- a/basis/cpu/arm/64/authors.txt
+++ b/basis/cpu/arm/64/authors.txt
@@ -1 +1 @@
-Doug Coleman
+Giftpflanze

diff --git a/basis/cpu/arm/arm.factor b/basis/cpu/arm/arm.factor
index 0df129f5479bbb87f42279976bcb94d94d2311a2..d4f52526acb4fc7282c5bd7f6647e2d8e73281b6 100644 (file)
--- a/basis/cpu/arm/arm.factor
+++ b/basis/cpu/arm/arm.factor
@@ -5,3 +5,5 @@ IN: cpu.arm
 
 HOOK: ds-reg cpu ( -- reg )
 HOOK: rs-reg cpu ( -- reg )
+
+ALIAS: eh? f

diff --git a/basis/cpu/arm/assembler/64/64.factor b/basis/cpu/arm/assembler/64/64.factor
index 7af57545198cffe341359afe8c1ea7322e221a56..f0c76e7024ab0115e5e10ecea51a1aef27d0ba8d 100644 (file)
--- a/basis/cpu/arm/assembler/64/64.factor
+++ b/basis/cpu/arm/assembler/64/64.factor
@@ -1,7 +1,7 @@
 ! Copyright (C) 2023 Doug Coleman.
 ! Copyright (C) 2023 Giftpflanze.
 ! See https://factorcode.org/license.txt for BSD license.
-USING: cpu.arm.assembler cpu.arm.assembler.opcodes kernel math
+USING: cpu.arm.assembler cpu.arm.assembler.opcodes kernel
 math.bitwise ;
 IN: cpu.arm.assembler.64
 
@@ -23,6 +23,8 @@ IN: cpu.arm.assembler.64
 
 : CBNZ ( simm21 Rt -- ) [ 2 ?>> 19 ?sbits ] dip CBNZ64-encode ;
 
+: CLZ ( Rn Rd -- ) CLZ64-encode ;
+
 : CMPi ( imm24 Rd -- ) [ split-imm ] dip CMPi64-encode ;
 : CMPr ( Rm Rn -- ) [ 3 0 ] dip CMPer64-encode ;
 
@@ -34,8 +36,7 @@ IN: cpu.arm.assembler.64
 : EORi ( imm64 Rn Rd -- ) [ encode-bitmask ] 2dip EORi64-encode ;
 : EORr ( Rm Rn Rd -- ) [ [ 0 ] dip 0 ] 2dip EORsr64-encode ;
 
-: FPCR ( -- op0 op1 CRn CRm op2 ) 3 3 4 4 0 ;
-: FPSR ( -- op0 op1 CRn CRm op2 ) 3 3 4 4 1 ;
+: FCVTZSsi ( Rn Rd var -- ) >ftype -rot FCVTZSsi64-encode ;
 
 : LDPpost ( simm10 Rn Rt2 Rt -- ) [ 3 ?>> 7 ?sbits ] 3dip swapd LDPpost64-encode ;
 : LDPpre ( simm10 Rn Rt2 Rt -- ) [ 3 ?>> 7 ?sbits ] 3dip swapd LDPpre64-encode ;
@@ -47,25 +48,19 @@ IN: cpu.arm.assembler.64
 : LDRr ( Rm Rn Rt -- ) [ 3 0 ] 2dip LDRr64-encode ;
 : LDRuoff ( uimm15 Rn Rt -- ) [ 3 ?>> 12 ?ubits ] 2dip LDRuoff64-encode ;
 
-: LDRBr ( Rm Rn Rt -- ) [ 0 ] 2dip LDRBsr-encode ;
-: LDRBuoff ( uimm12 Rn Rt -- ) [ 12 ?ubits ] 2dip LDRBuoff-encode ;
-
-: LDRHuoff ( uimm13 Rn Rt -- ) [ 1 ?>> 12 ?ubits ] 2dip LDRHuoff-encode ;
-
 : LDUR ( simm9 Rn Rt -- ) [ 9 ?sbits ] 2dip LDUR64-encode ;
 
 : LSLi ( uimm6 Rn Rd -- ) [ 6 ?ubits ] 2dip LSLi64-encode ;
 : LSLr ( Rm Rn Rd -- ) LSLr64-encode ;
 
 : LSRi ( uimm6 Rn Rd -- ) [ 6 ?ubits ] 2dip LSRi64-encode ;
+: LSRr ( Rm Rn Rd -- ) LSRr64-encode ;
 
 : MOVr ( Rn Rd -- ) MOVr64-encode ;
 : MOVsp ( Rn Rd -- ) [ 0 ] 2dip MOVsp64-encode ;
-: MOVwi ( imm16 Rt -- ) [ [ 0 ] dip 16 bits ] dip MOVwi64-encode ;
-
-: MRS ( op0 op1 CRn CRm op2 Rt -- ) MRS-encode ;
-
-: MSRr ( op0 op1 CRn CRm op2 Rt -- ) MSRr-encode ;
+: MOVwi ( imm16 Rd -- ) [ [ 0 ] dip 16 bits ] dip MOVwi64-encode ;
+: MOVZ ( lsl imm16 Rd -- ) [ 16 bits ] dip MOVZ64-encode ;
+: MOVK ( lsl imm16 Rd -- ) [ 16 bits ] dip MOVK64-encode ;
 
 : MSUB ( Ra Rm Rn Rd -- ) [ swap ] 2dip MSUB64-encode ;
 
@@ -75,10 +70,11 @@ IN: cpu.arm.assembler.64
 
 : NEG ( Rm Rd -- ) [ [ 0 ] dip 0 ] dip NEG64-encode ;
 
-: NZCV ( -- op0 op1 CRn CRm op2 ) 3 3 4 2 0 ;
-
+: ORRi ( imm64 Rn Rd -- ) [ encode-bitmask ] 2dip ORRi64-encode ;
 : ORRr ( Rm Rn Rd -- ) [ [ 0 ] dip 0 ] 2dip ORRsr64-encode ;
 
+: SCVTFsi ( Rn Rd var -- ) >ftype -rot SCVTFsi64-encode ;
+
 : SDIV ( Rm Rn Rd -- ) SDIV64-encode ;
 
 : STADD ( Rs Rn -- ) STADD64-encode ;

diff --git a/basis/cpu/arm/assembler/64/authors.txt b/basis/cpu/arm/assembler/64/authors.txt
index 7c1b2f22790bfdca05f14a555a40b7eaa3ce2abd..25356e4e7706e1e0c35a481c53653ba125e1e0d8 100644 (file)
--- a/basis/cpu/arm/assembler/64/authors.txt
+++ b/basis/cpu/arm/assembler/64/authors.txt
@@ -1 +1,2 @@
 Doug Coleman
+Giftpflanze

diff --git a/basis/cpu/arm/assembler/assembler.factor b/basis/cpu/arm/assembler/assembler.factor
index 891a53066bb5824bada7ad55a1cbd335357459ca..0693b4e1e206b1770ae0066cd0a49e33b7443af2 100644 (file)
--- a/basis/cpu/arm/assembler/assembler.factor
+++ b/basis/cpu/arm/assembler/assembler.factor
@@ -1,8 +1,9 @@
 ! Copyright (C) 2020 Doug Coleman.
 ! Copyright (C) 2023 Giftpflanze.
 ! See https://factorcode.org/license.txt for BSD license.
-USING: combinators cpu.arm.assembler.opcodes grouping kernel
-math math.bitwise math.parser sequences ;
+USING: assocs combinators cpu.arm.assembler.opcodes
+generalizations grouping kernel math math.bitwise math.parser
+sequences shuffle ;
 IN: cpu.arm.assembler
 
 ! pre-index mode: computed addres is the base-register + offset
@@ -42,6 +43,8 @@ ERROR: imm-out-of-range imm n ;
 
 : split-imm ( imm -- shift imm ) 12 (split-imm) 1 0 ? swap ;
 
+! Logical immediates
+
 ERROR: illegal-bitmask-immediate n ;
 : ?bitmask ( imm imm-size -- imm )
     dupd on-bits 0 [ = ] bi-curry@ bi or
@@ -73,16 +76,18 @@ ERROR: illegal-bitmask-element n ;
     [ ?element ] keep [ >Nimms ] [ >immr ] 2bi
     { 12 0 6 } bitfield* ;
 
-: ADR ( simm21 Rd -- ) [ [ 2 bits ] [ -2 shift 19 ?sbits ] bi ] dip ADR-encode ;
+! Floating-point variants
 
-: ADRP ( simm21 Rd -- ) [ 4096 / [ 2 bits ] [ -2 shift 19 ?sbits ] bi ] dip ADRP-encode ;
+SYMBOLS: H S D ;
 
-: RET ( Rn/f -- ) X30 or RET-encode ;
+: >ftype ( symbol -- n ) { { H 3 } { S 0 } { D 1 } } at ; inline
 
-: SVC ( uimm16 -- ) 16 ?ubits SVC-encode ;
 
-: BRK ( uimm16 -- ) 16 ?ubits BRK-encode ;
-: HLT ( uimm16 -- ) 16 ?ubits HLT-encode ;
+: ADDV ( Rn Rd size Q -- ) -roll -rot ADDV-encode ;
+
+: ADR ( simm21 Rd -- ) [ [ 2 bits ] [ -2 shift 19 ?sbits ] bi ] dip ADR-encode ;
+
+: ADRP ( simm21 Rd -- ) [ 4096 / [ 2 bits ] [ -2 shift 19 ?sbits ] bi ] dip ADRP-encode ;
 
 ! B but that is breakpoint
 : Br ( simm28 -- ) 2 ?>> 26 ?sbits B-encode ;
@@ -90,3 +95,38 @@ ERROR: illegal-bitmask-element n ;
 : BL ( simm28 -- ) 2 ?>> 26 ?sbits BL-encode ;
 : BR ( Rn -- ) BR-encode ;
 : BLR ( Rn -- ) BLR-encode ;
+
+: BRK ( uimm16 -- ) 16 ?ubits BRK-encode ;
+
+: CNT ( Vn Vd size Q -- ) -roll -rot CNT-encode ;
+
+: DUPgen ( Rn Rd size Q -- ) -roll 2^ -rot DUPgen-encode ;
+
+: FADDs ( Rm Rn Rd var -- ) >ftype -roll FADDs-encode ;
+: FCVT ( Rn Rd svar dvar -- ) [ >ftype ] bi@ 2swap FCVT-encode ;
+: FDIVs ( Rm Rn Rd var -- ) >ftype -roll FDIVs-encode ;
+: FMAXs ( Rm Rn Rd var -- ) >ftype -roll FMAXs-encode ;
+: FMINs ( Rm Rn Rd var -- ) >ftype -roll FMINs-encode ;
+: FMULs ( Rm Rn Rd var -- ) >ftype -roll FMULs-encode ;
+: FSQRTs ( Rn Rd var -- ) >ftype -rot FSQRTs-encode ;
+: FSUBs ( Rm Rn Rd var -- ) >ftype -roll FSUBs-encode ;
+
+: FMOVgen ( Rn Rd sf ftype rmode opcode -- ) 4 2 mnswap FMOVgen-encode ;
+
+: FPCR ( -- op0 op1 CRn CRm op2 ) 3 3 4 4 0 ;
+: FPSR ( -- op0 op1 CRn CRm op2 ) 3 3 4 4 1 ;
+
+: HLT ( uimm16 -- ) 16 ?ubits HLT-encode ;
+
+: LDRBr ( Rm Rn Rt -- ) [ 0 ] 2dip LDRBsr-encode ;
+: LDRBuoff ( uimm12 Rn Rt -- ) [ 12 ?ubits ] 2dip LDRBuoff-encode ;
+: LDRHuoff ( uimm13 Rn Rt -- ) [ 1 ?>> 12 ?ubits ] 2dip LDRHuoff-encode ;
+
+: MRS ( op0 op1 CRn CRm op2 Rt -- ) MRS-encode ;
+: MSRr ( op0 op1 CRn CRm op2 Rt -- ) MSRr-encode ;
+
+: NZCV ( -- op0 op1 CRn CRm op2 ) 3 3 4 2 0 ;
+
+: RET ( Rn/f -- ) X30 or RET-encode ;
+
+: SVC ( uimm16 -- ) 16 ?ubits SVC-encode ;

diff --git a/basis/cpu/arm/assembler/authors.txt b/basis/cpu/arm/assembler/authors.txt
index 7c1b2f22790bfdca05f14a555a40b7eaa3ce2abd..25356e4e7706e1e0c35a481c53653ba125e1e0d8 100644 (file)
--- a/basis/cpu/arm/assembler/authors.txt
+++ b/basis/cpu/arm/assembler/authors.txt
@@ -1 +1,2 @@
 Doug Coleman
+Giftpflanze

diff --git a/basis/cpu/arm/assembler/opcodes/authors.txt b/basis/cpu/arm/assembler/opcodes/authors.txt
index 7c1b2f22790bfdca05f14a555a40b7eaa3ce2abd..25356e4e7706e1e0c35a481c53653ba125e1e0d8 100644 (file)
--- a/basis/cpu/arm/assembler/opcodes/authors.txt
+++ b/basis/cpu/arm/assembler/opcodes/authors.txt
@@ -1 +1,2 @@
 Doug Coleman
+Giftpflanze

diff --git a/basis/cpu/arm/assembler/opcodes/opcodes.factor b/basis/cpu/arm/assembler/opcodes/opcodes.factor
index 2f2855d8ee5c60c6fd90cb8c96e1147a3d7de045..0db36084329d39fe58a59c5a8bd3ac9048640c72 100644 (file)
--- a/basis/cpu/arm/assembler/opcodes/opcodes.factor
+++ b/basis/cpu/arm/assembler/opcodes/opcodes.factor
@@ -97,6 +97,8 @@ FIELD: U 1
 FIELD: Z 1
 
 FIELD: sf 1
+FIELD: ftype 2
+FIELD: rmode 2
 
 FIELD: size1 1
 FIELD: size2 2
@@ -261,6 +263,30 @@ SINGLETONS: SPSR_EL1 SPSR_EL2 SPSR_EL3 ;
 : AL ( -- n ) 0b1110 ; inline ! always
 : NV ( -- n ) 0b1111 ; inline ! always
 
+! Arrangement specifiers
+
+: 8B ( -- size Q ) 0 0 ; inline
+: 16B ( -- size Q ) 0 1 ; inline
+: 4H ( -- size Q ) 1 0 ; inline
+: 8H ( -- size Q ) 1 1 ; inline
+: 2S ( -- size Q ) 2 0 ; inline
+: 4S ( -- size Q ) 2 1 ; inline
+: 2D ( -- size Q ) 3 1 ; inline
+
+! FMOVgen variants
+
+: HW ( -- sf ftype rmode opcode ) 0 3 0 6 ; inline
+: HX ( -- sf ftype rmode opcode ) 1 3 0 6 ; inline
+: WH ( -- sf ftype rmode opcode ) 0 3 0 7 ; inline
+: WS ( -- sf ftype rmode opcode ) 0 0 0 7 ; inline
+: SW ( -- sf ftype rmode opcode ) 0 0 0 6 ; inline
+: XH ( -- sf ftype rmode opcode ) 1 3 0 7 ; inline
+: XD ( -- sf ftype rmode opcode ) 1 1 0 7 ; inline
+: XD[1] ( -- sf ftype rmode opcode ) 1 2 0 7 ; inline
+: DX ( -- sf ftype rmode opcode ) 1 1 0 6 ; inline
+: D[1]X ( -- sf ftype rmode opcode ) 1 2 0 6 ; inline
+
+
 ERROR: no-field-word vocab name ;
 
 TUPLE: integer-literal value width ;
@@ -339,6 +365,9 @@ ARM-INSTRUCTION: ADDSi64-encode ( 1 0 1 10001 shift2 imm12 Rn Rd -- )
 ARM-INSTRUCTION: ADDSsr32-encode ( 0 0 1 01011 shift2 0 Rm imm6 Rn Rd -- )
 ARM-INSTRUCTION: ADDSsr64-encode ( 1 0 1 01011 shift2 0 Rm imm6 Rn Rd -- )
 
+! ADDV: Add across Vector.
+ARM-INSTRUCTION: ADDV-encode ( 0 Q 0 01110 size2 11000 11011 10 Rn Rd -- )
+
 ! ADR: Form PC-relative address.
 ! ADRP: Form PC-relative address to 4KB page.
 ARM-INSTRUCTION: ADR-encode  ( 0 immlo2 10000 immhi19 Rd -- )
@@ -431,6 +460,7 @@ ARM-INSTRUCTION: BIC64-encode ( 1 00 01010 shift2 1 Rm imm6 Rn Rd -- )
 ! BICS (shifted register): Bitwise Bit Clear (shifted register), setting flags.
 ARM-INSTRUCTION: BICS32-encode ( 0 11 01010 shift2 1 Rm imm6 Rn Rd -- )
 ARM-INSTRUCTION: BICS64-encode ( 1 11 01010 shift2 1 Rm imm6 Rn Rd -- )
+
 ! BL: Branch with Link.
 ARM-INSTRUCTION: BL-encode ( 1 00101 imm26 -- )
 ! BLR: Branch with Link to Register.
@@ -453,6 +483,7 @@ ARM-INSTRUCTION: BRABZ-encode ( 1101011 1 0 00 11111 0000 1 1 Rn Rm -- )
 
 ! BRK: Breakpoint instruction.
 ARM-INSTRUCTION: BRK-encode ( 11010100 001 imm16 000 00 -- )
+
 ! BTI: Branch Target Identification.
 ARM-INSTRUCTION: BTI-encode ( 1101010100 0 00 011 0010 0100 000 11111 -- )
 
@@ -511,16 +542,21 @@ ARM-INSTRUCTION: CCMPr64-encode ( 1 1 1 11010010 Rm cond4 0 0 Rn 0 nzcv -- )
 
 ! CFINV: Invert Carry Flag.
 ARM-INSTRUCTION: CFINV-encode ( 1101010100 0 0 0 000 0100 0000 000 11111 -- )
+
 ! CFP: Control Flow Prediction Restriction by Context: an alias of SYS.
 ARM-INSTRUCTION: CFP-encode ( 1101010100 0 01 011 0111 0011 100 Rt -- )
+
 ! CINC: Conditional Increment: an alias of CSINC.
 ARM-INSTRUCTION: CINC32-encode ( 0 0 0 11010100 Rm cond4 0 1 Rn Rd -- )
 ARM-INSTRUCTION: CINC64-encode ( 1 0 0 11010100 Rm cond4 0 1 Rn Rd -- )
+
 ! CINV: Conditional Invert: an alias of CSINV.
 ARM-INSTRUCTION: CINV32-encode ( 0 0 0 11010100 Rm cond4 0 0 Rn Rd -- )
 ARM-INSTRUCTION: CINV64-encode ( 1 0 0 11010100 Rm cond4 0 0 Rn Rd -- )
+
 ! CLREX: Clear Exclusive.
 ARM-INSTRUCTION: CLREX-encode ( 1101010100 0 00 011 0011 CRm 010 11111 -- )
+
 ! CLS: Count Leading Sign bits.
 ARM-INSTRUCTION: CLS32-encode ( 0 1 0 11010110 00000 00010 1 Rn Rd -- )
 ARM-INSTRUCTION: CLS64-encode ( 1 1 0 11010110 00000 00010 1 Rn Rd -- )
@@ -550,9 +586,14 @@ ARM-INSTRUCTION: CMPsr64-encode ( 1 1 1 01011 shift2 0 Rm imm6 Rn Rd -- )
 
 ! CMPP: Compare with Tag: an alias of SUBPS.
 ARM-INSTRUCTION: CMPP-encode ( 1 0 1 11010110 Xm 0 0 0 0 0 0 Xn Xd -- )
+
 ! CNEG: Conditional Negate: an alias of CSNEG.
 ARM-INSTRUCTION: CNEG32-encode ( 0 1 0 11010100 Rm cond4 0 1 Rn Rd -- )
 ARM-INSTRUCTION: CNEG64-encode ( 1 1 0 11010100 Rm cond4 0 1 Rn Rd -- )
+
+! CNT: Population Count per byte.
+ARM-INSTRUCTION: CNT-encode ( 0 Q 0 01110 size2 10000 00101 10 Rn Rd -- )
+
 ! CPP: Cache Prefetch Prediction Restriction by Context: an alias of SYS.
 ARM-INSTRUCTION: CPP-encode ( 1101010100 0 01 011 0111 0011 111 Rt -- )
 
@@ -602,6 +643,7 @@ ARM-INSTRUCTION: CSNEG64-encode ( 1 1 0 11010100 Rm cond4 0 1 Rn Rd -- )
 
 ! DC: Data Cache operation: an alias of SYS.
 ARM-INSTRUCTION: DC-encode ( 1101010100 0 01 op3 0111 CRm op3 Rt -- )
+
 ! DCPS1: Debug Change PE State to EL1..
 ARM-INSTRUCTION: DCPS1-encode ( 11010100 101 imm16 000 01 -- )
 ! DCPS2: Debug Change PE State to EL2..
@@ -611,10 +653,16 @@ ARM-INSTRUCTION: DCPS3-encode ( 11010100 101 imm16 000 11 -- )
 
 ! DMB: Data Memory Barrier.
 ARM-INSTRUCTION: DMB-encode ( 1101010100 0 00 011 0011 CRm 1 01 11111 -- )
+
 ! DRPS: Debug restore process state.
 ARM-INSTRUCTION: DPRS-encode ( 1101011 0101 11111 000000 11111 00000 -- )
+
 ! DSB: Data Synchronization Barrier.
 ARM-INSTRUCTION: DSB-encode ( 1101010100 0 00 011 0011 CRm 1 00 11111 -- )
+
+! DUP (general): Duplicate general-purpose register to vector.
+ARM-INSTRUCTION: DUPgen-encode ( 0 Q 0 01110000 imm5 0 0001 1 Rn Rd -- )
+
 ! DVP: Data Value Prediction Restriction by Context: an alias of SYS.
 ARM-INSTRUCTION: DVP-encode ( 1101010100 0 01 011 0111 0011 101 Rt -- )
 
@@ -641,23 +689,59 @@ ARM-INSTRUCTION: ERETAB-encode ( 1101011 0 100 11111 0000 1 1 11111 11111 -- )
 ! ESB: Error Synchronization Barrier.
 ! ARMv8.2
 ARM-INSTRUCTION: ESB-encode ( 1101010100 0 00 011 0010 0010 000 11111 -- )
+
 ! EXTR: Extract register.
 ARM-INSTRUCTION: EXTR32-encode ( 0 00 100111 0 0 Rm imms Rn Rd -- )
 ARM-INSTRUCTION: EXTR64-encode ( 1 00 100111 1 0 Rm imms Rn Rd -- )
 
+! FADD (scalar): Floating-point Add (scalar).
+ARM-INSTRUCTION: FADDs-encode ( 0 0 0 11110 ftype 1 Rm 001 0 10 Rn Rd -- )
+
+! FCVT: Floating-point Convert percision (scalar).
+ARM-INSTRUCTION: FCVT-encode ( 0 0 0 11110 ftype 1 0001 opc2 10000 Rn Rd -- )
+
+! FCVTZS (scalar, integer): Floating-point Convert to Signed integer, rounding toward Zero (scalar).
+ARM-INSTRUCTION: FCVTZSsi64-encode ( 1 0 0 11110 ftype 1 11 000 000000 Rn Rd -- )
+
+! FDIV (scalar): Floating-point Divide (scalar).
+ARM-INSTRUCTION: FDIVs-encode ( 0 0 0 11110 ftype 1 Rm 0001 10 Rn Rd -- )
+
+! FMAX (scalar): Floating-point Maximum (scalar).
+ARM-INSTRUCTION: FMAXs-encode ( 0 0 0 11110 ftype 1 Rm 01 00 10 Rn Rd -- )
+
+! FMIN (scalar): Floating-point Minimum (scalar).
+ARM-INSTRUCTION: FMINs-encode ( 0 0 0 11110 ftype 1 Rm 01 01 10 Rn Rd -- )
+
+! FMOV (general): Floating-point Move to or from general-purpose register without conversion.
+ARM-INSTRUCTION: FMOVgen-encode ( sf 0 0 11110 ftype 1 rmode opc3 000000 Rn Rd -- )
+
+! FMUL (scalar): Floating-point Multiply (scalar).
+ARM-INSTRUCTION: FMULs-encode ( 0 0 0 11110 ftype 1 Rm 0 000 10 Rn Rd -- )
+
+! FSQRT (scalar): Floating-point Square Root (scalar).
+ARM-INSTRUCTION: FSQRTs-encode ( 0 0 0 11110 ftype 1 0000 11 10000 Rn Rd -- )
+
+! FSUB (scalar): Floating-point Subtract (scalar).
+ARM-INSTRUCTION: FSUBs-encode ( 0 0 0 11110 ftype 1 Rm 001 1 10 Rn Rd -- )
+
 ! GMI: Tag Mask Insert.
 ARM-INSTRUCTION: GMI-encode ( 1 0 0 11010110 Xm 0 0 0 1 0 1 Xn Xd -- )
+
 ! HINT: Hint instruction.
 ARM-INSTRUCTION: HINT-encode ( 1101010100 0 00 011 0010 CRm op3 11111 -- )
+
 ! HLT: Halt instruction.
 ARM-INSTRUCTION: HLT-encode ( 11010100 010 imm16 000 00 -- )
 
 ! HVC: Hypervisor Call.
 ARM-INSTRUCTION: HVC-encode ( 11010100 000 imm16 000 10 -- )
+
 ! IC: Instruction Cache operation: an alias of SYS.
 ARM-INSTRUCTION: IC-encode ( 1101010100 0 01 op3 0111 CRm op3 Rt -- )
+
 ! IRG: Insert Random Tag.
 ARM-INSTRUCTION: IRG-encode ( 1 0 0 11010110 Xm 0 0 0 1 0 0 Xn Xd -- )
+
 ! ISB: Instruction Synchronization Barrier.
 ARM-INSTRUCTION: ISB-encode ( 1101010100 0 00 011 0011 CRm 1 10 11111 -- )
 
@@ -773,9 +857,9 @@ ARM-INSTRUCTION: LDEORLH-encode  ( 01 111 0 00 0 1 1 Rs 0 010 00 Rn Rt -- )
 ! LDG: Load Allocation Tag.
 ! ARMv8.5
 ARM-INSTRUCTION: LDG-encode ( 11011001 0 1 1 imm9 0 0 Xn Xt -- )
-! LDGV: Load Allocation Tag.
+! LDGV: Load Tag Multiple.
 ! ARMv8.5
-ARM-INSTRUCTION: LDGV-encode ( 11011001 1 1 1 0 0 0 0 0 0 0 0 0 0 0 Xn Xt -- )
+ARM-INSTRUCTION: LDGM-encode ( 11011001 1 1 1 0 0 0 0 0 0 0 0 0 0 0 Xn Xt -- )
 
 ! LDLAR: Load LOAcquire Register.
 ! ARMv8.1
@@ -1288,6 +1372,9 @@ ARM-INSTRUCTION: SBFM64-encode ( 1 00 100110 1 immr imms Rn Rd -- )
 ARM-INSTRUCTION: SBFX32-encode ( 0 00 100110 0 immr imms Rn Rd -- )
 ARM-INSTRUCTION: SBFX64-encode ( 1 00 100110 1 immr imms Rn Rd -- )
 
+! SCVTF (scalar, integer): Signed integer Convert to Floting-point (scalar).
+ARM-INSTRUCTION: SCVTFsi64-encode ( 1 0 0 11110 ftype 1 00 010 000000 Rn Rd -- )
+
 ! SDIV: Signed Divide.
 ARM-INSTRUCTION: SDIV32-encode ( 0 0 0 11010110 Rm 00001 1 Rn Rd -- )
 ARM-INSTRUCTION: SDIV64-encode ( 1 0 0 11010110 Rm 00001 1 Rn Rd -- )