cpu.arm.assembler: Fix instructions

Bump SIGNAL_HANDLER_STACK_FRAME_SIZE

diff --git a/basis/bootstrap/assembler/arm.64.factor b/basis/bootstrap/assembler/arm.64.factor
index c868716aebca8ae6158c2358d717009382fb08be..f8c882b710700c1b7d3cf7453fd4b7ecdf3758c9 100644 (file)
--- a/basis/bootstrap/assembler/arm.64.factor
+++ b/basis/bootstrap/assembler/arm.64.factor
@@ -490,6 +490,7 @@ big-endian off
     ! ! windows 64 bit, but including it doesn't hurt. Plus
     ! ! alignment. LEA used so we don't dirty flags -> 192/64 bytes.
     ! stack-reg stack-reg 7 bootstrap-cells neg [+] LEA
+    4 bootstrap-cells stack-reg stack-reg SUBi
 
     jit-load-vm ;
 

diff --git a/basis/cpu/arm/assembler/32/32.factor b/basis/cpu/arm/assembler/32/32.factor
index c20dd1817b842a8232249fa2b4ad216a3140c1af..a81ebfa0867ab460d83c25683fcbdc821f001c3d 100644 (file)
--- a/basis/cpu/arm/assembler/32/32.factor
+++ b/basis/cpu/arm/assembler/32/32.factor
@@ -15,7 +15,7 @@ IN: cpu.arm.assembler.32
 : LSLi ( imm6 Rn Rd -- ) [ 6 ?ubits ] 2dip LSLi32-encode ;
 : LSRi ( imm6 Rn Rd -- ) [ 6 ?ubits ] 2dip LSRi32-encode ;
 
-: STRuoff ( imm12 Rn Rt -- ) [ 4 / 12 ?ubits ] 2dip STRuoff32-encode ;
+: STRuoff ( imm14 Rn Rt -- ) [ 4 / 12 ?ubits ] 2dip STRuoff32-encode ;
 
 : SUBi ( imm12 Rn Rd -- ) [ split-imm ] 2dip SUBi32-encode ;
 

diff --git a/basis/cpu/arm/assembler/64/64.factor b/basis/cpu/arm/assembler/64/64.factor
index 98733e4447c3d5c1ab617563af121749056abc3f..5e9611a1cd15574f4d61dcd3f7881c27c6a78f64 100644 (file)
--- a/basis/cpu/arm/assembler/64/64.factor
+++ b/basis/cpu/arm/assembler/64/64.factor
@@ -10,7 +10,7 @@ IN: cpu.arm.assembler.64
 : ADCS ( Rm Rn Rd -- ) ADCS64-encode ;
 
 : ADDi ( imm12 Rn Rd -- ) [ split-imm ] 2dip ADDi64-encode ;
-: ADDr ( Rm Rn Rd -- ) [ 0 0 ] 2dip ADDer64-encode ;
+: ADDr ( Rm Rn Rd -- ) [ 3 0 ] 2dip ADDer64-encode ;
 
 : ANDi ( imm64 Rn Rd -- ) [ encode-bitmask ] 2dip ANDi64-encode ;
 : ANDr ( Rm Rn Rd -- ) [ [ 0 ] dip 0 ] 2dip ANDsr64-encode ;
@@ -41,8 +41,8 @@ IN: cpu.arm.assembler.64
 : LDPsoff ( imm10 Rn Rt2 Rt -- ) [ 8 / 7 ?sbits ] 3dip swapd LDPsoff64-encode ;
 
 : LDRl ( imm21 Rt -- ) [ 4 / 19 ?sbits ] dip LDRl64-encode ;
-: LDRpost ( imm12 Rn Rt -- ) [ 8 / 9 ?sbits ] 2dip LDRpost64-encode ;
-: LDRpre ( imm12 Rn Rt -- ) [ 8 / 9 ?sbits ] 2dip LDRpre64-encode ;
+: LDRpost ( imm9 Rn Rt -- ) [ 9 ?sbits ] 2dip LDRpost64-encode ;
+: LDRpre ( imm9 Rn Rt -- ) [ 9 ?sbits ] 2dip LDRpre64-encode ;
 : LDRr ( Rm Rn Rt -- ) [ 3 0 ] 2dip LDRr64-encode ;
 : LDRuoff ( imm15 Rn Rt -- ) [ 8 / 12 ?ubits ] 2dip LDRuoff64-encode ;
 
@@ -86,8 +86,8 @@ IN: cpu.arm.assembler.64
 : STPpre ( imm10 Rn Rt2 Rt -- ) [ 8 / 7 ?sbits ] 3dip swapd STPpre64-encode ;
 : STPsoff ( imm10 Rn Rt2 Rt -- ) [ 8 / 7 ?sbits ] 3dip swapd STPsoff64-encode ;
 
-: STRpre ( imm12 Rn Rt -- ) [ 8 / 9 ?sbits ] 2dip STRpre64-encode ;
-: STRpost ( imm12 Rn Rt -- ) [ 8 / 9 ?sbits ] 2dip STRpost64-encode ;
+: STRpre ( imm9 Rn Rt -- ) [ 9 ?sbits ] 2dip STRpre64-encode ;
+: STRpost ( imm9 Rn Rt -- ) [ 9 ?sbits ] 2dip STRpost64-encode ;
 : STRr ( Rm Rn Rt -- ) [ 3 0 ] 2dip STRr64-encode ;
 : STRuoff ( imm15 Rn Rt -- ) [ 8 / 12 ?ubits ] 2dip STRuoff64-encode ;
 

diff --git a/basis/cpu/arm/assembler/opcodes/opcodes.factor b/basis/cpu/arm/assembler/opcodes/opcodes.factor
index 561c1fe4a9165daf2b4f4e7f0691f6967b321d73..793925677871aaadaca2a7b397a4aaf308e4d9c7 100644 (file)
--- a/basis/cpu/arm/assembler/opcodes/opcodes.factor
+++ b/basis/cpu/arm/assembler/opcodes/opcodes.factor
@@ -313,8 +313,8 @@ ARM-INSTRUCTION: ADC64-encode ( 1 0 0 11010000 Rm 000000 Rn Rd -- )
 ARM-INSTRUCTION: ADCS64-encode ( 1 0 1 11010000 Rm 000000 Rn Rd -- )
 
 ! ADD (extended register): Add (extended register).
-ARM-INSTRUCTION: ADDer32-encode ( 0 0 0 01011 00 0 Rm option3 imm3 Rn Rd -- )
-ARM-INSTRUCTION: ADDer64-encode ( 1 0 0 01011 00 0 Rm option3 imm3 Rn Rd -- )
+ARM-INSTRUCTION: ADDer32-encode ( 0 0 0 01011 00 1 Rm option3 imm3 Rn Rd -- )
+ARM-INSTRUCTION: ADDer64-encode ( 1 0 0 01011 00 1 Rm option3 imm3 Rn Rd -- )
 
 ! ADD (immediate): Add (immediate).
 ARM-INSTRUCTION: ADDi32-encode ( 0 0 0 10001 shift2 imm12 Rn Rd -- )
@@ -1454,11 +1454,11 @@ ARM-INSTRUCTION: STPsoff32-encode ( 00 101 0 010 0 imm7 Rt2 Rn Rt -- )
 ARM-INSTRUCTION: STPsoff64-encode ( 10 101 0 010 0 imm7 Rt2 Rn Rt -- )
 
 ! STR (immediate): Store Register (immediate).
-ARM-INSTRUCTION: STRpost32-encode ( 00 111 0 00 00 0 imm9 01 Rn Rt -- )
+ARM-INSTRUCTION: STRpost32-encode ( 10 111 0 00 00 0 imm9 01 Rn Rt -- )
 ARM-INSTRUCTION: STRpost64-encode ( 11 111 0 00 00 0 imm9 01 Rn Rt -- )
-ARM-INSTRUCTION: STRpre32-encode  ( 00 111 0 00 00 0 imm9 11 Rn Rt -- )
+ARM-INSTRUCTION: STRpre32-encode  ( 10 111 0 00 00 0 imm9 11 Rn Rt -- )
 ARM-INSTRUCTION: STRpre64-encode  ( 11 111 0 00 00 0 imm9 11 Rn Rt -- )
-ARM-INSTRUCTION: STRuoff32-encode ( 00 111 0 01 00 imm12 Rn Rt -- )
+ARM-INSTRUCTION: STRuoff32-encode ( 10 111 0 01 00 imm12 Rn Rt -- )
 ARM-INSTRUCTION: STRuoff64-encode ( 11 111 0 01 00 imm12 Rn Rt -- )
 
 ! STR (register): Store Register (register).

diff --git a/vm/os-linux-arm.64.hpp b/vm/os-linux-arm.64.hpp
index 2d32ec3ddd3ebda0a8c06a46a7510f6968317f86..39a6c388575c6af1286e039510fbdc0c0230e924 100644 (file)
--- a/vm/os-linux-arm.64.hpp
+++ b/vm/os-linux-arm.64.hpp
@@ -73,6 +73,6 @@ static const unsigned char call_opcode = 0x14;
 // last byte of 12 Br in absolute-jump
 static const unsigned char jmp_opcode = 0xd6;
 
-static const unsigned SIGNAL_HANDLER_STACK_FRAME_SIZE = 256;
+static const unsigned SIGNAL_HANDLER_STACK_FRAME_SIZE = 288;
 
 }

diff --git a/vm/os-macosx-arm64.hpp b/vm/os-macosx-arm64.hpp
index f9ab44f5e931869643c2607af0ad2009b7a84c94..78427d122ee78e1cc469af2230950beca691b309 100644 (file)
--- a/vm/os-macosx-arm64.hpp
+++ b/vm/os-macosx-arm64.hpp
@@ -151,7 +151,7 @@ static const unsigned char call_opcode = 0x14;
 // last byte of 12 Br in absolute-jump
 static const unsigned char jmp_opcode = 0xd6;
 
-static const unsigned SIGNAL_HANDLER_STACK_FRAME_SIZE = 256;
+static const unsigned SIGNAL_HANDLER_STACK_FRAME_SIZE = 288;