arm: update gifti's changes to not have the "64" suffix

diff --git a/basis/bootstrap/assembler/arm.64.factor b/basis/bootstrap/assembler/arm.64.factor
index 4e5b6f59367bb27a15799becbb48b792d2a9f7d2..8306971d8b4120cfe881c66b66c65875fbfec13e 100644 (file)
--- a/basis/bootstrap/assembler/arm.64.factor
+++ b/basis/bootstrap/assembler/arm.64.factor
@@ -479,26 +479,26 @@ big-endian off
     ! nv-reg PUSH
 
     vm-context-offset vm-reg ctx-reg LDR-uoff
-    8 SP ctx-reg STRuoff64
+    8 SP ctx-reg STRuoff
 
     ! ! Switch over to the spare context
     ! nv-reg vm-reg vm-spare-context-offset [+] MOV
     ! vm-reg vm-context-offset [+] nv-reg MOV
 
     vm-spare-context-offset vm-reg ctx-reg LDR-uoff
-    vm-context-offset vm-reg ctx-reg STRuoff64
+    vm-context-offset vm-reg ctx-reg STRuoff
 
     ! ! Save C callstack pointer
     ! nv-reg context-callstack-save-offset [+] stack-reg MOV
 
-    0 stack-reg temp0 ADDi64 ! MOV temp0, stack-reg
-    context-callstack-save-offset ctx-reg temp0 STRuoff64
+    0 stack-reg temp0 ADDi ! MOV temp0, stack-reg
+    context-callstack-save-offset ctx-reg temp0 STRuoff
 
     ! ! Load Factor stack pointers
     ! stack-reg nv-reg context-callstack-bottom-offset [+] MOV
 
     context-callstack-bottom-offset ctx-reg temp0 LDR-uoff
-    0 temp0 stack-reg ADDi64 ! MOV stack-reg, temp0
+    0 temp0 stack-reg ADDi ! MOV stack-reg, temp0
 
     ! rs-reg nv-reg context-retainstack-offset [+] MOV
     ! ds-reg nv-reg context-datastack-offset [+] MOV
@@ -519,14 +519,14 @@ big-endian off
 
     vm-context-offset vm-reg ctx-reg LDR-uoff
     context-callstack-save-offset ctx-reg temp0 LDR-uoff
-    0 temp0 stack-reg ADDi64 ! MOV stack-reg, temp0
+    0 temp0 stack-reg ADDi ! MOV stack-reg, temp0
 
     ! ! Load old context
     ! nv-reg POP
     ! vm-reg vm-context-offset [+] nv-reg MOV
 
     8 SP ctx-reg LDR-uoff
-    vm-context-offset vm-reg ctx-reg STRuoff64
+    vm-context-offset vm-reg ctx-reg STRuoff
 
     ! ! Restore non-volatile registers
     ! nv-regs <reversed> [ POP ] each

diff --git a/basis/cpu/arm/assembler/64/64-tests.factor b/basis/cpu/arm/assembler/64/64-tests.factor
new file mode 100644 (file)
index 0000000..e9eb7b6
--- /dev/null
+++ b/basis/cpu/arm/assembler/64/64-tests.factor
@@ -0,0 +1,9 @@
+! Copyright (C) 2023 Doug Coleman.
+! See https://factorcode.org/license.txt for BSD license.
+USING: cpu.arm.assembler.64 cpu.arm.assembler.opcodes make
+tools.test ;
+IN: cpu.arm.assembler.64.tests
+
+{ { 0x10 0x02 0x00 0x91 } } [ [ 0 X16 X16 ADDi ] { } make ] unit-test
+{ { 0x10 0x22 0x00 0x91 } } [ [ 8 X16 X16 ADDi ] { } make ] unit-test
+{ { 0x10 0xe2 0x3f 0x91 } } [ [ 0xff8 X16 X16 ADDi ] { } make ] unit-test

diff --git a/basis/cpu/arm/assembler/64/64.factor b/basis/cpu/arm/assembler/64/64.factor
index b21cefb3e683fc4b14a7ae35742295980af5e470..1489d8175fb5f9b2bcea7bdea1f1f18fc0fc9e8b 100644 (file)
--- a/basis/cpu/arm/assembler/64/64.factor
+++ b/basis/cpu/arm/assembler/64/64.factor
@@ -27,6 +27,7 @@ IN: cpu.arm.assembler.64
 : LDR-pre ( imm9 Rn Rt -- ) LDRpre64-encode ;
 : LDR-post ( imm9 Rn Rt -- ) LDRpost64-encode ;
 : LDR-uoff ( imm12 Rn Rt -- ) [ 8 / ] 2dip LDRuoff64-encode ;
+: LDR-literal ( imm19 Rt -- ) [ 4 / 19 bits ] dip LDRl64-encode ;
 
 : LDP-pre ( offset register-offset register-mid register -- )
     [ 8 / 7 bits ] 3dip swapd LDPpre64-encode ;
@@ -57,6 +58,12 @@ IN: cpu.arm.assembler.64
 : STP-signed-offset ( offset register-offset register-mid register -- )
     [ 8 / 7 bits ] 3dip swapd STPsoff64-encode ;
 
+: STR-pre ( imm9 Rn Rt -- )
+    [ 9 bits ] 2dip STRpre64-encode ;
+
+: STR-post ( imm9 Rn Rt -- )
+    [ 9 bits ] 2dip STRpost64-encode ;
+
 : STRr ( Rm Rn Rt -- )
     [ 0 0 ] 2dip STRr64-encode ;
 

diff --git a/basis/cpu/arm/assembler/assembler-tests.factor b/basis/cpu/arm/assembler/assembler-tests.factor
index c22e6927c9fbce104c916435e5ffa1b628953c9d..c3333a60c4d631ead07e429eebbd14764289cb8b 100644 (file)
--- a/basis/cpu/arm/assembler/assembler-tests.factor
+++ b/basis/cpu/arm/assembler/assembler-tests.factor
@@ -4,10 +4,6 @@ USING: cpu.arm.assembler cpu.arm.assembler.opcodes make
 tools.test ;
 IN: cpu.arm.assembler.tests
 
-{ { 0x10 0x02 0x00 0x91 } } [ [ 0 X16 X16 ADDi64 ] { } make ] unit-test
-{ { 0x10 0x22 0x00 0x91 } } [ [ 8 X16 X16 ADDi64 ] { } make ] unit-test
-{ { 0x10 0xe2 0x3f 0x91 } } [ [ 0xff8 X16 X16 ADDi64 ] { } make ] unit-test
-
 { { 0xb8 0x04 0x40 0x94 } } [ [ 0x04004b8 BL ] { } make ] unit-test
 { { 0x20 0x02 0x1f 0xd6 } } [ [ X17 BR ] { } make ] unit-test