it now compiles to something sensible

diff --git a/basis/bootstrap/assembler/arm.64.factor b/basis/bootstrap/assembler/arm.64.factor
index ccdaa046442c1663dafe0bcf35a0d7e7ae7c7160..adf7efc690c80e5c14bdc9666561aef51b32c1ca 100644 (file)
--- a/basis/bootstrap/assembler/arm.64.factor
+++ b/basis/bootstrap/assembler/arm.64.factor
@@ -94,9 +94,6 @@ big-endian off
 : temp2 ( -- reg ) X11 ;
 : temp3 ( -- reg ) X12 ;
 
-: nv-reg ( -- reg ) temp0 ; ! X19
-: link-reg* ( -- reg ) temp1 ;
-
 ! : pic-tail-reg ( -- reg ) RBX ;
 : return-reg ( -- reg ) X0 ;
 : stack-reg ( -- reg ) SP ;
@@ -106,7 +103,8 @@ big-endian off
 : vm-reg ( -- reg ) X28 ;
 : ds-reg ( -- reg ) X27 ;
 : rs-reg ( -- reg ) X26 ;
-! : ctx-reg ( -- reg ) R12 ;
+: ctx-reg ( -- reg ) X13 ;
+: word-reg ( -- reg ) X14 ;
 ! : fixnum>slot@ ( -- ) temp0 1 SAR ;
 ! : rex-length ( -- n ) 1 ;
 
@@ -451,6 +449,7 @@ big-endian off
 ! C to Factor entry point
 [
 
+    9999 BRK
     ! ! Optimizing compiler's side of callback accesses
     ! ! arguments that are on the stack via the frame pointer.
     ! ! On x86-32 fastcall, and x86-64, some arguments are passed
@@ -472,87 +471,75 @@ big-endian off
     -16 SP X28 X29 STP-pre
     -16 SP X30 STR-pre
 
-    jit-save-tib ! nop
-
     ! ! Load VM into vm-reg
     ! vm-reg 0 MOV 0 rc-absolute-cell rel-vm
-    0 vm-reg MOVwi64
-    0 rc-absolute-cell rel-vm
+
+    104 vm-reg LDR-literal
 
     ! ! Save old context
     ! nv-reg vm-reg vm-context-offset [+] MOV
     ! nv-reg PUSH
 
-    vm-context-offset vm-reg nv-reg LDR-uoff
-    -16 SP nv-reg STR-pre
+    vm-context-offset vm-reg ctx-reg LDR-uoff
+    8 SP ctx-reg STRuoff64
 
     ! ! Switch over to the spare context
     ! nv-reg vm-reg vm-spare-context-offset [+] MOV
     ! vm-reg vm-context-offset [+] nv-reg MOV
 
-    vm-spare-context-offset vm-reg nv-reg LDR-uoff
-    vm-context-offset vm-reg nv-reg STRuoff64
+    vm-spare-context-offset vm-reg ctx-reg LDR-uoff
+    vm-context-offset vm-reg ctx-reg STRuoff64
 
     ! ! Save C callstack pointer
     ! nv-reg context-callstack-save-offset [+] stack-reg MOV
 
-    context-callstack-save-offset nv-reg stack-reg STRuoff64
+    0 stack-reg temp0 ADDi64 ! MOV temp0, stack-reg
+    context-callstack-save-offset ctx-reg temp0 STRuoff64
 
     ! ! Load Factor stack pointers
     ! stack-reg nv-reg context-callstack-bottom-offset [+] MOV
-    ! nv-reg jit-update-tib
-    ! jit-install-seh
 
-    context-callstack-bottom-offset nv-reg stack-reg LDR-uoff
-    nv-reg jit-update-tib ! nop
-    jit-install-seh ! uh
+    context-callstack-bottom-offset ctx-reg temp0 LDR-uoff
+    0 temp0 stack-reg ADDi64 ! MOV stack-reg, temp0
 
     ! rs-reg nv-reg context-retainstack-offset [+] MOV
     ! ds-reg nv-reg context-datastack-offset [+] MOV
 
-    context-retainstack-offset nv-reg rs-reg LDR-uoff
-    context-datastack-offset nv-reg ds-reg LDR-uoff
+    context-retainstack-offset ctx-reg rs-reg LDR-uoff
+    context-datastack-offset ctx-reg ds-reg LDR-uoff
 
     ! ! Call into Factor code
     ! link-reg 0 MOV f rc-absolute-cell rel-word
     ! link-reg CALL
 
-    0 link-reg* MOVwi64
-    f rc-absolute-cell rel-word
-    link-reg* BLR
-
-    ! ! Load VM into vm-reg; only needed on x86-32, but doesn't
-    ! ! hurt on x86-64
-    ! vm-reg 0 MOV 0 rc-absolute-cell rel-vm
-
-    ! --?
+    68 word-reg LDR-literal
+    word-reg BLR
 
     ! ! Load C callstack pointer
     ! nv-reg vm-reg vm-context-offset [+] MOV
     ! stack-reg nv-reg context-callstack-save-offset [+] MOV
 
-    vm-context-offset vm-reg nv-reg LDR-uoff
-    context-callstack-save-offset nv-reg stack-reg LDR-uoff
+    vm-context-offset vm-reg ctx-reg LDR-uoff
+    context-callstack-save-offset ctx-reg temp0 LDR-uoff
+    0 temp0 stack-reg ADDi64 ! MOV stack-reg, temp0
 
     ! ! Load old context
     ! nv-reg POP
     ! vm-reg vm-context-offset [+] nv-reg MOV
 
-    16 SP nv-reg LDR-post
-    vm-context-offset vm-reg nv-reg LDR-uoff
+    8 SP ctx-reg LDR-uoff
+    vm-context-offset vm-reg ctx-reg STRuoff64
 
     ! ! Restore non-volatile registers
-    jit-restore-tib ! nop
-
     ! nv-regs <reversed> [ POP ] each
 
-    -16 SP X30 LDR-post
-    -16 SP X28 X29 LDP-post
-    -16 SP X26 X27 LDP-post
-    -16 SP X24 X25 LDP-post
-    -16 SP X22 X23 LDP-post
-    -16 SP X20 X21 LDP-post
-    -16 SP X18 X19 LDP-post
+    16 SP X30 LDR-post
+    16 SP X28 X29 LDP-post
+    16 SP X26 X27 LDP-post
+    16 SP X24 X25 LDP-post
+    16 SP X22 X23 LDP-post
+    16 SP X20 X21 LDP-post
+    16 SP X18 X19 LDP-post
 
     ! frame-reg POP
 
@@ -565,6 +552,9 @@ big-endian off
     f RET
     ! f rc-absolute-2 rel-untagged ! ?
 
+    NOP NOP 0 rc-absolute-cell rel-vm
+    NOP NOP f rc-absolute-cell rel-word
+
 ] CALLBACK-STUB jit-define
 
 [

diff --git a/basis/cpu/arm/assembler/assembler.factor b/basis/cpu/arm/assembler/assembler.factor
index f56eb8ebe77e880c50aadfbf0ac34ebf17830838..aade11ddf96aca1e49b9d013eb8230532e3a059e 100644 (file)
--- a/basis/cpu/arm/assembler/assembler.factor
+++ b/basis/cpu/arm/assembler/assembler.factor
@@ -24,6 +24,7 @@ ERROR: arm64-encoding-imm original n-bits-requested truncated ;
 : LDR-pre ( imm9 Rn Rt -- ) LDRpre64-encode ;
 : LDR-post ( imm9 Rn Rt -- ) LDRpost64-encode ;
 : LDR-uoff ( imm12 Rn Rt -- ) [ 8 / ] 2dip LDRuoff64-encode ;
+: LDR-literal ( imm19 Rt -- ) [ 4 / 19 bits ] dip LDRl64-encode ;
 
 : MOVwi64 ( imm Rt -- ) [ 0 ] 2dip MOVwi64-encode ;
 : MOVr64 ( Rn Rd -- ) MOVr64-encode ;
@@ -101,9 +102,11 @@ ERROR: imm-out-of-range imm n ;
 : STRr64 ( Rm Rn Rt -- )
     [ 0 0 ] 2dip STRr64-encode ;
 
-: STR-pre ( imm9 Rn Rt -- ) STRpre64-encode ;
+: STR-pre ( imm9 Rn Rt -- )
+    [ 9 bits ] 2dip STRpre64-encode ;
 
-: STR-post ( imm9 Rn Rt -- ) STRpost64-encode ;
+: STR-post ( imm9 Rn Rt -- )
+    [ 9 bits ] 2dip STRpost64-encode ;
 
 : ASRi32 ( imm6 Rn Rd -- ) [ 6 ?bits ] 2dip ASRi32-encode ;
 : ASRi64 ( imm6 Rn Rd -- ) [ 6 ?bits ] 2dip ASRi64-encode ;

diff --git a/basis/cpu/arm/assembler/opcodes/opcodes.factor b/basis/cpu/arm/assembler/opcodes/opcodes.factor
index 0240a18d90f4a2ea49b4846f6ddb03ea5c835948..fa87bbe2aec1b7af1f7050203c1d8143855d0ce4 100644 (file)
--- a/basis/cpu/arm/assembler/opcodes/opcodes.factor
+++ b/basis/cpu/arm/assembler/opcodes/opcodes.factor
@@ -836,7 +836,7 @@ ARM-INSTRUCTION: LDRuoff64-encode ( 11 111 0 01 01 imm12 Rn Rt -- )
 
 ! LDR (literal): Load Register (literal).
 ARM-INSTRUCTION: LDRl32-encode ( 00 011 0 00 imm19 Rt -- )
-ARM-INSTRUCTION: LDRl64-encode ( 00 011 0 00 imm19 Rt -- )
+ARM-INSTRUCTION: LDRl64-encode ( 01 011 0 00 imm19 Rt -- )
 
 ! LDR (register): Load Register (register).
 ARM-INSTRUCTION: LDRr32-encode ( 10 111 0 00 01 1 Rm option3 S 1 0 Rn Rt -- )
@@ -1490,9 +1490,9 @@ ARM-INSTRUCTION: STRr32-encode ( 10 111 0 00 00 1 Rm option3 S 10 Rn Rt -- )
 ARM-INSTRUCTION: STRr64-encode ( 11 111 0 00 00 1 Rm option3 S 10 Rn Rt -- )
 
 ! STRB (immediate): Store Register Byte (immediate).
-ARM-INSTRUCTION: STRpost-encode ( 00 111 0 00 00 0 imm9 01 Rn Rt -- )
-ARM-INSTRUCTION: STRpre-encode  ( 00 111 0 00 00 0 imm9 11 Rn Rt -- )
-ARM-INSTRUCTION: STRuoff-encode ( 00 111 0 01 00 imm12 Rn Rt -- )
+ARM-INSTRUCTION: STRBpost-encode ( 00 111 0 00 00 0 imm9 01 Rn Rt -- )
+ARM-INSTRUCTION: STRBpre-encode  ( 00 111 0 00 00 0 imm9 11 Rn Rt -- )
+ARM-INSTRUCTION: STRBuoff-encode ( 00 111 0 01 00 imm12 Rn Rt -- )
 
 ! STRB (register): Store Register Byte (register).
 ARM-INSTRUCTION: STRBext-encode   ( 00 111 0 00 00 1 Rm option3 S 10 Rn Rt -- )