Now you should have a complete Factor system ready to run.
Factor does not yet work on arm64 cpus. There is an arm64 assembler
-in `cpu.arm.assembler` and we are working on a port and also looking for
+in `cpu.arm.64.assembler` and we are working on a port and also looking for
contributors.
More information on [building factor](https://concatenative.org/wiki/view/Factor/Building%20Factor)
! Copyright (C) 2023 Giftpflanze.
! See https://factorcode.org/license.txt for BSD license.
USING: bootstrap.image.private compiler.codegen.relocation
-compiler.constants compiler.units cpu.arm.assembler
-cpu.arm.assembler.64 cpu.arm.assembler.opcodes
+compiler.constants compiler.units cpu.arm.64.assembler
generic.single.private kernel kernel.private layouts
locals.backend math math.private namespaces slots.private
strings.private threads.private vocabs ;
-RENAME: STRuoff cpu.arm.assembler.32 => STRuoff32
IN: bootstrap.assembler.arm
8 \ cell set
! X29/FP frame pointer
! X30/LR non-volatile link register
-: words ( n -- n ) 4 * ;
-: stack-frame-size ( -- n ) 8 bootstrap-cells ;
-
-: return-reg ( -- reg ) X0 ;
-: arg1 ( -- reg ) X0 ;
-: arg2 ( -- reg ) X1 ;
-: arg3 ( -- reg ) X2 ;
-: arg4 ( -- reg ) X3 ;
-: temp0 ( -- reg ) X9 ;
-: temp1 ( -- reg ) X10 ;
-: temp2 ( -- reg ) X11 ;
-: temp3 ( -- reg ) X12 ;
-: stack-reg ( -- reg ) SP ;
-: link-reg ( -- reg ) X30 ; ! LR
-: stack-frame-reg ( -- reg ) X29 ; ! FP
-: vm-reg ( -- reg ) X28 ;
-: ds-reg ( -- reg ) X27 ;
-: rs-reg ( -- reg ) X26 ;
-: ctx-reg ( -- reg ) X25 ;
+: words ( n -- n ) 4 * ; inline
+: stack-frame-size ( -- n ) 8 bootstrap-cells ; inline
+
+: return-reg ( -- reg ) X0 ; inline
+: arg1 ( -- reg ) X0 ; inline
+: arg2 ( -- reg ) X1 ; inline
+: arg3 ( -- reg ) X2 ; inline
+: arg4 ( -- reg ) X3 ; inline
+
+: temp0 ( -- reg ) X9 ; inline
+: temp1 ( -- reg ) X10 ; inline
+: temp2 ( -- reg ) X11 ; inline
+: temp3 ( -- reg ) X12 ; inline
+: pic-tail-reg ( -- reg ) X12 ; inline
+
+: stack-reg ( -- reg ) SP ; inline
+: link-reg ( -- reg ) X30 ; inline ! LR
+: stack-frame-reg ( -- reg ) X29 ; inline ! FP
+: vm-reg ( -- reg ) X28 ; inline
+: ds-reg ( -- reg ) X27 ; inline
+: rs-reg ( -- reg ) X26 ; inline
+: ctx-reg ( -- reg ) X25 ; inline
: push-link-reg ( -- ) -16 stack-reg link-reg STRpre ;
: pop-link-reg ( -- ) 16 stack-reg link-reg LDRpost ;
: absolute-jump ( -- word class )
2 words temp0 LDRl
temp0 BR
- NOP NOP f rc-absolute-cell ;
+ NOP NOP f rc-absolute-cell ; inline
: absolute-call ( -- word class )
5 words temp0 LDRl
temp0 BLR
pop-link-reg
3 words Br
- NOP NOP f rc-absolute-cell ;
+ NOP NOP f rc-absolute-cell ; inline
[
- ! pic-tail-reg 5 [RIP+] LEA
+ ! ! pic-tail-reg 5 [RIP+] LEA
! why do we store the address after JMP in EBX, where is it
! picked up?
- ! 0 JMP f rc-relative rel-word-pic-tail
+ 4 pic-tail-reg ADR
+ ! ! 0 JMP f rc-relative rel-word-pic-tail
+ ! 0 Br f rc-relative-arm64-branch rel-word-pic-tail
absolute-jump rel-word-pic-tail
] JIT-WORD-JUMP jit-define
[
- ! 0 CALL f rc-relative rel-word-pic
+ ! ! 0 CALL f rc-relative rel-word-pic
+ ! push-link-reg
+ ! 0 BL f rc-relative-arm64-branch rel-word-pic
+ ! pop-link-reg
absolute-call rel-word-pic
] JIT-WORD-CALL jit-define
[
! 0 [RIP+] EAX MOV rc-relative rel-safepoint
3 words temp0 LDRl
- 0 temp0 W0 STRuoff32
+ 0 temp0 W0 STRuoff
3 words Br
NOP NOP rc-absolute-cell rel-safepoint
] JIT-SAFEPOINT jit-define
! temp0 \ f type-number CMP
\ f type-number temp0 CMPi
! ! jump to true branch if not equal
- ! 0 JNE f rc-relative rel-word
+ ! ! 0 JNE f rc-relative rel-word
+ ! 0 NE B.cond f rc-relative-arm64-bcond rel-word
5 words EQ B.cond
absolute-jump rel-word
! ! jump to false branch if equal
- ! 0 JMP f rc-relative rel-word
+ ! ! 0 JMP f rc-relative rel-word
+ ! 0 Br f rc-relative-arm64-branch rel-word
absolute-jump rel-word
] JIT-IF jit-define
[
>r
- ! 0 CALL f rc-relative rel-word
+ ! ! 0 CALL f rc-relative rel-word
+ ! push-link-reg
+ ! 0 Br f rc-relative-arm64-branch rel-word
+ ! pop-link-reg
absolute-call rel-word
r>
] JIT-DIP jit-define
[
>r >r
- ! 0 CALL f rc-relative rel-word
+ ! ! 0 CALL f rc-relative rel-word
+ ! push-link-reg
+ ! 0 Br f rc-relative-arm64-branch rel-word
+ ! pop-link-reg
absolute-call rel-word
r> r>
] JIT-2DIP jit-define
[
>r >r >r
- ! 0 CALL f rc-relative rel-word
+ ! ! 0 CALL f rc-relative rel-word
+ ! push-link-reg
+ ! 0 Br f rc-relative-arm64-branch rel-word
+ ! pop-link-reg
absolute-call rel-word
r> r> r>
] JIT-3DIP jit-define
! ! make room for LR plus magic number of callback, 16byte align
! x64 ! stack-reg stack-frame-size bootstrap-cell - SUB
stack-frame-size stack-reg stack-reg SUBi
- -16 SP link-reg STRpre
+ push-link-reg
] JIT-PROLOG jit-define
[
! x64 ! stack-reg stack-frame-size bootstrap-cell - ADD
- 16 SP link-reg LDRpost
+ pop-link-reg
stack-frame-size stack-reg stack-reg ADDi
] JIT-EPILOG jit-define
] PIC-CHECK-TAG jit-define
[
- ! 0 JE f rc-relative rel-word
+ ! ! 0 JE f rc-relative rel-word
+ ! 0 EQ B.cond f rc-relative-arm64-bcond rel-word
5 words NE B.cond
absolute-jump rel-word
] PIC-HIT jit-define
context-callstack-bottom-offset ctx-reg arg1 LDRuoff
! ! Get top of callstack object -- 'src' for memcpy
! arg2 arg4 callstack-top-offset [+] LEA
- callstack-top-offset temp0 arg2 ADDr
+ callstack-top-offset temp0 arg2 ADDi
! ! Get callstack length, in bytes --- 'len' for memcpy
! arg3 arg4 callstack-length-offset [+] MOV
2 temp0 temp0 SUBi ! callstack-length-offset
jit-signal-handler-epilog
! Pop the fake leaf frame along with our return address
! leaf-stack-frame-size bootstrap-cell - RET
- leaf-stack-frame-size bootstrap-cell - SP SP ADDr
+ leaf-stack-frame-size bootstrap-cell - SP SP ADDi
f RET
] }
{ signal-handler [
! Copyright (C) 2020 Doug Coleman.
! See https://factorcode.org/license.txt for BSD license.
-USING: cpu.arm.assembler cpu.arm.assembler.opcodes cpu.arm.assembler.64
-kernel layouts parser sequences ;
+USING: kernel parser sequences ;
IN: bootstrap.assembler.arm
<< "resource:basis/bootstrap/assembler/arm.unix.factor" parse-file suffix! >> call
! Copyright (C) 2020 Doug Coleman.
! See https://factorcode.org/license.txt for BSD license.
-USING: bootstrap.image.private cpu.arm.assembler kernel
+USING: bootstrap.image.private cpu.arm.64.assembler kernel
kernel.private layouts locals.backend math.private namespaces
slots.private strings.private ;
IN: bootstrap.assembler.arm
big-endian off
! [ "bootstrap.assembler.arm" forget-vocab ] with-compilation-unit
-
CONSTANT: rc-absolute-2 10
CONSTANT: rc-absolute-1 11
CONSTANT: rc-absolute-ppc-2/2/2/2 12
+CONSTANT: rc-relative-arm64-branch 13
+CONSTANT: rc-relative-arm64-bcond 14
CONSTANT: rt-dlsym 0
CONSTANT: rt-entry-point 1
! Copyright (C) 2020 Doug Coleman.
! See https://factorcode.org/license.txt for BSD license.
-USING: ;
+USING: cpu.arm.32.assembler ;
IN: cpu.arm.32
-
! Copyright (C) 2023 Giftpflanze.
! See https://factorcode.org/license.txt for BSD license.
USING: accessors assocs compiler.cfg compiler.cfg.comparisons
-compiler.cfg.instructions compiler.cfg.intrinsics continuations
-cpu.architecture cpu.arm cpu.arm.assembler cpu.arm.assembler.64
-cpu.arm.assembler.opcodes generalizations kernel math math.order
-sequences system words.symbol ;
-FROM: cpu.arm.assembler => S D ;
+compiler.cfg.instructions compiler.cfg.intrinsics
+compiler.cfg.stack-frame compiler.codegen.labels
+compiler.codegen.relocation compiler.constants continuations
+cpu.architecture cpu.arm cpu.arm.64.assembler generalizations
+kernel layouts math math.order sequences system words.symbol ;
IN: cpu.arm.64
+<< ALIAS: eh? f >>
+
+: words ( n -- n ) 4 * ; inline
+
+: temp0 ( -- reg ) X9 ; inline
+: pic-tail-reg ( -- reg ) X12 ; inline
+
+: stack-reg ( -- reg ) SP ; inline
M: arm.64 frame-reg X29 ;
: vm-reg ( -- reg ) X28 ; inline
M: arm.64 ds-reg X27 ;
M: arm.64 %load-immediate ( reg val -- )
[ XZR MOVr ] [
{ 0 1 2 3 } [
- tuck -8 * shift 0xffff bitand
+ tuck -16 * shift 0xffff bitand
] with map>alist [ nip 0 = ] assoc-reject
unclip
overd first2 rot MOVZ
] if-zero ;
M: arm.64 %load-reference ( reg obj -- )
- ! [ swap 0 MOV rc-absolute-cell rel-literal ]
- ! [ \ f type-number MOV ] if* ;
- 2drop ;
+ [
+ 3 words rot LDRl
+ 3 words Br
+ NOP NOP rc-absolute-cell rel-literal
+ ] [ \ f type-number swap MOVwi ] if* ;
M: arm.64 %load-float 2drop ;
M: arm.64 %load-double 2drop ;
M: arm.64 %copy ( dst src rep -- )
2over eq? [ 3drop ] [
! [ [ ?spill-slot ] bi@ ] dip
- ! 2over [ register? ] both? [ copy-register* ] [ copy-memory* ] if
+ ! 2over [ register? ] both?
+ ! [ copy-register* ] [ copy-memory* ] if
3drop
] if ;
M: arm.64 %write-barrier 6 ndrop ;
M: arm.64 %write-barrier-imm 5drop ;
-M: arm.64 stack-frame-size ;
-M: arm.64 %call drop ;
-M: arm.64 %epilogue drop ;
-M: arm.64 %jump drop ;
-M: arm.64 %jump-label drop ;
-M: arm.64 %prologue drop ;
+M: arm.64 stack-frame-size
+ (stack-frame-size) cell + 16 align ;
+
+M: arm.64 %call
+ -16 stack-reg stack-reg STRpre
+ 0 BL rc-relative-arm64-branch rel-word-pic
+ 16 stack-reg stack-reg LDRpost ;
+
+M: arm.64 %epilogue
+ cell + 16 align [ stack-reg stack-reg ADDr ] unless-zero ;
+
+M: arm.64 %jump
+ 4 pic-tail-reg ADR
+ 0 Br rc-relative-arm64-branch rel-word-pic-tail ;
+
+M: arm.64 %jump-label
+ 0 Br rc-relative-arm64-branch label-fixup ;
+
+M: arm.64 %prologue
+ cell - 16 align [ stack-reg stack-reg SUBr ] unless-zero ;
+
M: arm.64 %return f RET ;
-M: arm.64 %safepoint ;
+
+M: arm.64 %safepoint
+ 3 words temp0 LDRl
+ 0 temp0 W0 STRuoff
+ 3 words Br
+ NOP NOP rc-absolute-cell rel-safepoint ;
M: arm.64 %compare 5drop ;
M: arm.64 %compare-imm 5drop ;
M: arm.64 machine-registers {
{
int-regs {
- X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
+ X0 X1 X2 X3 X4 X5 X6 X7
+ X8 X9 X10 X11 X12 X13 X14 X15
X19 X20 X21 X22 X23 X24
}
- }
- {
- float-regs
- {
+ } {
+ float-regs {
V0 V1 V2 V3 V4 V5 V6 V7
V16 V17 V18 V19 V20 V21 V22 V23 V24 V25 V26 V27 V28
V29 V30 V31
}
}
} ;
+
M: arm.64 param-regs drop {
{ int-regs { X0 X1 X2 X3 X4 X5 X6 X7 X8 } }
{ float-regs { V0 V1 V2 V3 V4 V5 V6 V7 } }
} ;
+
M: arm.64 return-regs {
{ int-regs { X0 X1 X2 X3 X4 X5 X6 X7 X8 } }
{ float-regs { V0 V1 V2 V3 V4 V5 V6 V7 } }
M: arm.64 %reload 3drop ;
M: arm.64 gc-root-offset ;
-M: arm.64 immediate-arithmetic? -2147483648 2147483647 between? ;
+M: arm.64 immediate-arithmetic?
+ -2147483648 2147483647 between? ;
+
M: arm.64 immediate-bitwise?
[ encode-bitmask drop t ] [ 2drop f ] recover ;
+
M: arm.64 immediate-comparand? drop eh? ;
M: arm.64 immediate-store? drop eh? ;
--- /dev/null
+! Copyright (C) 2020 Doug Coleman.
+! See https://factorcode.org/license.txt for BSD license.
+USING: cpu.arm.64.assembler make tools.test ;
+IN: cpu.arm.64.assembler.tests
+
+! useful for testing maybe: https://armconverter.com/
+
+{ { 0x2e 0x01 0x10 0x94 } } [ [ 0x04004b8 BL ] { } make ] unit-test
+{ { 0x20 0x02 0x1f 0xd6 } } [ [ X17 BR ] { } make ] unit-test
+
+{ { 0xc0 0x03 0x5f 0xd6 } } [ [ f RET ] { } make ] unit-test
+
+{ { 0x10 0x02 0x00 0x91 } } [ [ 0 X16 X16 ADDi ] { } make ] unit-test
+{ { 0x10 0x22 0x00 0x91 } } [ [ 8 X16 X16 ADDi ] { } make ] unit-test
+{ { 0x10 0xe2 0x3f 0x91 } } [ [ 0xff8 X16 X16 ADDi ] { } make ] unit-test
+
+! mov x29, #0x0
+{ { 0x1d 0x00 0x80 0xd2 } } [ [ 0 X29 MOVwi ] { } make ] unit-test
+{ { 0x1e 0x00 0x80 0xd2 } } [ [ 0 X30 MOVwi ] { } make ] unit-test
+{ { 0xe5 0x03 0x00 0xaa } } [ [ X0 X5 MOVr ] { } make ] unit-test
+
+{ { 0x20 0xfc 0x6c 0xd3 } } [ [ 44 X1 X0 LSRi ] { } make ] unit-test
+
+{ { 0xfd 0x7b 0xbf 0xa9 } } [ [ -16 SP X30 X29 STPpre ] { } make ] unit-test
+{ { 0xf0 0x7b 0xbf 0xa9 } } [ [ -16 SP X30 X16 STPpre ] { } make ] unit-test
+
+{ { 0x11 0xfe 0x47 0xf9 } } [ [ 4088 X16 X17 LDRuoff ] { } make ] unit-test
+{ { 0x11 0x02 0x40 0xf9 } } [ [ 0 X16 X17 LDRuoff ] { } make ] unit-test
+! ldr x17, [x16, #8]
+{ { 0x11 0x06 0x40 0xf9 } } [ [ 8 X16 X17 LDRuoff ] { } make ] unit-test
+
+! ldr x1, [sp]
+{ { 0xe1 0x03 0x40 0xf9 } } [ [ 0 SP X1 LDRuoff ] { } make ] unit-test
+
+{ { 0x08 0xed 0x7c 0x92 } } [ [ -16 X8 X8 ANDi ] { } make ] unit-test
+
+{ { 0x00 0x00 0x00 0x10 } } [ [ 0 X0 ADR ] { } make ] unit-test
+{ { 0x00 0x00 0x00 0x30 } } [ [ 1 X0 ADR ] { } make ] unit-test
+
+{ { 0x90 0x20 0x00 0xb0 } } [ [ 0x411000 X16 ADRP ] { } make ] unit-test
--- /dev/null
+! Copyright (C) 2020 Doug Coleman.
+! Copyright (C) 2023 Giftpflanze.
+! See https://factorcode.org/license.txt for BSD license.
+USING: accessors assocs combinators cpu.arm.64.assembler.opcodes
+generalizations grouping kernel lexer math math.bitwise
+math.parser parser sequences sequences.generalizations shuffle
+words words.symbol ;
+IN: cpu.arm.64.assembler
+
+<PRIVATE
+
+<<
+: name>ord ( str -- n )
+ dup 2 tail* { "ZR" "SP" } member?
+ [ drop 31 ] [ 1 tail string>number ] if ;
+
+SYNTAX: REGISTERS:
+ ";" [
+ create-word-in
+ [ define-symbol ]
+ [ dup name>> name>ord "ordinal" set-word-prop ] bi
+ ] each-token ;
+>>
+
+PRIVATE>
+
+! General purpose registers, 64bit
+REGISTERS: X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12
+X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25
+X26 X27 X28 X29 X30 XZR SP ;
+
+! Lower registers, shared with X0..X30, 32bit
+REGISTERS: W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12
+W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 W25
+W26 W27 W28 W29 W30 WZR WSP ;
+
+! https://static.docs.arm.com/ddi0487/fb/DDI0487F_b_armv8_arm.pdf pgA1-42
+! Neon registers (SIMD Scalar) Q/D/S/H/B 128/64/32/16/8 bits
+REGISTERS: V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12
+V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 V25
+V26 V27 V28 V29 V30 V31 ;
+
+REGISTERS: Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12
+Q13 Q14 Q15 Q16 Q17 Q18 Q19 Q20 Q21 Q22 Q23 Q24 Q25
+Q26 Q27 Q28 Q29 Q30 Q31 ;
+
+REGISTERS: D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12
+D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25
+D26 D27 D28 D29 D30 D31 ;
+
+REGISTERS: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12
+S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25
+S26 S27 S28 S29 S30 S31 ;
+
+REGISTERS: H0 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12
+H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25
+H26 H27 H28 H29 H30 H31 ;
+
+REGISTERS: B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12
+B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25
+B26 B27 B28 B29 B30 B31 ;
+
+! Condition codes
+: EQ ( -- cond ) 0b0000 ; inline ! Z set: equal
+: NE ( -- cond ) 0b0001 ; inline ! Z clear: not equal
+: CS ( -- cond ) 0b0010 ; inline ! C set: unsigned higher or same
+: HS ( -- cond ) 0b0010 ; inline !
+: CC ( -- cond ) 0b0011 ; inline ! C clear: unsigned lower
+: LO ( -- cond ) 0b0011 ; inline !
+: MI ( -- cond ) 0b0100 ; inline ! N set: negative
+: PL ( -- cond ) 0b0101 ; inline ! N clear: positive or zero
+: VS ( -- cond ) 0b0110 ; inline ! V set: overflow
+: VC ( -- cond ) 0b0111 ; inline ! V clear: no overflow
+: HI ( -- cond ) 0b1000 ; inline ! C set and Z clear: unsigned higher
+: LS ( -- cond ) 0b1001 ; inline ! C clear or Z set: unsigned lower or same
+: GE ( -- cond ) 0b1010 ; inline ! N equals V: greater or equal
+: LT ( -- cond ) 0b1011 ; inline ! N not equal to V: less than
+: GT ( -- cond ) 0b1100 ; inline ! Z clear AND (N equals V): greater than
+: LE ( -- cond ) 0b1101 ; inline ! Z set OR (N not equal to V): less than or equal
+: AL ( -- cond ) 0b1110 ; inline ! always
+: NV ( -- cond ) 0b1111 ; inline ! always
+
+! SIMD Arrangement specifiers
+: 8B ( -- size Q ) 0 0 ; inline
+: 16B ( -- size Q ) 0 1 ; inline
+: 4H ( -- size Q ) 1 0 ; inline
+: 8H ( -- size Q ) 1 1 ; inline
+: 2S ( -- size Q ) 2 0 ; inline
+: 4S ( -- size Q ) 2 1 ; inline
+: 2D ( -- size Q ) 3 1 ; inline
+
+! FMOVgen variants
+: HW ( -- sf ftype rmode opcode ) 0 3 0 6 ; inline
+: HX ( -- sf ftype rmode opcode ) 1 3 0 6 ; inline
+: WH ( -- sf ftype rmode opcode ) 0 3 0 7 ; inline
+: WS ( -- sf ftype rmode opcode ) 0 0 0 7 ; inline
+: SW ( -- sf ftype rmode opcode ) 0 0 0 6 ; inline
+: XH ( -- sf ftype rmode opcode ) 1 3 0 7 ; inline
+: XD ( -- sf ftype rmode opcode ) 1 1 0 7 ; inline
+: XD[1] ( -- sf ftype rmode opcode ) 1 2 0 7 ; inline
+: DX ( -- sf ftype rmode opcode ) 1 1 0 6 ; inline
+: D[1]X ( -- sf ftype rmode opcode ) 1 2 0 6 ; inline
+
+! Floating-point variants
+: H ( -- ftype ) 3 ; inline
+: S ( -- ftype ) 0 ; inline
+: D ( -- ftype ) 1 ; inline
+
+! Special-purpose registers
+: FPCR ( -- op0 op1 CRn CRm op2 ) 3 3 4 4 0 ;
+: FPSR ( -- op0 op1 CRn CRm op2 ) 3 3 4 4 1 ;
+: NZCV ( -- op0 op1 CRn CRm op2 ) 3 3 4 2 0 ;
+
+<PRIVATE
+
+ERROR: arm64-encoding-imm original n-bits-requested truncated ;
+: ?ubits ( x n -- x )
+ 2dup bits dup reach =
+ [ 2drop ] [ arm64-encoding-imm ] if ; inline
+
+: ?sbits ( x n -- x )
+ 2dup >signed dup reach =
+ [ drop bits ] [ arm64-encoding-imm ] if ; inline
+
+ERROR: scaling-error original n-bits-shifted rest ;
+: ?>> ( x n -- x )
+ 2dup bits [ neg shift ] [ scaling-error ] if-zero ;
+
+! Some instructions allow an immediate literal of n bits
+! or n bits shifted. This means there are invalid immediate
+! values, e.g. imm12 of 1, 4096, but not 4097
+ERROR: imm-out-of-range imm n ;
+: imm-lower? ( imm n -- ? ) on-bits unmask 0 > not ;
+
+: imm-upper? ( imm n -- ? )
+ [ on-bits ] [ shift ] bi unmask 0 > not ;
+
+: (split-imm) ( imm n -- imm upper? )
+ {
+ { [ 2dup imm-lower? ] [ drop f ] }
+ { [ 2dup imm-upper? ] [ drop t ] }
+ [ imm-out-of-range ]
+ } cond ;
+
+: split-imm ( imm -- shift imm ) 12 (split-imm) 1 0 ? swap ;
+
+: ADR-split ( simm21 -- immlo immhi )
+ [ 2 bits ] [ -2 shift 19 ?sbits ] bi ;
+
+! Logical immediates
+
+ERROR: illegal-bitmask-immediate n ;
+: ?bitmask ( imm imm-size -- imm )
+ dupd on-bits 0 [ = ] bi-curry@ bi or
+ [ dup illegal-bitmask-immediate ] when ;
+
+: element-size ( imm imm-size -- imm element-size )
+ [ 2dup 2/ [ neg shift ] 2keep '[ _ on-bits bitand ] same? ]
+ [ 2/ ] while ;
+
+: bit-transitions ( imm element-size -- seq )
+ [ >bin ] dip CHAR: 0 pad-head 2 circular-clump ;
+
+ERROR: illegal-bitmask-element n ;
+: ?element ( imm element-size -- element )
+ [ bits ] keep dupd bit-transitions
+ [ first2 = not ] count 2 =
+ [ dup illegal-bitmask-element ] unless ;
+
+: >Nimms ( element element-size -- N imms )
+ [ bit-count 1 - ] [ log2 1 + ] bi*
+ 7 [ on-bits ] bi@ bitxor bitor
+ 6 toggle-bit [ -6 shift ] [ 6 bits ] bi ;
+
+: >immr ( element element-size -- immr )
+ [ bit-transitions "10" swap index 1 + ] keep mod ;
+
+: (encode-bitmask) ( imm imm-size -- (N)immrimms )
+ [ bits ] [ ?bitmask ] [ element-size ] tri
+ [ ?element ] keep [ >Nimms ] [ >immr ] 2bi
+ { 12 0 6 } bitfield* ;
+
+ERROR: register-mismatch registers ;
+MACRO: bw ( n -- quot ) ! ( ... -- bw ... )
+ dup '[
+ [
+ _ narray [
+ name>> dup "SP" = [ drop "X" ] when first
+ ] map
+ dup all-equal? [ register-mismatch ] unless
+ first CHAR: X = 1 0 ?
+ ] _ nkeep
+ ] ;
+
+: 1bw ( Rt -- bw Rt ) 1 bw ;
+: 2bw ( Rn Rd -- bw Rn Rd ) 2 bw ;
+: 3bw ( Rm Rn Rd -- bw Rm Rn Rd ) 3 bw ;
+: 4bw ( Ra Rm Rn Rd -- bw Ra Rm Rn Rd ) 4 bw ;
+
+: (load/store-pair) ( simm10 Rn Rt2 Rt -- bw imm7 Rt2 Rn Rt )
+ 2bw [ -rot [ 3 ?>> 7 ?sbits ] dip ] 2dip swapd ;
+
+PRIVATE>
+
+: encode-bitmask ( imm64 -- Nimmrimms ) 64 (encode-bitmask) ;
+
+
+: ADC ( Rm Rn Rd -- ) 3bw ADC-encode ;
+: ADCS ( Rm Rn Rd -- ) 3bw ADCS-encode ;
+
+: ADDi ( uimm12 Rn Rd -- ) 2bw [ swap split-imm ] 2dip ADDi-encode ;
+: ADDr ( Rm Rn Rd -- ) 3bw [ 3 0 ] 2dip ADDer-encode ;
+
+: ADDV ( Vn Rd size Q -- ) -roll -rot ADDV-encode ;
+
+: ADR ( simm21 Xd -- ) [ ADR-split ] dip ADR-encode ;
+: ADRP ( simm33 Xd -- ) [ 12 ?>> ADR-split ] dip ADRP-encode ;
+
+: ANDi ( imm64 Rn Rd -- ) 2bw [ swap encode-bitmask ] 2dip ANDi-encode ;
+: ANDr ( Rm Rn Rd -- ) 3bw [ 0 0 -rot ] 2dip ANDsr-encode ;
+
+: ASRi ( uimm6 Rn Rd -- ) 2bw [ swap 6 ?ubits ] 2dip ASRi-encode ;
+: ASRr ( Rm Rn Rd -- ) 3bw ASRr-encode ;
+
+! B but that is breakpoint
+: Br ( simm28 -- ) 2 ?>> 26 ?sbits B-encode ;
+: BR ( Rn -- ) BR-encode ;
+
+: B.cond ( simm21 cond -- ) [ 2 ?>> 19 ?sbits ] dip B.cond-encode ;
+
+: BL ( simm28 -- ) 2 ?>> 26 ?sbits BL-encode ;
+: BLR ( Rn -- ) BLR-encode ;
+
+: BIC ( Rm Rn Rd -- ) 3bw [ 0 0 -rot ] 2dip BIC-encode ;
+
+: BRK ( uimm16 -- ) 16 ?ubits BRK-encode ;
+
+: CBNZ ( simm21 Rt -- ) 1bw [ swap 2 ?>> 19 ?sbits ] dip CBNZ-encode ;
+
+: CLZ ( Rn Rd -- ) 2bw CLZ-encode ;
+
+: CMPi ( imm12 Rn -- ) 1bw [ swap split-imm ] dip CMPi-encode ;
+: CMPr ( Rm Rn -- ) 2bw [ 3 0 ] dip CMPer-encode ;
+
+: CNT ( Vn Vd size Q -- ) -roll -rot CNT-encode ;
+
+! cond is EQ NE CS HS CC LO MI PL VS VC HI LS GE LT GT LE AL NV
+: CSEL ( Rm Rn Rd cond -- ) [ 3bw ] dip -rot CSEL-encode ;
+: CSET ( Rd cond -- ) [ 1bw ] dip swap CSET-encode ;
+: CSETM ( Rd cond -- ) [ 1bw ] dip swap CSETM-encode ;
+
+: DUPgen ( Rn Rd size Q -- ) -roll 2^ -rot DUPgen-encode ;
+
+: EORi ( imm64 Rn Rd -- ) 2bw [ swap encode-bitmask ] 2dip EORi-encode ;
+: EORr ( Rm Rn Rd -- ) 3bw [ 0 0 -rot ] 2dip EORsr-encode ;
+
+: FADDs ( Rm Rn Rd var -- ) -roll FADDs-encode ;
+
+: FCVT ( Rn Rd svar dvar -- ) 2swap FCVT-encode ;
+: FCVTZSsi ( Rn Rd var -- ) [ 2bw ] dip -rot FCVTZSsi-encode ;
+
+: FDIVs ( Rm Rn Rd var -- ) -roll FDIVs-encode ;
+
+: FMAXs ( Rm Rn Rd var -- ) -roll FMAXs-encode ;
+: FMINs ( Rm Rn Rd var -- ) -roll FMINs-encode ;
+
+: FMOVgen ( Rn Rd sf ftype rmode opcode -- ) 4 2 mnswap FMOVgen-encode ;
+
+: FMULs ( Rm Rn Rd var -- ) -roll FMULs-encode ;
+
+: FSQRTs ( Rn Rd var -- ) -rot FSQRTs-encode ;
+
+: FSUBs ( Rm Rn Rd var -- ) -roll FSUBs-encode ;
+
+: HLT ( uimm16 -- ) 16 ?ubits HLT-encode ;
+
+: LDPpost ( simm10 Rn Rt2 Rt -- ) (load/store-pair) LDPpost-encode ;
+: LDPpre ( simm10 Rn Rt2 Rt -- ) (load/store-pair) LDPpre-encode ;
+: LDPsoff ( simm10 Rn Rt2 Rt -- ) (load/store-pair) LDPsoff-encode ;
+
+: LDRl ( simm21 Rt -- ) 1bw [ swap 2 ?>> 19 ?sbits ] dip LDRl-encode ;
+: LDRpost ( simm9 Rn Rt -- ) 2bw [ swap 9 ?sbits ] 2dip LDRpost-encode ;
+: LDRpre ( simm9 Rn Rt -- ) 2bw [ swap 9 ?sbits ] 2dip LDRpre-encode ;
+: LDRr ( Rm Rn Rt -- ) 3bw [ 3 0 ] 2dip LDRr-encode ;
+
+: LDRuoff ( uimm14/15 Rn Rt -- ) 1bw -rotd [ over 2 + ?>> 12 ?ubits ] 2dip LDRuoff-encode ;
+
+: LDRBr ( Rm Rn Rt -- ) [ 0 ] 2dip LDRBsr-encode ;
+: LDRBuoff ( uimm12 Rn Rt -- ) [ 12 ?ubits ] 2dip LDRBuoff-encode ;
+: LDRHuoff ( uimm13 Rn Rt -- ) [ 1 ?>> 12 ?ubits ] 2dip LDRHuoff-encode ;
+
+: LDUR ( simm9 Rn Rt -- ) 2bw [ swap 9 ?sbits ] 2dip LDUR-encode ;
+
+: LSLi ( uimm6 Rn Rd -- ) 2bw [ tuck [ dup ] 2dip 6 ?ubits ] 2dip LSLi-encode ;
+: LSLr ( Rm Rn Rd -- ) 3bw LSLr-encode ;
+
+: LSRi ( uimm6 Rn Rd -- ) 2bw [ tuck [ dup ] 2dip 6 ?ubits ] 2dip LSRi-encode ;
+: LSRr ( Rm Rn Rd -- ) 3bw LSRr-encode ;
+
+: MOVr ( Rn Rd -- ) 2bw MOVr-encode ;
+: MOVsp ( Rn Rd -- ) 2bw [ 0 ] 2dip MOVsp-encode ;
+: MOVwi ( imm16 Rd -- ) 1bw [ 0 rot 16 bits ] dip MOVwi-encode ;
+: MOVZ ( lsl imm16 Rd -- ) 1bw -rotd [ 16 bits ] dip MOVZ-encode ;
+: MOVK ( lsl imm16 Rd -- ) 1bw -rotd [ 16 bits ] dip MOVK-encode ;
+
+: MRS ( op0 op1 CRn CRm op2 Rt -- ) MRS-encode ;
+: MSRr ( op0 op1 CRn CRm op2 Rt -- ) MSRr-encode ;
+
+: MSUB ( Ra Rm Rn Rd -- ) 4bw [ swap ] 2dip MSUB-encode ;
+
+: MUL ( Rm Rn Rd -- ) 3bw MUL-encode ;
+
+: MVN ( Rm Rd -- ) 2bw [ 0 0 -rot ] dip MVN-encode ;
+
+: NEG ( Rm Rd -- ) 2bw [ 0 0 -rot ] dip NEG-encode ;
+
+: NOP ( -- ) NOP-encode ;
+
+: ORRi ( imm64 Rn Rd -- ) 2bw [ swap encode-bitmask ] 2dip ORRi-encode ;
+: ORRr ( Rm Rn Rd -- ) 3bw [ 0 0 -rot ] 2dip ORRsr-encode ;
+
+: RET ( Rn/f -- ) X30 or RET-encode ;
+
+: SCVTFsi ( Rn Rd var -- ) [ 2bw ] dip -rot SCVTFsi-encode ;
+
+: SDIV ( Rm Rn Rd -- ) 3bw SDIV-encode ;
+
+: STADD ( Rs Rn -- ) 2bw STADD-encode ;
+
+: STPpost ( simm10 Rn Rt2 Rt -- ) (load/store-pair) STPpost-encode ;
+: STPpre ( simm10 Rn Rt2 Rt -- ) (load/store-pair) STPpre-encode ;
+: STPsoff ( simm10 Rn Rt2 Rt -- ) (load/store-pair) STPsoff-encode ;
+
+: STRpost ( simm9 Rn Rt -- ) 2bw [ swap 9 ?sbits ] 2dip STRpost-encode ;
+: STRpre ( simm9 Rn Rt -- ) 2bw [ swap 9 ?sbits ] 2dip STRpre-encode ;
+: STRr ( Rm Rn Rt -- ) 3bw [ 3 0 ] 2dip STRr-encode ;
+: STRuoff ( uimm14/15 Rn Rt -- ) 1bw -rotd [ over 2 + ?>> 12 ?ubits ] 2dip STRuoff-encode ;
+
+: SUBi ( uimm12 Rn Rd -- ) 2bw [ swap split-imm ] 2dip SUBi-encode ;
+: SUBr ( Rm Rn Rd -- ) 3bw [ 3 0 ] 2dip SUBer-encode ;
+
+: SVC ( uimm16 -- ) 16 ?ubits SVC-encode ;
+
+: TSTi ( imm64 Rn -- ) 1bw [ swap encode-bitmask ] dip TSTi-encode ;
--- /dev/null
+Doug Coleman
+Giftpflanze
--- /dev/null
+Doug Coleman
+Giftpflanze
--- /dev/null
+! Copyright (C) 2020 Doug Coleman.
+! See https://factorcode.org/license.txt for BSD license.
+USING: cpu.arm.64.assembler cpu.arm.64.assembler.opcodes make
+math math.bitwise tools.test ;
+IN: cpu.arm.64.assembler.opcodes.tests
+
+{ { 0x41 0x0 0x3 0x1a } } [ [ 0 W3 W2 W1 ADC-encode ] { } make ] unit-test
+{ { 0x41 0x0 0x3 0x3a } } [ [ 0 W3 W2 W1 ADCS-encode ] { } make ] unit-test
+{ { 0x41 0x0 0x3 0x5a } } [ [ 0 W3 W2 W1 SBC-encode ] { } make ] unit-test
+{ { 0x41 0x0 0x3 0x7a } } [ [ 0 W3 W2 W1 SBCS-encode ] { } make ] unit-test
+{ { 0x41 0x0 0x3 0x9a } } [ [ 1 X3 X2 X1 ADC-encode ] { } make ] unit-test
+{ { 0x41 0x0 0x3 0xba } } [ [ 1 X3 X2 X1 ADCS-encode ] { } make ] unit-test
+{ { 0x41 0x0 0x3 0xda } } [ [ 1 X3 X2 X1 SBC-encode ] { } make ] unit-test
+{ { 0x41 0x0 0x3 0xfa } } [ [ 1 X3 X2 X1 SBCS-encode ] { } make ] unit-test
+
+{ { 0xfd 0x03 0x00 0x91 } } [ [ 1 0 SP X29 MOVsp-encode ] { } make ] unit-test
+
+! stp x29, x30, [sp, #-16]!
+{ { 0xfd 0x7b 0xbf 0xa9 } } [ [ 1 -16 8 / 7 bits X30 SP X29 STPpre-encode ] { } make ] unit-test
--- /dev/null
+! Copyright (C) 2020 Doug Coleman.
+! Copyright (C) 2023 Giftpflanze.
+! See https://factorcode.org/license.txt for BSD license.
+USING: accessors assocs classes.error classes.parser effects
+effects.parser endian kernel lexer make math math.bitwise
+math.parser multiline parser sequences vocabs.parser words
+words.symbol ;
+IN: cpu.arm.64.assembler.opcodes
+
+! https://developer.arm.com/documentation/ddi0487/latest/
+! https://static.docs.arm.com/ddi0487/fb/DDI0487F_b_armv8_arm.pdf ! initial work
+! https://static.docs.arm.com/ddi0487/fb/DDI0487G_a_armv8_arm.pdf ! 3/13/21
+
+<<
+GENERIC: register ( obj -- n )
+M: word register "ordinal" word-prop ;
+M: integer register ;
+: error-word ( word -- new-class )
+ name>> "-range" append create-class-in dup save-location
+ tuple
+ { "value" }
+ [ define-error-class ] keepdd ;
+
+: make-checker-word ( word n -- )
+ [ drop dup error-word ]
+ [ nip swap '[ dup _ on-bits > [ _ execute( value -- * ) ] when ] ]
+ [ 2drop ( n -- n ) ] 2tri
+ define-declared ;
+
+SYNTAX: FIELD:
+ scan-new-word scan-object
+ [ "width" set-word-prop ] 2keep
+ make-checker-word ;
+
+: make-register-checker-word ( word n -- )
+ [ drop dup error-word '[ _ execute( value -- * ) ] ]
+ [ nip swap '[ register dup _ on-bits > _ when ] ]
+ [ 2drop ( n -- n ) ] 2tri
+ define-declared ;
+
+SYNTAX: REGISTER-FIELD:
+ scan-new-word scan-object
+ [ "width" set-word-prop ] 2keep
+ make-register-checker-word ;
+>>
+
+<<
+FIELD: bw 1
+FIELD: !bw 1
+
+FIELD: op1 1
+FIELD: op2 2
+FIELD: op3 3
+FIELD: op4 4
+FIELD: op5 5
+FIELD: op6 6
+FIELD: op7 7
+FIELD: op8 8
+FIELD: op9 9
+FIELD: op10 10
+
+FIELD: opc1 1
+FIELD: opc2 2
+FIELD: opc3 3
+FIELD: opc4 4
+
+FIELD: option1 1
+FIELD: option2 2
+FIELD: option3 3
+FIELD: option4 4
+FIELD: option5 5
+
+FIELD: a1 1
+FIELD: b1 1
+FIELD: c1 1
+FIELD: d1 1
+FIELD: e1 1
+FIELD: f1 1
+FIELD: g1 1
+FIELD: h1 1
+
+FIELD: A 1
+FIELD: D 1
+FIELD: L 1
+FIELD: M 1
+FIELD: N 1
+FIELD: Q 1
+FIELD: S 1
+FIELD: U 1
+FIELD: Z 1
+
+FIELD: sf 1
+FIELD: ftype 2
+FIELD: rmode 2
+
+FIELD: size1 1
+FIELD: size2 2
+
+FIELD: shift2 2
+
+FIELD: b40 5
+
+FIELD: immr 6
+FIELD: imms 6
+FIELD: immrimms 12
+FIELD: Nimmrimms 13
+FIELD: (N)immrimms 13
+FIELD: imm3 3
+FIELD: imm4 4
+FIELD: imm5 5
+FIELD: imm6 6
+FIELD: imm7 7
+FIELD: imm9 9
+FIELD: imm12 12
+FIELD: imm13 13
+FIELD: imm14 14
+FIELD: imm16 16
+FIELD: imm19 19
+FIELD: imm26 26
+
+FIELD: simm7 7
+FIELD: uimm4 4
+FIELD: uimm6 6
+
+FIELD: immlo2 2
+FIELD: immhi19 19
+
+FIELD: cond4 4
+FIELD: CRm 4
+FIELD: CRn 4
+FIELD: nzcv 4
+FIELD: hw2 2
+FIELD: mask4 4
+
+REGISTER-FIELD: Ra 5
+REGISTER-FIELD: Rm 5
+REGISTER-FIELD: Rn 5
+REGISTER-FIELD: Rd 5
+REGISTER-FIELD: Rs 5
+REGISTER-FIELD: Rt 5
+REGISTER-FIELD: Rt2 5
+REGISTER-FIELD: Xd 5
+REGISTER-FIELD: Xm 5
+REGISTER-FIELD: Xn 5
+REGISTER-FIELD: Xt 5
+REGISTER-FIELD: Xt2 5
+
+! Stack Pointer EL0 is 64bit, rest are 32bit
+SINGLETONS: SP_EL0 SP_EL1 SP_EL2 SP_EL3 ;
+
+! Exception link registers, 64bit
+SINGLETONS: ELR_EL1 ELR_EL2 ELR_EL3 ;
+
+! Saved program status registers, exception level, 64bit
+SINGLETONS: SPSR_EL1 SPSR_EL2 SPSR_EL3 ;
+
+! Program counter, 64bit
+! SINGLETONS: PC ; ! not accessible (?)
+
+! Flags: N negative, Z zero, C carry, V overflow, SS software step, IL illegal execution
+! D debug, A SError system error, I IRQ normal interrupt, F FIQ fast interrupt
+
+! Distinct L1 I-cache (instruction) and D-cache (data), unified L2 cache
+! 4kb page size alignment, unaligned accepted
+
+! PCS Procedure Call Standard X0-X7 parameters/results registers
+! X9-X15 caller-saved temp regs (use)
+! X19-X29 callee-saved (preserved)
+! X8 indirect result register, syscalls register
+! X16 X17 are IP0 and IP1, intra-procedure temp regs (avoid)
+! X18 platform-register (avoid)
+! X29 FP frame pointer register (avoid)
+! X30 LR link register (avoid)
+
+![[
+(bits(N), bit) LSL_C(bits(N) x, integer shift)
+ assert shift > 0;
+ shift = if shift > N then N else shift;
+ extended_x = x : Zeros(shift);
+ result = extended_x<N-1:0>;
+ carry_out = extended_x<N>;
+ return (result, carry_out);
+]]
+
+! Instructions
+
+ERROR: no-field-word vocab name ;
+
+TUPLE: integer-literal value width ;
+C: <integer-literal> integer-literal
+
+! handle 1xx0 where x = dontcare
+: make-integer-literal ( string -- integer-literal )
+ [ "0b" prepend { { CHAR: x CHAR: 0 } } substitute string>number ]
+ [ length ] bi <integer-literal> ;
+
+: ?lookup-word ( name vocab -- word )
+ 2dup lookup-word
+ [ 2nip ]
+ [ over [ "01x" member? ] all? [ drop make-integer-literal ] [ no-field-word ] if ] if* ;
+
+GENERIC: width ( obj -- n )
+M: word width "width" word-prop ;
+M: integer-literal width width>> ;
+
+GENERIC: value ( obj -- n )
+M: integer-literal value value>> ;
+M: object value ;
+
+: arm-bitfield ( seq -- assoc )
+ [ current-vocab name>> ?lookup-word ] map
+ [ dup width ] map>alist
+ dup values [ f = ] any? [ throw ] when ;
+
+ERROR: bad-instruction values ;
+
+SYNTAX: ARM-INSTRUCTION:
+ scan-new-word
+ scan-effect
+ [
+ in>> arm-bitfield
+ [ keys [ value ] map ]
+ [ values 32 [ - ] accumulate* ] bi zip
+ dup last second 0 = [ bad-instruction ] unless
+ '[ _ bitfield* 4 >le % ]
+ ] [ in>> [ string>number ] reject { } <effect> ] bi define-declared ;
+>>
+
+! ADC: Add with Carry.
+! ADCS: Add with Carry, setting flags.
+ARM-INSTRUCTION: ADC-encode ( bw 0 0 11010000 Rm 000000 Rn Rd -- )
+ARM-INSTRUCTION: ADCS-encode ( bw 0 1 11010000 Rm 000000 Rn Rd -- )
+
+! ADD (extended register): Add (extended register).
+ARM-INSTRUCTION: ADDer-encode ( bw 0 0 01011 00 1 Rm option3 imm3 Rn Rd -- )
+
+! ADD (immediate): Add (immediate).
+ARM-INSTRUCTION: ADDi-encode ( bw 0 0 10001 shift2 imm12 Rn Rd -- )
+
+! ADD (shifted register): Add (shifted register).
+ARM-INSTRUCTION: ADDsr-encode ( bw 0 0 01011 shift2 0 Rm imm6 Rn Rd -- )
+
+! ADDG: Add with Tag.
+ARM-INSTRUCTION: ADDG-encode ( 1 0 0 100011 0 uimm6 00 uimm4 Xn Xd -- )
+
+! ADDS (extended register): Add (extended register), setting flags.
+ARM-INSTRUCTION: ADDSer-encode ( bw 0 1 01011 00 1 Rm option3 imm3 Rn Rd -- )
+
+! ADDS (immediate): Add (immediate), setting flags.
+ARM-INSTRUCTION: ADDSi-encode ( bw 0 1 10001 shift2 imm12 Rn Rd -- )
+
+! ADDS (shifted register): Add (shifted register), setting flags.
+ARM-INSTRUCTION: ADDSsr-encode ( bw 0 1 01011 shift2 0 Rm imm6 Rn Rd -- )
+
+! ADDV: Add across Vector.
+ARM-INSTRUCTION: ADDV-encode ( 0 Q 0 01110 size2 11000 11011 10 Rn Rd -- )
+
+! ADR: Form PC-relative address.
+! ADRP: Form PC-relative address to 4KB page.
+ARM-INSTRUCTION: ADR-encode ( 0 immlo2 10000 immhi19 Rd -- )
+ARM-INSTRUCTION: ADRP-encode ( 1 immlo2 10000 immhi19 Rd -- )
+
+! AND (immediate): Bitwise AND (immediate).
+ARM-INSTRUCTION: ANDi-encode ( bw 00 100100 (N)immrimms Rn Rd -- )
+
+! AND (shifted register): Bitwise AND (shifted register).
+ARM-INSTRUCTION: ANDsr-encode ( bw 00 01010 shift2 0 Rm imm6 Rn Rd -- )
+
+! ANDS (immediate): Bitwise AND (immediate), setting flags.
+ARM-INSTRUCTION: ANDSi-encode ( bw 11 100100 (N)immrimms Rn Rd -- )
+
+! ANDS (shifted register): Bitwise AND (shifted register), setting flags.
+ARM-INSTRUCTION: ANDSsr-encode ( bw 11 01010 shift2 0 Rm imm6 Rn Rd -- )
+
+! ASR (immediate): Arithmetic Shift Right (immediate): an alias of SBFM.
+ARM-INSTRUCTION: ASRi-encode ( bw 00 100110 0 immr 011111 Rn Rd -- )
+
+! ASR (register): Arithmetic Shift Right (register): an alias of ASRV.
+ARM-INSTRUCTION: ASRr-encode ( bw 0 0 11010110 Rm 0010 10 Rn Rd -- )
+
+! ASRV: Arithmetic Shift Right Variable.
+ARM-INSTRUCTION: ASRV-encode ( bw 0 0 11010110 Rm 0010 10 Rn Rd -- )
+
+! AT: Address Translate: an alias of SYS.
+ARM-INSTRUCTION: AT-encode ( 1101010100 0 01 op3 0111 1000 op3 Rt -- )
+
+! AUTDA, AUTDZA: Authenticate Data address, using key A.
+! AUTDB, AUTDZB: Authenticate Data address, using key B.
+ARM-INSTRUCTION: AUTDA-encode ( 1 1 0 11010110 00001 0 0 0 110 Rn Rd -- )
+ARM-INSTRUCTION: AUTDZA-encode ( 1 1 0 11010110 00001 0 0 1 110 11111 Rd -- )
+ARM-INSTRUCTION: AUTDB-encode ( 1 1 0 11010110 00001 0 0 0 111 Rn Rd -- )
+ARM-INSTRUCTION: AUTDZB-encode ( 1 1 0 11010110 00001 0 0 1 111 11111 Rd -- )
+
+! AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZA: Authenticate Instruction address, using key A.
+! ARMv8.3
+ARM-INSTRUCTION: AUTIA-encode ( 1 1 0 11010110 00001 0 0 0 100 Rn Rd -- )
+ARM-INSTRUCTION: AUTIZA-encode ( 1 1 0 11010110 00001 0 0 1 100 11111 Rd -- )
+! ARMv8.3
+ARM-INSTRUCTION: AUTIA1716-encode ( 1101010100 0 00 011 0010 0001 100 11111 -- )
+ARM-INSTRUCTION: AUTIASP-encode ( 1101010100 0 00 011 0010 0011 101 11111 -- )
+ARM-INSTRUCTION: AUTIAAZ-encode ( 1101010100 0 00 011 0010 0011 100 11111 -- )
+
+! AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZB: Authenticate Instruction address, using key B.
+! ARMv8.3
+ARM-INSTRUCTION: AUTIB-encode ( 1 1 0 11010110 00001 0 0 0 101 Rn Rd -- )
+ARM-INSTRUCTION: AUTIZB-encode ( 1 1 0 11010110 00001 0 0 1 101 11111 Rd -- )
+! ARMv8.3
+ARM-INSTRUCTION: AUTIB1716-encode ( 1101010100 0 00 011 0010 0001 110 11111 -- )
+ARM-INSTRUCTION: AUTIBSP-encode ( 1101010100 0 00 011 0010 0011 111 11111 -- )
+ARM-INSTRUCTION: AUTIBZ-encode ( 1101010100 0 00 011 0010 0011 110 11111 -- )
+
+! AXFlag: Convert floating-point condition flags from ARM to external format.
+ARM-INSTRUCTION: AXFlag-encode ( 1101010100 0 00 000 0100 0000 010 11111 -- )
+
+! B: Branch.
+ARM-INSTRUCTION: B-encode ( 0 00101 imm26 -- )
+
+! B.cond: Branch conditionally.
+ARM-INSTRUCTION: B.cond-encode ( 0101010 0 imm19 0 cond4 -- )
+
+! BFC: Bitfield Clear: an alias of BFM.
+ARM-INSTRUCTION: BFC-encode ( bw 01 100110 (N)immrimms 11111 Rd -- )
+
+! BFI: Bitfield Insert: an alias of BFM.
+ARM-INSTRUCTION: BFI-encode ( bw 01 100110 (N)immrimms Rn Rd -- )
+
+! BFM: Bitfield Move.
+ARM-INSTRUCTION: BFM-encode ( bw 01 100110 (N)immrimms Rn Rd -- )
+
+! BFXIL: Bitfield extract and insert at low end: an alias of BFM.
+ARM-INSTRUCTION: BFXIL-encode ( bw 01 100110 (N)immrimms Rn Rd -- )
+
+! BIC (shifted register): Bitwise Bit Clear (shifted register).
+ARM-INSTRUCTION: BIC-encode ( bw 00 01010 shift2 1 Rm imm6 Rn Rd -- )
+! BICS (shifted register): Bitwise Bit Clear (shifted register), setting flags.
+ARM-INSTRUCTION: BICS-encode ( bw 11 01010 shift2 1 Rm imm6 Rn Rd -- )
+
+! BL: Branch with Link.
+ARM-INSTRUCTION: BL-encode ( 1 00101 imm26 -- )
+! BLR: Branch with Link to Register.
+ARM-INSTRUCTION: BLR-encode ( 1101011 0 0 01 11111 0000 0 0 Rn 00000 -- )
+
+! BLRAA, BLRAAZ, BLRAB, BLRABZ: Branch with Link to Register, with pointer authentication.
+ARM-INSTRUCTION: BLRAA-encode ( 1101011 0 0 01 11111 0000 1 0 Rn Rm -- )
+ARM-INSTRUCTION: BLRAAZ-encode ( 1101011 1 0 01 11111 0000 1 0 Rn 11111 -- )
+ARM-INSTRUCTION: BLRAB-encode ( 1101011 0 0 01 11111 0000 1 1 Rn Rm -- )
+ARM-INSTRUCTION: BLRABZ-encode ( 1101011 1 0 01 11111 0000 1 1 Rn 11111 -- )
+
+! BR: Branch to Register.
+ARM-INSTRUCTION: BR-encode ( 1101011 0 0 00 11111 0000 0 0 Rn 00000 -- )
+
+! BRAA, BRAAZ, BRAB, BRABZ: Branch to Register, with pointer authentication.
+ARM-INSTRUCTION: BRAA-encode ( 1101011 0 0 00 11111 0000 1 0 Rn 11111 -- )
+ARM-INSTRUCTION: BRAAZ-encode ( 1101011 1 0 00 11111 0000 1 0 Rn Rm -- )
+ARM-INSTRUCTION: BRAB-encode ( 1101011 0 0 00 11111 0000 1 1 Rn 11111 -- )
+ARM-INSTRUCTION: BRABZ-encode ( 1101011 1 0 00 11111 0000 1 1 Rn Rm -- )
+
+! BRK: Breakpoint instruction.
+ARM-INSTRUCTION: BRK-encode ( 11010100 001 imm16 000 00 -- )
+
+! BTI: Branch Target Identification.
+ARM-INSTRUCTION: BTI-encode ( 1101010100 0 00 011 0010 0100 000 11111 -- )
+
+! CAS, CASA, CASAL, CASL: Compare and Swap word or doubleword in memory.
+ARM-INSTRUCTION: CAS-encode ( 1 bw 001000 1 0 1 Rs 0 11111 Rn Rt -- )
+ARM-INSTRUCTION: CASA-encode ( 1 bw 001000 1 1 1 Rs 0 11111 Rn Rt -- )
+ARM-INSTRUCTION: CASAL-encode ( 1 bw 001000 1 1 1 Rs 1 11111 Rn Rt -- )
+ARM-INSTRUCTION: CASL-encode ( 1 bw 001000 1 0 1 Rs 1 11111 Rn Rt -- )
+
+! CASB, CASAB, CASALB, CASLB: Compare and Swap byte in memory.
+ARM-INSTRUCTION: CASAB-encode ( 00 001000 1 1 1 Rs 0 11111 Rn Rt -- )
+ARM-INSTRUCTION: CASALB-encode ( 00 001000 1 1 1 Rs 1 11111 Rn Rt -- )
+ARM-INSTRUCTION: CASB-encode ( 00 001000 1 0 1 Rs 0 11111 Rn Rt -- )
+ARM-INSTRUCTION: CASLB-encode ( 00 001000 1 0 1 Rs 1 11111 Rn Rt -- )
+
+! CASH, CASAH, CASALH, CASLH: Compare and Swap halfword in memory.
+ARM-INSTRUCTION: CASAH-encode ( 01 001000 1 1 1 Rs 0 11111 Rn Rt -- )
+ARM-INSTRUCTION: CASALH-encode ( 01 001000 1 1 1 Rs 1 11111 Rn Rt -- )
+ARM-INSTRUCTION: CASH-encode ( 01 001000 1 0 1 Rs 0 11111 Rn Rt -- )
+ARM-INSTRUCTION: CASLH-encode ( 01 001000 1 0 1 Rs 1 11111 Rn Rt -- )
+
+! CASP, CASPA, CASPAL, CASPL: Compare and Swap Pair of words or doublewords in memory.
+ARM-INSTRUCTION: CASP-encode ( 0 bw 001000 0 0 1 Rs 0 11111 Rn Rt -- )
+ARM-INSTRUCTION: CASPA-encode ( 0 bw 001000 0 1 1 Rs 0 11111 Rn Rt -- )
+ARM-INSTRUCTION: CASPAL-encode ( 0 bw 001000 0 1 1 Rs 1 11111 Rn Rt -- )
+ARM-INSTRUCTION: CASPL-encode ( 0 bw 001000 0 0 1 Rs 1 11111 Rn Rt -- )
+
+! CBNZ: Compare and Branch on Nonzero.
+ARM-INSTRUCTION: CBNZ-encode ( bw 011010 1 imm19 Rt -- )
+
+! CBZ: Compare and Branch on Zero.
+ARM-INSTRUCTION: CBZ-encode ( bw 011010 0 imm19 Rt -- )
+
+! CCMN (immediate): Conditional Compare Negative (immediate).
+ARM-INSTRUCTION: CCMNi-encode ( bw 0 1 11010010 imm5 cond4 1 0 Rn 0 nzcv -- )
+! CCMN (register): Conditional Compare Negative (register).
+ARM-INSTRUCTION: CCMNr-encode ( bw 0 1 11010010 Rm cond4 0 0 Rn 0 nzcv -- )
+! CCMP (immediate): Conditional Compare (immediate).
+ARM-INSTRUCTION: CCMPi-encode ( bw 1 1 11010010 imm5 cond4 1 0 Rn 0 nzcv -- )
+! CCMP (register): Conditional Compare (register).
+ARM-INSTRUCTION: CCMPr-encode ( bw 1 1 11010010 Rm cond4 0 0 Rn 0 nzcv -- )
+
+! CFINV: Invert Carry Flag.
+ARM-INSTRUCTION: CFINV-encode ( 1101010100 0 0 0 000 0100 0000 000 11111 -- )
+
+! CFP: Control Flow Prediction Restriction by Context: an alias of SYS.
+ARM-INSTRUCTION: CFP-encode ( 1101010100 0 01 011 0111 0011 100 Rt -- )
+
+! CINC: Conditional Increment: an alias of CSINC.
+ARM-INSTRUCTION: CINC-encode ( bw 0 0 11010100 Rm cond4 0 1 Rn Rd -- )
+
+! CINV: Conditional Invert: an alias of CSINV.
+ARM-INSTRUCTION: CINV-encode ( bw 0 0 11010100 Rm cond4 0 0 Rn Rd -- )
+
+! CLREX: Clear Exclusive.
+ARM-INSTRUCTION: CLREX-encode ( 1101010100 0 00 011 0011 CRm 010 11111 -- )
+
+! CLS: Count Leading Sign bits.
+ARM-INSTRUCTION: CLS-encode ( bw 1 0 11010110 00000 00010 1 Rn Rd -- )
+
+! CLZ: Count Leading Zeros.
+ARM-INSTRUCTION: CLZ-encode ( bw 1 0 11010110 00000 00010 0 Rn Rd -- )
+
+! CMN (extended register): Compare Negative (extended register): an alias of ADDS (extended register).
+ARM-INSTRUCTION: CMNer-encode ( bw 0 1 01011 00 1 Rm option3 imm3 Rn Rd -- )
+! CMN (immediate): Compare Negative (immediate): an alias of ADDS (immediate).
+ARM-INSTRUCTION: CMNi-encode ( bw 0 1 10001 shift2 imm12 Rn 11111 -- )
+! CMN (shifted register): Compare Negative (shifted register): an alias of ADDS (shifted register).
+ARM-INSTRUCTION: CMNsr-encode ( bw 0 1 01011 shift2 0 Rm imm6 Rn 11111 -- )
+
+! CMP (extended register): Compare (extended register): an alias of SUBS (extended register).
+ARM-INSTRUCTION: CMPer-encode ( bw 1 1 01011 00 1 Rm option3 imm3 Rn 11111 -- )
+! CMP (immediate): Compare (immediate): an alias of SUBS (immediate).
+ARM-INSTRUCTION: CMPi-encode ( bw 1 1 10001 shift2 imm12 Rn 11111 -- )
+! CMP (shifted register): Compare (shifted register): an alias of SUBS (shifted register).
+ARM-INSTRUCTION: CMPsr-encode ( bw 1 1 01011 shift2 0 Rm imm6 Rn Rd -- )
+
+! CMPP: Compare with Tag: an alias of SUBPS.
+ARM-INSTRUCTION: CMPP-encode ( 1 0 1 11010110 Xm 0 0 0 0 0 0 Xn Xd -- )
+
+! CNEG: Conditional Negate: an alias of CSNEG.
+ARM-INSTRUCTION: CNEG-encode ( bw 1 0 11010100 Rm cond4 0 1 Rn Rd -- )
+
+! CNT: Population Count per byte.
+ARM-INSTRUCTION: CNT-encode ( 0 Q 0 01110 size2 10000 00101 10 Rn Rd -- )
+
+! CPP: Cache Prefetch Prediction Restriction by Context: an alias of SYS.
+ARM-INSTRUCTION: CPP-encode ( 1101010100 0 01 011 0111 0011 111 Rt -- )
+
+! CRC32B, CRC32H, CRC32W, CRC32X: CRC32 checksum.
+ARM-INSTRUCTION: CRC32B-encode ( bw 0 0 11010110 Rm 010 0 00 Rn Rd -- )
+ARM-INSTRUCTION: CRC32H-encode ( bw 0 0 11010110 Rm 010 0 01 Rn Rd -- )
+ARM-INSTRUCTION: CRC32W-encode ( bw 0 0 11010110 Rm 010 0 10 Rn Rd -- )
+ARM-INSTRUCTION: CRC32X-encode ( bw 0 0 11010110 Rm 010 0 11 Rn Rd -- )
+
+! CRC32CB, CRC32CH, CRC32CW, CRC32CX: CRC32C checksum.
+ARM-INSTRUCTION: CRC32CB-encode ( bw 0 0 11010110 Rm 010 1 00 Rn Rd -- )
+ARM-INSTRUCTION: CRC32CH-encode ( bw 0 0 11010110 Rm 010 1 01 Rn Rd -- )
+ARM-INSTRUCTION: CRC32CW-encode ( bw 0 0 11010110 Rm 010 1 10 Rn Rd -- )
+ARM-INSTRUCTION: CRC32CX-encode ( bw 0 0 11010110 Rm 010 1 11 Rn Rd -- )
+
+! CSDB: Consumption of Speculative Data Barrier.
+ARM-INSTRUCTION: CSDB-encode ( 1101010100 0 00 011 0010 0010 100 11111 -- )
+! CSEL: Conditional Select.
+ARM-INSTRUCTION: CSEL-encode ( bw 0 0 11010100 Rm cond4 0 0 Rn Rd -- )
+! CSET: Conditional Set: an alias of CSINC.
+ARM-INSTRUCTION: CSET-encode ( bw 0 0 11010100 11111 cond4 0 1 11111 Rd -- )
+! CSETM: Conditional Set Mask: an alias of CSINV.
+ARM-INSTRUCTION: CSETM-encode ( bw 0 0 11010100 11111 cond4 0 0 11111 Rd -- )
+
+! CSINC: Conditional Select Increment.
+ARM-INSTRUCTION: CSINC-encode ( bw 0 0 11010100 Rm cond4 0 1 Rn Rd -- )
+
+! CSINV: Conditional Select Invert.
+ARM-INSTRUCTION: CSINV-encode ( bw 0 0 11010100 Rm cond4 0 0 Rn Rd -- )
+
+! CSNEG: Conditional Select Negation.
+ARM-INSTRUCTION: CSNEG-encode ( bw 1 0 11010100 Rm cond4 0 1 Rn Rd -- )
+
+! DC: Data Cache operation: an alias of SYS.
+ARM-INSTRUCTION: DC-encode ( 1101010100 0 01 op3 0111 CRm op3 Rt -- )
+
+! DCPS1: Debug Change PE State to EL1..
+ARM-INSTRUCTION: DCPS1-encode ( 11010100 101 imm16 000 01 -- )
+! DCPS2: Debug Change PE State to EL2..
+ARM-INSTRUCTION: DCPS2-encode ( 11010100 101 imm16 000 10 -- )
+! DCPS3: Debug Change PE State to EL3.
+ARM-INSTRUCTION: DCPS3-encode ( 11010100 101 imm16 000 11 -- )
+
+! DMB: Data Memory Barrier.
+ARM-INSTRUCTION: DMB-encode ( 1101010100 0 00 011 0011 CRm 1 01 11111 -- )
+
+! DRPS: Debug restore process state.
+ARM-INSTRUCTION: DPRS-encode ( 1101011 0101 11111 000000 11111 00000 -- )
+
+! DSB: Data Synchronization Barrier.
+ARM-INSTRUCTION: DSB-encode ( 1101010100 0 00 011 0011 CRm 1 00 11111 -- )
+
+! DUP (general): Duplicate general-purpose register to vector.
+ARM-INSTRUCTION: DUPgen-encode ( 0 Q 0 01110000 imm5 0 0001 1 Rn Rd -- )
+
+! DVP: Data Value Prediction Restriction by Context: an alias of SYS.
+ARM-INSTRUCTION: DVP-encode ( 1101010100 0 01 011 0111 0011 101 Rt -- )
+
+! EON (shifted register): Bitwise Exclusive OR NOT (shifted register).
+ARM-INSTRUCTION: EONsr-encode ( bw 10 01010 shift2 1 Rm imm6 Rn Rd -- )
+
+! EOR (immediate): Bitwise Exclusive OR (immediate).
+ARM-INSTRUCTION: EORi-encode ( bw 10 100100 (N)immrimms Rn Rd -- )
+
+! EOR (shifted register): Bitwise Exclusive OR (shifted register).
+ARM-INSTRUCTION: EORsr-encode ( bw 10 01010 shift2 0 Rm imm6 Rn Rd -- )
+
+! ERET: Exception Return.
+ARM-INSTRUCTION: ERET-encode ( 1101011 0 100 11111 0000 0 0 11111 00000 -- )
+
+! ERETAA, ERETAB: Exception Return, with pointer authentication.
+! ARMv8.3
+ARM-INSTRUCTION: ERETAA-encode ( 1101011 0 100 11111 0000 1 0 11111 00000 -- )
+ARM-INSTRUCTION: ERETAB-encode ( 1101011 0 100 11111 0000 1 1 11111 11111 -- )
+
+! ESB: Error Synchronization Barrier.
+! ARMv8.2
+ARM-INSTRUCTION: ESB-encode ( 1101010100 0 00 011 0010 0010 000 11111 -- )
+
+! EXTR: Extract register.
+ARM-INSTRUCTION: EXTR-encode ( bw 00 100111 0 0 Rm imms Rn Rd -- )
+
+! FADD (scalar): Floating-point Add (scalar).
+ARM-INSTRUCTION: FADDs-encode ( 0 0 0 11110 ftype 1 Rm 001 0 10 Rn Rd -- )
+
+! FCVT: Floating-point Convert percision (scalar).
+ARM-INSTRUCTION: FCVT-encode ( 0 0 0 11110 ftype 1 0001 opc2 10000 Rn Rd -- )
+
+! FCVTZS (scalar, integer): Floating-point Convert to Signed integer, rounding toward Zero (scalar).
+ARM-INSTRUCTION: FCVTZSsi-encode ( bw 0 0 11110 ftype 1 11 000 000000 Rn Rd -- )
+
+! FDIV (scalar): Floating-point Divide (scalar).
+ARM-INSTRUCTION: FDIVs-encode ( 0 0 0 11110 ftype 1 Rm 0001 10 Rn Rd -- )
+
+! FMAX (scalar): Floating-point Maximum (scalar).
+ARM-INSTRUCTION: FMAXs-encode ( 0 0 0 11110 ftype 1 Rm 01 00 10 Rn Rd -- )
+
+! FMIN (scalar): Floating-point Minimum (scalar).
+ARM-INSTRUCTION: FMINs-encode ( 0 0 0 11110 ftype 1 Rm 01 01 10 Rn Rd -- )
+
+! FMOV (general): Floating-point Move to or from general-purpose register without conversion.
+ARM-INSTRUCTION: FMOVgen-encode ( sf 0 0 11110 ftype 1 rmode opc3 000000 Rn Rd -- )
+
+! FMUL (scalar): Floating-point Multiply (scalar).
+ARM-INSTRUCTION: FMULs-encode ( 0 0 0 11110 ftype 1 Rm 0 000 10 Rn Rd -- )
+
+! FSQRT (scalar): Floating-point Square Root (scalar).
+ARM-INSTRUCTION: FSQRTs-encode ( 0 0 0 11110 ftype 1 0000 11 10000 Rn Rd -- )
+
+! FSUB (scalar): Floating-point Subtract (scalar).
+ARM-INSTRUCTION: FSUBs-encode ( 0 0 0 11110 ftype 1 Rm 001 1 10 Rn Rd -- )
+
+! GMI: Tag Mask Insert.
+ARM-INSTRUCTION: GMI-encode ( 1 0 0 11010110 Xm 0 0 0 1 0 1 Xn Xd -- )
+
+! HINT: Hint instruction.
+ARM-INSTRUCTION: HINT-encode ( 1101010100 0 00 011 0010 CRm op3 11111 -- )
+
+! HLT: Halt instruction.
+ARM-INSTRUCTION: HLT-encode ( 11010100 010 imm16 000 00 -- )
+
+! HVC: Hypervisor Call.
+ARM-INSTRUCTION: HVC-encode ( 11010100 000 imm16 000 10 -- )
+
+! IC: Instruction Cache operation: an alias of SYS.
+ARM-INSTRUCTION: IC-encode ( 1101010100 0 01 op3 0111 CRm op3 Rt -- )
+
+! IRG: Insert Random Tag.
+ARM-INSTRUCTION: IRG-encode ( 1 0 0 11010110 Xm 0 0 0 1 0 0 Xn Xd -- )
+
+! ISB: Instruction Synchronization Barrier.
+ARM-INSTRUCTION: ISB-encode ( 1101010100 0 00 011 0011 CRm 1 10 11111 -- )
+
+! LDADD, LDADDA, LDADDAL, LDADDL: Atomic add on word or doubleword in memory.
+ARM-INSTRUCTION: LDADD-encode ( 1 bw 111 0 00 0 0 1 Rs 0 000 00 Rn Rt -- )
+ARM-INSTRUCTION: LDADDA-encode ( 1 bw 111 0 00 1 0 1 Rs 0 000 00 Rn Rt -- )
+ARM-INSTRUCTION: LDADDAL-encode ( 1 bw 111 0 00 1 1 1 Rs 0 000 00 Rn Rt -- )
+ARM-INSTRUCTION: LDADDL-encode ( 1 bw 111 0 00 0 1 1 Rs 0 000 00 Rn Rt -- )
+
+! LDADDB, LDADDAB, LDADDALB, LDADDLB: Atomic add on byte in memory.
+ARM-INSTRUCTION: LDADDAB-encode ( 00 111 0 00 1 0 1 Rs 0 000 00 Rn Rt -- )
+ARM-INSTRUCTION: LDADDALB-encode ( 00 111 0 00 1 1 1 Rs 0 000 00 Rn Rt -- )
+ARM-INSTRUCTION: LDADDB-encode ( 00 111 0 00 0 0 1 Rs 0 000 00 Rn Rt -- )
+ARM-INSTRUCTION: LDADDLB-encode ( 00 111 0 00 0 1 1 Rs 0 000 00 Rn Rt -- )
+
+! LDADDH, LDADDAH, LDADDALH, LDADDLH: Atomic add on halfword in memory.
+ARM-INSTRUCTION: LDADDAH-encode ( 01 111 0 00 1 0 1 Rs 0 000 00 Rn Rt -- )
+ARM-INSTRUCTION: LDADDALH-encode ( 01 111 0 00 1 1 1 Rs 0 000 00 Rn Rt -- )
+ARM-INSTRUCTION: LDADDH-encode ( 01 111 0 00 0 0 1 Rs 0 000 00 Rn Rt -- )
+ARM-INSTRUCTION: LDADDLH-encode ( 01 111 0 00 0 1 1 Rs 0 000 00 Rn Rt -- )
+
+! LDAPR: Load-Acquire RCpc Register.
+! ARMv8.3
+ARM-INSTRUCTION: LDAPR-encode ( 1 bw 111 0 00 1 0 1 11111 1 100 00 Rn Rt -- )
+! LDAPRB: Load-Acquire RCpc Register Byte.
+ARM-INSTRUCTION: LDAPRB-encode ( 00 111 0 00 1 0 1 11111 1 100 00 Rn Rt -- )
+! LDAPRH: Load-Acquire RCpc Register Halfword.
+ARM-INSTRUCTION: LDAPRH-encode ( 01 111 0 00 1 0 1 11111 1 100 00 Rn Rt -- )
+
+! LDAPUR: Load-Acquire RCpc Register (unscaled).
+ARM-INSTRUCTION: LDAPUR-encode ( 1 bw 011001 01 0 imm9 00 Rn Rt -- )
+! LDAPURB: Load-Acquire RCpc Register Byte (unscaled).
+ARM-INSTRUCTION: LDAPURB-encode ( 00 011001 01 0 imm9 00 Rn Rt -- )
+! LDAPURH: Load-Acquire RCpc Register Halfword (unscaled).
+ARM-INSTRUCTION: LDAPURH-encode ( 01 011001 01 0 imm9 00 Rn Rt -- )
+! LDAPURSB: Load-Acquire RCpc Register Signed Byte (unscaled).
+ARM-INSTRUCTION: LDAPURSB-encode ( 00 011001 1 !bw 0 imm9 00 Rn Rt -- )
+! LDAPURSH: Load-Acquire RCpc Register Signed Halfword (unscaled).
+ARM-INSTRUCTION: LDAPURSH-encode ( 01 011001 1 !bw 0 imm9 00 Rn Rt -- )
+! LDAPURSW: Load-Acquire RCpc Register Signed Word (unscaled).
+ARM-INSTRUCTION: LDAPURSW-encode ( 10 011001 10 0 imm9 00 Rn Rt -- )
+! LDAR: Load-Acquire Register.
+ARM-INSTRUCTION: LDAR-encode ( 1 bw 001000 1 1 0 11111 1 11111 Rn Rt -- )
+! LDARB: Load-Acquire Register Byte.
+ARM-INSTRUCTION: LDARB-encode ( 00 001000 1 1 0 11111 1 11111 Rn Rt -- )
+! LDARH: Load-Acquire Register Halfword.
+ARM-INSTRUCTION: LDARH-encode ( 01 001000 1 1 0 11111 1 11111 Rn Rt -- )
+! LDAXP: Load-Acquire Exclusive Pair of Registers.
+ARM-INSTRUCTION: LDAXP-encode ( 1 bw 001000 0 1 1 11111 1 Rt2 Rn Rt -- )
+! LDAXR: Load-Acquire Exclusive Register.
+ARM-INSTRUCTION: LDAXR-encode ( 1 bw 001000 0 1 0 11111 1 11111 Rn Rt -- )
+! LDAXRB: Load-Acquire Exclusive Register Byte.
+ARM-INSTRUCTION: LDAXRB-encode ( 00 001000 0 1 0 11111 1 11111 Rn Rt -- )
+! LDAXRH: Load-Acquire Exclusive Register Halfword.
+ARM-INSTRUCTION: LDAXRH-encode ( 01 001000 0 1 0 11111 1 11111 Rn Rt -- )
+
+! LDCLR, LDCLRA, LDCLRAL, LDCLRL: Atomic bit clear on word or doubleword in memory.
+ARM-INSTRUCTION: LDCLR-encode ( 1 bw 111 0 00 0 0 1 Rs 0 001 00 Rn Rt -- )
+ARM-INSTRUCTION: LDCLRA-encode ( 1 bw 111 0 00 1 0 1 Rs 0 001 00 Rn Rt -- )
+ARM-INSTRUCTION: LDCLRAL-encode ( 1 bw 111 0 00 1 1 1 Rs 0 001 00 Rn Rt -- )
+ARM-INSTRUCTION: LDCLRL-encode ( 1 bw 111 0 00 0 1 1 Rs 0 001 00 Rn Rt -- )
+
+! LDCLRB, LDCLRAB, LDCLRALB, LDCLRLB: Atomic bit clear on byte in memory.
+ARM-INSTRUCTION: LDCLRAB-encode ( 00 111 0 00 1 0 1 Rs 0 001 00 Rn Rt -- )
+ARM-INSTRUCTION: LDCLRALB-encode ( 00 111 0 00 1 1 1 Rs 0 001 00 Rn Rt -- )
+ARM-INSTRUCTION: LDCLRB-encode ( 00 111 0 00 0 0 1 Rs 0 001 00 Rn Rt -- )
+ARM-INSTRUCTION: LDCLRLB-encode ( 00 111 0 00 0 1 1 Rs 0 001 00 Rn Rt -- )
+
+! LDCLRH, LDCLRAH, LDCLRALH, LDCLRLH: Atomic bit clear on halfword in memory.
+ARM-INSTRUCTION: LDCLRAH-encode ( 01 111 0 00 1 0 1 Rs 0 001 00 Rn Rt -- )
+ARM-INSTRUCTION: LDCLRALH-encode ( 01 111 0 00 1 1 1 Rs 0 001 00 Rn Rt -- )
+ARM-INSTRUCTION: LDCLRH-encode ( 01 111 0 00 0 0 1 Rs 0 001 00 Rn Rt -- )
+ARM-INSTRUCTION: LDCLRLH-encode ( 01 111 0 00 0 1 1 Rs 0 001 00 Rn Rt -- )
+
+! LDEOR, LDEORA, LDEORAL, LDEORL: Atomic exclusive OR on word or doubleword in memory.
+ARM-INSTRUCTION: LDEOR-encode ( 1 bw 111 0 00 0 0 1 Rs 0 010 00 Rn Rt -- )
+ARM-INSTRUCTION: LDEORA-encode ( 1 bw 111 0 00 1 0 1 Rs 0 010 00 Rn Rt -- )
+ARM-INSTRUCTION: LDEORAL-encode ( 1 bw 111 0 00 1 1 1 Rs 0 010 00 Rn Rt -- )
+ARM-INSTRUCTION: LDEORL-encode ( 1 bw 111 0 00 0 1 1 Rs 0 010 00 Rn Rt -- )
+
+! LDEORB, LDEORAB, LDEORALB, LDEORLB: Atomic exclusive OR on byte in memory.
+ARM-INSTRUCTION: LDEORAB-encode ( 00 111 0 00 1 0 1 Rs 0 010 00 Rn Rt -- )
+ARM-INSTRUCTION: LDEORALB-encode ( 00 111 0 00 1 1 1 Rs 0 010 00 Rn Rt -- )
+ARM-INSTRUCTION: LDEORB-encode ( 00 111 0 00 0 0 1 Rs 0 010 00 Rn Rt -- )
+ARM-INSTRUCTION: LDEORLB-encode ( 00 111 0 00 0 1 1 Rs 0 010 00 Rn Rt -- )
+
+! LDEORH, LDEORAH, LDEORALH, LDEORLH: Atomic exclusive OR on halfword in memory.
+! ARMv8.1
+ARM-INSTRUCTION: LDEORAH-encode ( 01 111 0 00 1 0 1 Rs 0 010 00 Rn Rt -- )
+ARM-INSTRUCTION: LDEORALH-encode ( 01 111 0 00 1 1 1 Rs 0 010 00 Rn Rt -- )
+ARM-INSTRUCTION: LDEORH-encode ( 01 111 0 00 0 0 1 Rs 0 010 00 Rn Rt -- )
+ARM-INSTRUCTION: LDEORLH-encode ( 01 111 0 00 0 1 1 Rs 0 010 00 Rn Rt -- )
+
+! LDG: Load Allocation Tag.
+! ARMv8.5
+ARM-INSTRUCTION: LDG-encode ( 11011001 0 1 1 imm9 0 0 Xn Xt -- )
+! LDGV: Load Tag Multiple.
+! ARMv8.5
+ARM-INSTRUCTION: LDGM-encode ( 11011001 1 1 1 0 0 0 0 0 0 0 0 0 0 0 Xn Xt -- )
+
+! LDLAR: Load LOAcquire Register.
+! ARMv8.1
+ARM-INSTRUCTION: LDLAR-encode ( 1 bw 001000 1 1 0 11111 0 11111 Rn Rt -- )
+! LDLARB: Load LOAcquire Register Byte.
+ARM-INSTRUCTION: LDLARB-encode ( 00 001000 1 1 0 11111 0 11111 Rn Rt -- )
+! LDLARH: Load LOAcquire Register Halfword.
+ARM-INSTRUCTION: LDLARH-encode ( 01 001000 1 1 0 11111 0 11111 Rn Rt -- )
+
+! LDNP: Load Pair of Registers, with non-temporal hint.
+ARM-INSTRUCTION: LDNP-encode ( bw 0 101 0 000 1 imm7 Rt2 Rn Rt -- )
+
+! LDP: Load Pair of Registers.
+ARM-INSTRUCTION: LDPpost-encode ( bw 0 101 0 001 1 imm7 Rt2 Rn Rt -- )
+ARM-INSTRUCTION: LDPpre-encode ( bw 0 101 0 011 1 imm7 Rt2 Rn Rt -- )
+ARM-INSTRUCTION: LDPsoff-encode ( bw 0 101 0 010 1 imm7 Rt2 Rn Rt -- )
+
+! LDPSW: Load Pair of Registers Signed Word.
+ARM-INSTRUCTION: LDPSWpost-encode ( 01 101 0 001 1 imm7 Rt2 Rn Rt -- )
+ARM-INSTRUCTION: LDPSWpre-encode ( 01 101 0 011 1 imm7 Rt2 Rn Rt -- )
+ARM-INSTRUCTION: LDPSWsoff-encode ( 01 101 0 010 1 imm7 Rt2 Rn Rt -- )
+
+! LDR (immediate): Load Register (immediate).
+ARM-INSTRUCTION: LDRpost-encode ( 1 bw 111 0 00 01 0 imm9 01 Rn Rt -- )
+ARM-INSTRUCTION: LDRpre-encode ( 1 bw 111 0 00 01 0 imm9 11 Rn Rt -- )
+ARM-INSTRUCTION: LDRuoff-encode ( 1 bw 111 0 01 01 imm12 Rn Rt -- )
+
+! LDR (literal): Load Register (literal).
+ARM-INSTRUCTION: LDRl-encode ( 1 bw 011 0 00 imm19 Rt -- )
+
+! LDR (register): Load Register (register).
+ARM-INSTRUCTION: LDRr-encode ( 1 bw 111 0 00 01 1 Rm option3 S 1 0 Rn Rt -- )
+
+! LDRAA, LDRAB: Load Register, with pointer authentication.
+! ARMv8.3
+ARM-INSTRUCTION: LDRAAoff-encode ( 11 111 0 00 0 S 1 imm9 0 1 Rn Rt -- )
+ARM-INSTRUCTION: LDRAApre-encode ( 11 111 0 00 0 S 1 imm9 1 1 Rn Rt -- )
+ARM-INSTRUCTION: LDRABoff-encode ( 11 111 0 00 1 S 1 imm9 0 1 Rn Rt -- )
+ARM-INSTRUCTION: LDRABpre-encode ( 11 111 0 00 1 S 1 imm9 1 1 Rn Rt -- )
+
+! LDRB (immediate): Load Register Byte (immediate).
+ARM-INSTRUCTION: LDRBpost-encode ( 00 111 0 00 01 0 imm9 01 Rn Rt -- )
+ARM-INSTRUCTION: LDRBpre-encode ( 00 111 0 00 01 0 imm9 11 Rn Rt -- )
+ARM-INSTRUCTION: LDRBuoff-encode ( 00 111 0 01 01 imm12 Rn Rt -- )
+
+! LDRB (register): Load Register Byte (register).
+! option: 010: UXTW, 110 SXTW, 111 SXTX, S shift 0/1
+ARM-INSTRUCTION: LDRBer-encode ( 00 111 0 00 01 1 Rm option3 S 10 Rn Rt -- )
+ARM-INSTRUCTION: LDRBsr-encode ( 00 111 0 00 01 1 Rm 011 S 10 Rn Rt -- )
+
+! LDRH (immediate): Load Register Halfword (immediate).
+ARM-INSTRUCTION: LDRHpost-encode ( 01 111 0 00 01 0 imm9 01 Rn Rt -- )
+ARM-INSTRUCTION: LDRHpre-encode ( 01 111 0 00 01 0 imm9 11 Rn Rt -- )
+ARM-INSTRUCTION: LDRHuoff-encode ( 01 111 0 01 01 imm12 Rn Rt -- )
+
+! LDRH (register): Load Register Halfword (register).
+ARM-INSTRUCTION: LDRHr-encode ( 01 111 0 00 01 1 Rm option3 S 10 Rn Rt -- )
+
+! LDRSB (immediate): Load Register Signed Byte (immediate).
+ARM-INSTRUCTION: LDRSBpost-encode ( 00 111 0 00 1 !bw 0 imm9 01 Rn Rt -- )
+ARM-INSTRUCTION: LDRSBpre-encode ( 00 111 0 00 1 !bw 0 imm9 11 Rn Rt -- )
+ARM-INSTRUCTION: LDRSBuoff-encode ( 00 111 0 01 1 !bw imm12 Rn Rt -- )
+
+! LDRSB (register): Load Register Signed Byte (register).
+ARM-INSTRUCTION: LDRSBer-encode ( 00 111 0 00 1 !bw 1 Rm option3 S 10 Rn Rt -- )
+ARM-INSTRUCTION: LDRSBsr-encode ( 00 111 0 00 1 !bw 1 Rm 011 S 10 Rn Rt -- )
+
+! LDRSH (immediate): Load Register Signed Halfword (immediate).
+ARM-INSTRUCTION: LDRSHpost-encode ( 01 111 0 00 1 !bw 0 imm9 01 Rn Rt -- )
+ARM-INSTRUCTION: LDRSHpre-encode ( 01 111 0 00 1 !bw 0 imm9 11 Rn Rt -- )
+ARM-INSTRUCTION: LDRSHuoff-encode ( 01 111 0 01 1 !bw imm12 Rn Rt -- )
+
+! LDRSH (register): Load Register Signed Halfword (register).
+ARM-INSTRUCTION: LDRSHr-encode ( 01 111 0 00 1 !bw 1 Rm option3 S 10 Rn Rt -- )
+
+! LDRSW (immediate): Load Register Signed Word (immediate).
+ARM-INSTRUCTION: LDRSWpost-encode ( 10 111 0 00 10 0 imm9 01 Rn Rt -- )
+ARM-INSTRUCTION: LDRSWpre-encode ( 10 111 0 00 10 0 imm9 11 Rn Rt -- )
+ARM-INSTRUCTION: LDRSWuoff-encode ( 10 111 0 01 10 imm12 Rn Rt -- )
+
+! LDRSW (literal): Load Register Signed Word (literal).
+ARM-INSTRUCTION: LDRSWl-encode ( 10 011 0 00 imm19 Rt -- )
+
+! LDRSW (register): Load Register Signed Word (register).
+ARM-INSTRUCTION: LDRSWr-encode ( 10 111 0 00 10 1 Rm option3 S 10 Rn Rt -- )
+
+! LDSET, LDSETA, LDSETAL, LDSETL: Atomic bit set on word or doubleword in memory.
+ARM-INSTRUCTION: LDSET-encode ( 1 bw 111 0 00 0 0 1 Rs 0 011 00 Rn Rt -- )
+ARM-INSTRUCTION: LDSETA-encode ( 1 bw 111 0 00 1 0 1 Rs 0 011 00 Rn Rt -- )
+ARM-INSTRUCTION: LDSETAL-encode ( 1 bw 111 0 00 1 1 1 Rs 0 011 00 Rn Rt -- )
+ARM-INSTRUCTION: LDSETL-encode ( 1 bw 111 0 00 0 1 1 Rs 0 011 00 Rn Rt -- )
+
+! LDSETB, LDSETAB, LDSETALB, LDSETLB: Atomic bit set on byte in memory.
+ARM-INSTRUCTION: LDSETAB-encode ( 00 111 0 00 1 0 1 Rs 0 011 00 Rn Rt -- )
+ARM-INSTRUCTION: LDSETALB-encode ( 00 111 0 00 1 1 1 Rs 0 011 00 Rn Rt -- )
+ARM-INSTRUCTION: LDSETB-encode ( 00 111 0 00 0 0 1 Rs 0 011 00 Rn Rt -- )
+ARM-INSTRUCTION: LDSETLB-encode ( 00 111 0 00 0 1 1 Rs 0 011 00 Rn Rt -- )
+
+! LDSETH, LDSETAH, LDSETALH, LDSETLH: Atomic bit set on halfword in memory.
+ARM-INSTRUCTION: LDSETAH-encode ( 01 111 0 00 1 0 1 Rs 0 011 00 Rn Rt -- )
+ARM-INSTRUCTION: LDSETALH-encode ( 01 111 0 00 1 1 1 Rs 0 011 00 Rn Rt -- )
+ARM-INSTRUCTION: LDSETH-encode ( 01 111 0 00 0 0 1 Rs 0 011 00 Rn Rt -- )
+ARM-INSTRUCTION: LDSETLH-encode ( 01 111 0 00 0 1 1 Rs 0 011 00 Rn Rt -- )
+
+! LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL: Atomic signed maximum on word or doubleword in memory.
+ARM-INSTRUCTION: LDSMAX-encode ( 1 bw 111 0 00 0 0 1 Rs 0 100 00 Rn Rt -- )
+ARM-INSTRUCTION: LDSMAXA-encode ( 1 bw 111 0 00 1 0 1 Rs 0 100 00 Rn Rt -- )
+ARM-INSTRUCTION: LDSMAXAL-encode ( 1 bw 111 0 00 1 1 1 Rs 0 100 00 Rn Rt -- )
+ARM-INSTRUCTION: LDSMAXL-encode ( 1 bw 111 0 00 0 1 1 Rs 0 100 00 Rn Rt -- )
+
+! LDSMAXB, LDSMAXAB, LDSMAXALB, LDSMAXLB: Atomic signed maximum on byte in memory.
+ARM-INSTRUCTION: LDSMAXAB-encode ( 00 111 0 00 1 0 1 Rs 0 100 00 Rn Rt -- )
+ARM-INSTRUCTION: LDSMAXALB-encode ( 00 111 0 00 1 1 1 Rs 0 100 00 Rn Rt -- )
+ARM-INSTRUCTION: LDSMAXB-encode ( 00 111 0 00 0 0 1 Rs 0 100 00 Rn Rt -- )
+ARM-INSTRUCTION: LDSMAXLB-encode ( 00 111 0 00 0 1 1 Rs 0 100 00 Rn Rt -- )
+
+! LDSMAXH, LDSMAXAH, LDSMAXALH, LDSMAXLH: Atomic signed maximum on halfword in memory.
+ARM-INSTRUCTION: LDSMAXAH-encode ( 00 111 0 00 1 0 1 Rs 0 100 00 Rn Rt -- )
+ARM-INSTRUCTION: LDSMAXALH-encode ( 00 111 0 00 1 1 1 Rs 0 100 00 Rn Rt -- )
+ARM-INSTRUCTION: LDSMAXH-encode ( 00 111 0 00 0 0 1 Rs 0 100 00 Rn Rt -- )
+ARM-INSTRUCTION: LDSMAXLH-encode ( 00 111 0 00 0 1 1 Rs 0 100 00 Rn Rt -- )
+
+! LDSMIN, LDSMINA, LDSMINAL, LDSMINL: Atomic signed minimum on word or doubleword in memory.
+ARM-INSTRUCTION: LDSMIN-encode ( 1 bw 111 0 00 0 0 1 Rs 0 101 00 Rn Rt -- )
+ARM-INSTRUCTION: LDSMINA-encode ( 1 bw 111 0 00 1 0 1 Rs 0 101 00 Rn Rt -- )
+ARM-INSTRUCTION: LDSMINAL-encode ( 1 bw 111 0 00 1 1 1 Rs 0 101 00 Rn Rt -- )
+ARM-INSTRUCTION: LDSMINL-encode ( 1 bw 111 0 00 0 1 1 Rs 0 101 00 Rn Rt -- )
+
+! LDSMINB, LDSMINAB, LDSMINALB, LDSMINLB: Atomic signed minimum on byte in memory.
+! ARMv8.1
+ARM-INSTRUCTION: LDSMINAB-encode ( 00 111 0 00 1 0 1 Rs 0 101 00 Rn Rt -- )
+ARM-INSTRUCTION: LDSMINALB-encode ( 00 111 0 00 1 1 1 Rs 0 101 00 Rn Rt -- )
+ARM-INSTRUCTION: LDSMINB-encode ( 00 111 0 00 0 0 1 Rs 0 101 00 Rn Rt -- )
+ARM-INSTRUCTION: LDSMINLB-encode ( 00 111 0 00 0 1 1 Rs 0 101 00 Rn Rt -- )
+
+! LDSMINH, LDSMINAH, LDSMINALH, LDSMINLH: Atomic signed minimum on halfword in memory.
+! ARMv8.1
+ARM-INSTRUCTION: LDSMINAH-encode ( 01 111 0 00 1 0 1 Rs 0 101 00 Rn Rt -- )
+ARM-INSTRUCTION: LDSMINALH-encode ( 01 111 0 00 1 1 1 Rs 0 101 00 Rn Rt -- )
+ARM-INSTRUCTION: LDSMINH-encode ( 01 111 0 00 0 0 1 Rs 0 101 00 Rn Rt -- )
+ARM-INSTRUCTION: LDSMINLH-encode ( 01 111 0 00 0 1 1 Rs 0 101 00 Rn Rt -- )
+
+! LDTR: Load Register (unprivileged).
+ARM-INSTRUCTION: LDTR-encode ( 1 bw 111 0 00 01 0 imm9 10 Rn Rt -- )
+
+! LDTRB: Load Register Byte (unprivileged).
+ARM-INSTRUCTION: LDTRB-encode ( 00 111 0 00 01 0 imm9 10 Rn Rt -- )
+
+! LDTRH: Load Register Halfword (unprivileged).
+ARM-INSTRUCTION: LDTRH-encode ( 01 111 0 00 01 0 imm9 10 Rn Rt -- )
+
+! LDTRSB: Load Register Signed Byte (unprivileged).
+ARM-INSTRUCTION: LDTRSB-encode ( 00 111 0 00 1 !bw 0 imm9 10 Rn Rt -- )
+
+! LDTRSH: Load Register Signed Halfword (unprivileged).
+ARM-INSTRUCTION: LDTRSH-encode ( 01 111 0 00 1 !bw 0 imm9 10 Rn Rt -- )
+
+! LDTRSW: Load Register Signed Word (unprivileged).
+ARM-INSTRUCTION: LDTRSW-encode ( 10 111 0 00 10 0 imm9 10 Rn Rt -- )
+
+! LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL: Atomic unsigned maximum on word or doubleword in memory.
+! ARMv8.1
+ARM-INSTRUCTION: LDUMAX-encode ( 1 bw 111 0 00 0 0 1 Rs 0 110 00 Rn Rt -- )
+ARM-INSTRUCTION: LDUMAXA-encode ( 1 bw 111 0 00 1 0 1 Rs 0 110 00 Rn Rt -- )
+ARM-INSTRUCTION: LDUMAXAL-encode ( 1 bw 111 0 00 1 1 1 Rs 0 110 00 Rn Rt -- )
+ARM-INSTRUCTION: LDUMAXL-encode ( 1 bw 111 0 00 0 1 1 Rs 0 110 00 Rn Rt -- )
+
+! LDUMAXB, LDUMAXAB, LDUMAXALB, LDUMAXLB: Atomic unsigned maximum on byte in memory.
+! ARMv8.1
+ARM-INSTRUCTION: LDUMAXAB-encode ( 00 111 0 00 1 0 1 Rs 0 110 00 Rn Rt -- )
+ARM-INSTRUCTION: LDUMAXALB-encode ( 00 111 0 00 1 1 1 Rs 0 110 00 Rn Rt -- )
+ARM-INSTRUCTION: LDUMAXB-encode ( 00 111 0 00 0 0 1 Rs 0 110 00 Rn Rt -- )
+ARM-INSTRUCTION: LDUMAXLB-encode ( 00 111 0 00 0 1 1 Rs 0 110 00 Rn Rt -- )
+
+! LDUMAXH, LDUMAXAH, LDUMAXALH, LDUMAXLH: Atomic unsigned maximum on halfword in memory.
+! ARMv8.1
+ARM-INSTRUCTION: LDUMAXAH-encode ( 01 111 0 00 1 0 1 Rs 0 110 00 Rn Rt -- )
+ARM-INSTRUCTION: LDUMAXALH-encode ( 01 111 0 00 1 1 1 Rs 0 110 00 Rn Rt -- )
+ARM-INSTRUCTION: LDUMAXH-encode ( 01 111 0 00 0 0 1 Rs 0 110 00 Rn Rt -- )
+ARM-INSTRUCTION: LDUMAXLH-encode ( 01 111 0 00 0 1 1 Rs 0 110 00 Rn Rt -- )
+
+! LDUMIN, LDUMINA, LDUMINAL, LDUMINL: Atomic unsigned minimum on word or doubleword in memory.
+! ARMv8.1
+ARM-INSTRUCTION: LDUMIN-encode ( 1 bw 111 0 00 0 0 1 Rs 0 111 00 Rn Rt -- )
+ARM-INSTRUCTION: LDUMINA-encode ( 1 bw 111 0 00 1 0 1 Rs 0 111 00 Rn Rt -- )
+ARM-INSTRUCTION: LDUMINAL-encode ( 1 bw 111 0 00 1 1 1 Rs 0 111 00 Rn Rt -- )
+ARM-INSTRUCTION: LDUMINL-encode ( 1 bw 111 0 00 0 1 1 Rs 0 111 00 Rn Rt -- )
+
+! LDUMINB, LDUMINAB, LDUMINALB, LDUMINLB: Atomic unsigned minimum on byte in memory.
+! ARMv8.1
+ARM-INSTRUCTION: LDUMINAB-encode ( 00 111 0 00 1 0 1 Rs 0 111 00 Rn Rt -- )
+ARM-INSTRUCTION: LDUMINALB-encode ( 00 111 0 00 1 1 1 Rs 0 111 00 Rn Rt -- )
+ARM-INSTRUCTION: LDUMINB-encode ( 00 111 0 00 0 0 1 Rs 0 111 00 Rn Rt -- )
+ARM-INSTRUCTION: LDUMINLB-encode ( 00 111 0 00 0 1 1 Rs 0 111 00 Rn Rt -- )
+
+! LDUMINH, LDUMINAH, LDUMINALH, LDUMINLH: Atomic unsigned minimum on halfword in memory.
+! ARMv8.1
+ARM-INSTRUCTION: LDUMINAH-encode ( 01 111 0 00 1 0 1 Rs 0 111 00 Rn Rt -- )
+ARM-INSTRUCTION: LDUMINALH-encode ( 01 111 0 00 1 1 1 Rs 0 111 00 Rn Rt -- )
+ARM-INSTRUCTION: LDUMINH-encode ( 01 111 0 00 0 0 1 Rs 0 111 00 Rn Rt -- )
+ARM-INSTRUCTION: LDUMINLH-encode ( 01 111 0 00 0 1 1 Rs 0 111 00 Rn Rt -- )
+
+! LDUR: Load Register (unscaled).
+ARM-INSTRUCTION: LDUR-encode ( 1 bw 111 0 00 01 0 imm9 00 Rn Rt -- )
+
+! LDURB: Load Register Byte (unscaled).
+ARM-INSTRUCTION: LDURB-encode ( 00 111 0 00 01 0 imm9 00 Rn Rt -- )
+
+! LDURH: Load Register Halfword (unscaled).
+ARM-INSTRUCTION: LDURH-encode ( 01 111 0 00 01 0 imm9 00 Rn Rt -- )
+
+! LDURSB: Load Register Signed Byte (unscaled).
+ARM-INSTRUCTION: LDURSB-encode ( 00 111 0 00 1 !bw 0 imm9 00 Rn Rt -- )
+
+! LDURSH: Load Register Signed Halfword (unscaled).
+ARM-INSTRUCTION: LDURSH-encode ( 01 111 0 00 1 !bw 0 imm9 00 Rn Rt -- )
+
+! LDURSW: Load Register Signed Word (unscaled).
+ARM-INSTRUCTION: LDURSW-encode ( 10 111 0 00 10 0 imm9 00 Rn Rt -- )
+
+! LDXP: Load Exclusive Pair of Registers.
+ARM-INSTRUCTION: LDXP-encode ( 1 bw 001000 0 1 1 11111 0 Rt2 Rn Rt -- )
+
+! LDXR: Load Exclusive Register.
+ARM-INSTRUCTION: LDXR-encode ( 1 bw 001000 0 1 0 11111 0 11111 Rn Rt -- )
+
+! LDXRB: Load Exclusive Register Byte.
+ARM-INSTRUCTION: LDXRB-encode ( 00 001000 0 1 0 11111 0 11111 Rn Rt -- )
+
+! LDXRH: Load Exclusive Register Halfword.
+ARM-INSTRUCTION: LDXRH-encode ( 01 001000 0 1 0 11111 0 11111 Rn Rt -- )
+
+! LSL (immediate): Logical Shift Left (immediate): an alias of UBFM.
+ARM-INSTRUCTION: LSLi-encode ( bw 10 100110 bw immr bw 00000 Rn Rd -- )
+
+! LSL (register): Logical Shift Left (register): an alias of LSLV.
+ARM-INSTRUCTION: LSLr-encode ( bw 0 0 11010110 Rm 0010 00 Rn Rd -- )
+
+! LSLV: Logical Shift Left Variable.
+ARM-INSTRUCTION: LSLV-encode ( bw 0 0 11010110 Rm 0010 00 Rn Rd -- )
+
+! LSR (immediate): Logical Shift Right (immediate): an alias of UBFM.
+ARM-INSTRUCTION: LSRi-encode ( bw 10 100110 bw immr bw 11111 Rn Rd -- )
+
+! LSR (register): Logical Shift Right (register): an alias of LSRV.
+ARM-INSTRUCTION: LSRr-encode ( bw 0 0 11010110 Rm 0010 01 Rn Rd -- )
+
+! LSRV: Logical Shift Right Variable.
+ARM-INSTRUCTION: LSRV-encode ( bw 0 0 11010110 Rm 0010 01 Rn Rd -- )
+
+! MADD: Multiply-Add.
+ARM-INSTRUCTION: MADD-encode ( bw 00 11011 000 Rm 0 Ra Rn Rd -- )
+
+! MNEG: Multiply-Negate: an alias of MSUB.
+ARM-INSTRUCTION: MNEG-encode ( bw 00 11011 000 Rm 1 11111 Rn Rd -- )
+
+! MOV (bitmask immediate): Move (bitmask immediate): an alias of ORR (immediate).
+ARM-INSTRUCTION: MOVbi-encode ( bw 01 100100 (N)immrimms 11111 Rn -- )
+
+! MOV (inverted wide immediate): Move (inverted wide immediate): an alias of MOVN.
+ARM-INSTRUCTION: MOViwi-encode ( bw 00 100101 hw2 imm16 Rd -- )
+
+! MOV (register): Move (register): an alias of ORR (shifted register).
+ARM-INSTRUCTION: MOVr-encode ( bw 01 01010 00 0 Rm 000000 11111 Rd -- )
+
+! MOV (to/from SP): Move between register and stack pointer: an alias of ADD (immediate).
+ARM-INSTRUCTION: MOVsp-encode ( bw 0 0 10001 shift2 000000000000 Rn Rd -- )
+
+! MOV (wide immediate): Move (wide immediate): an alias of MOVZ.
+ARM-INSTRUCTION: MOVwi-encode ( bw 10 100101 hw2 imm16 Rd -- )
+
+! MOVK: Move wide with keep.
+ARM-INSTRUCTION: MOVK-encode ( bw 11 100101 hw2 imm16 Rd -- )
+
+! MOVN: Move wide with NOT.
+ARM-INSTRUCTION: MOVN-encode ( bw 00 100101 hw2 imm16 Rd -- )
+
+! MOVZ: Move wide with zero.
+ARM-INSTRUCTION: MOVZ-encode ( bw 10 100101 hw2 imm16 Rd -- )
+
+! MRS: Move System Register.
+! System register name, encoded in the "o0:op1:CRn:CRm:op2"
+ARM-INSTRUCTION: MRS-encode ( 1101010100 1 op2 op3 CRn CRm op3 Rt -- )
+
+! MSR (immediate): Move immediate value to Special Register.
+ARM-INSTRUCTION: MSRi-encode ( 1101010100 0 00 op3 0100 CRm op3 11111 -- )
+
+! MSR (register): Move general-purpose register to System Register.
+ARM-INSTRUCTION: MSRr-encode ( 1101010100 0 op2 op3 CRn CRm op3 Rt -- )
+
+! MSUB: Multiply-Subtract.
+ARM-INSTRUCTION: MSUB-encode ( bw 00 11011 000 Rm 1 Ra Rn Rd -- )
+
+! MUL: Multiply: an alias of MADD.
+ARM-INSTRUCTION: MUL-encode ( bw 00 11011 000 Rm 0 11111 Rn Rd -- )
+
+! MVN: Bitwise NOT: an alias of ORN (shifted register).
+ARM-INSTRUCTION: MVN-encode ( bw 0 1 01010 shift2 1 Rm imm6 11111 Rd -- )
+
+! NEG (shifted register): Negate (shifted register): an alias of SUB (shifted register).
+ARM-INSTRUCTION: NEG-encode ( bw 1 0 01011 shift2 0 Rm imm6 11111 Rd -- )
+
+! NEGS: Negate, setting flags: an alias of SUBS (shifted register).
+ARM-INSTRUCTION: NEGS-encode ( bw 1 1 01011 shift2 0 Rm imm6 11111 Rd -- )
+
+! NGC: Negate with Carry: an alias of SBC.
+ARM-INSTRUCTION: NGC-encode ( bw 1 0 11010000 Rm 000000 11111 Rd -- )
+
+! NGCS: Negate with Carry, setting flags: an alias of SBCS.
+ARM-INSTRUCTION: NGCS-encode ( bw 1 1 11010000 Rm 000000 11111 Rd -- )
+
+! NOP: No Operation.
+ARM-INSTRUCTION: NOP-encode ( 1101010100 0 00 011 0010 0000 000 11111 -- )
+
+! ORN (shifted register): Bitwise OR NOT (shifted register).
+ARM-INSTRUCTION: ORNsr-encode ( bw 01 01010 shift2 1 Rm imm6 Rn Rd -- )
+
+! ORR (immediate): Bitwise OR (immediate).
+ARM-INSTRUCTION: ORRi-encode ( bw 01 100100 (N)immrimms Rn Rd -- )
+
+! ORR (shifted register): Bitwise OR (shifted register).
+ARM-INSTRUCTION: ORRsr-encode ( bw 01 01010 shift2 0 Rm imm6 Rn Rd -- )
+
+! PACDA, PACDZA: Pointer Authentication Code for Data address, using key A.
+! ARMv8.3
+ARM-INSTRUCTION: PACDA-encode ( 1 1 0 11010110 00001 0 0 0 010 Rn Rd -- )
+ARM-INSTRUCTION: PACDZA-encode ( 1 1 0 11010110 00001 0 0 1 010 11111 Rd -- )
+
+! PACDB, PACDZB: Pointer Authentication Code for Data address, using key B.
+! ARMv8.3
+ARM-INSTRUCTION: PACDB-encode ( 1 1 0 11010110 00001 0 0 0 011 Rn Rd -- )
+ARM-INSTRUCTION: PACDZB-encode ( 1 1 0 11010110 00001 0 0 1 011 11111 Rd -- )
+
+! PACGA: Pointer Authentication Code, using Generic key.
+! ARMv8.3
+ARM-INSTRUCTION: PACGA-encode ( 1 0 0 11010110 Rm 001100 Rn Rd -- )
+
+! PACIA, PACIA1716, PACIASP, PACIAZ, PACIZA: Pointer Authentication Code for Instruction address, using key A.
+! ARMv8.3
+ARM-INSTRUCTION: PACIA-encode ( 1 1 0 11010110 00001 0 0 0 000 Rn Rd -- )
+ARM-INSTRUCTION: PACIZA-encode ( 1 1 0 11010110 00001 0 0 1 000 Rn Rd -- )
+! ARMv8.3
+ARM-INSTRUCTION: PACIA1716-encode ( 1101010100 0 00 011 0010 0001 000 11111 -- )
+ARM-INSTRUCTION: PACIASP-encode ( 1101010100 0 00 011 0010 0011 001 11111 -- )
+ARM-INSTRUCTION: PACIAZ-encode ( 1101010100 0 00 011 0010 0011 000 11111 -- )
+
+! PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZB: Pointer Authentication Code for Instruction address, using key B.
+! ARMv8.3
+ARM-INSTRUCTION: PACIB-encode ( 1 1 0 11010110 00001 0 0 0 001 Rn Rd -- )
+ARM-INSTRUCTION: PACIZB-encode ( 1 1 0 11010110 00001 0 0 1 001 Rn Rd -- )
+! ARMv8.3
+ARM-INSTRUCTION: PACIB1716-encode ( 1101010100 0 00 011 0010 0001 010 11111 -- )
+ARM-INSTRUCTION: PACIBSP-encode ( 1101010100 0 00 011 0010 0011 011 11111 -- )
+ARM-INSTRUCTION: PACIBZ-encode ( 1101010100 0 00 011 0010 0011 010 11111 -- )
+
+! PRFM (immediate): Prefetch Memory (immediate).
+ARM-INSTRUCTION: PRFMi-encode ( 11 111 0 01 10 imm12 Rn Rt -- )
+
+! PRFM (literal): Prefetch Memory (literal).
+ARM-INSTRUCTION: PRFMl-encode ( 11 011 0 00 imm19 Rt -- )
+
+! PRFM (register): Prefetch Memory (register).
+ARM-INSTRUCTION: PRFMr-encode ( 11 111 0 00 10 1 Rm option3 S 10 Rn Rt -- )
+
+! PRFM (unscaled offset): Prefetch Memory (unscaled offset).
+ARM-INSTRUCTION: PRFMunscoff-encode ( 11 111 0 00 10 0 imm9 00 Rn Rt -- )
+
+! PSB CSYNC: Profiling Synchronization Barrier.
+! ARMv8.2
+ARM-INSTRUCTION: PSB-CSYNC-encode ( 1101010100 0 00 011 0010 0010 001 11111 -- )
+
+! PSSBB: Physical Speculative Store Bypass Barrier.
+ARM-INSTRUCTION: PSSBB-encode ( 1101010100 0 00 011 0011 0100 1 00 11111 -- )
+
+! RBIT: Reverse Bits.
+ARM-INSTRUCTION: RBIT-encode ( bw 1 0 11010110 00000 0000 00 Rn Rd -- )
+
+! RET: Return from subroutine.
+ARM-INSTRUCTION: RET-encode ( 1101011 0 0 10 11111 0000 0 0 Rn 00000 -- )
+
+! RETAA, RETAB: Return from subroutine, with pointer authentication.
+! ARMv8.3
+ARM-INSTRUCTION: RETAA-encode ( 1101011 0 0 10 11111 0000 1 0 11111 11111 -- )
+ARM-INSTRUCTION: RETAB-encode ( 1101011 0 0 10 11111 0000 1 1 11111 11111 -- )
+
+! REV: Reverse Bytes.
+ARM-INSTRUCTION: REV-encode ( bw 1 0 11010110 00000 0000 10 Rn Rd -- )
+
+! REV16: Reverse bytes in 16-bit halfwords.
+ARM-INSTRUCTION: REV16-encode ( bw 1 0 11010110 00000 0000 01 Rn Rd -- )
+
+! REV32: Reverse bytes in 32-bit words.
+ARM-INSTRUCTION: REV32-encode ( 1 1 0 11010110 00000 0000 10 Rn Rd -- )
+
+! REV64: Reverse Bytes: an alias of REV.
+ARM-INSTRUCTION: REV64-encode ( 1 1 0 11010110 00000 0000 11 Rn Rd -- )
+
+! RMIF: Rotate, Mask Insert Flags.
+! ARMv8.4
+ARM-INSTRUCTION: RMIF-encode ( 1 0 1 11010000 imm6 00001 Rn 0 mask4 -- )
+
+! ROR (immediate): Rotate right (immediate): an alias of EXTR.
+ARM-INSTRUCTION: RORi-encode ( bw 00 100111 0 0 Rm 0 imm5 Rn Rd -- )
+
+! ROR (register): Rotate Right (register): an alias of RORV.
+ARM-INSTRUCTION: RORr-encode ( bw 0 0 11010110 Rm 0010 11 Rn Rd -- )
+
+! RORV: Rotate Right Variable.
+ARM-INSTRUCTION: RORV-encode ( bw 0 0 11010110 Rm 0010 11 Rn Rd -- )
+
+! SB: Speculation Barrier.
+ARM-INSTRUCTION: SB-encode ( 1101010100 0 00 011 0011 0000 1 11 11111 -- )
+
+! SBC: Subtract with Carry.
+ARM-INSTRUCTION: SBC-encode ( bw 1 0 11010000 Rm 000000 Rn Rd -- )
+
+! SBCS: Subtract with Carry, setting flags.
+ARM-INSTRUCTION: SBCS-encode ( bw 1 1 11010000 Rm 000000 Rn Rd -- )
+
+! SBFIZ: Signed Bitfield Insert in Zero: an alias of SBFM.
+ARM-INSTRUCTION: SBFIZ-encode ( bw 00 100110 0 immr imms Rn Rd -- )
+
+! SBFM: Signed Bitfield Move.
+ARM-INSTRUCTION: SBFM-encode ( bw 00 100110 0 immr imms Rn Rd -- )
+
+! SBFX: Signed Bitfield Extract: an alias of SBFM.
+ARM-INSTRUCTION: SBFX-encode ( bw 00 100110 0 immr imms Rn Rd -- )
+
+! SCVTF (scalar, integer): Signed integer Convert to Floting-point (scalar).
+ARM-INSTRUCTION: SCVTFsi-encode ( bw 0 0 11110 ftype 1 00 010 000000 Rn Rd -- )
+
+! SDIV: Signed Divide.
+ARM-INSTRUCTION: SDIV-encode ( bw 0 0 11010110 Rm 00001 1 Rn Rd -- )
+
+! SETF8, SETF16: Evaluation of 8 or 16 bit flag values.
+! ARMv8.4
+ARM-INSTRUCTION: SETF8-encode ( 0 0 1 11010000 000000 0 0010 Rn 0 1101 -- )
+ARM-INSTRUCTION: SETF16-encode ( 0 0 1 11010000 000000 1 0010 Rn 0 1101 -- )
+
+! SEV: Send Event.
+ARM-INSTRUCTION: SEV-encode ( 1101010100 0 00 011 0010 0000 100 11111 -- )
+
+! SEVL: Send Event Local.
+ARM-INSTRUCTION: SEVL-encode ( 1101010100 0 00 011 0010 0000 101 11111 -- )
+
+! SMADDL: Signed Multiply-Add Long.
+ARM-INSTRUCTION: SMADDL-encode ( 1 00 11011 0 01 Rm 0 Ra Rn Rd -- )
+
+! SMC: Secure Monitor Call.
+ARM-INSTRUCTION: SMC-encode ( 11010100 000 imm16 000 11 -- )
+
+! SMNEGL: Signed Multiply-Negate Long: an alias of SMSUBL.
+ARM-INSTRUCTION: SMNEGL-encode ( 1 00 11011 0 01 Rm 1 11111 Rn Rd -- )
+
+! SMSUBL: Signed Multiply-Subtract Long.
+ARM-INSTRUCTION: SMSUBL-encode ( 1 00 11011 0 01 Rm 1 Ra Rn Rd -- )
+
+! SMULH: Signed Multiply High.
+ARM-INSTRUCTION: SMULH-encode ( 1 00 11011 0 10 Rm 0 11111 Rn Rd -- )
+
+! SMULL: Signed Multiply Long: an alias of SMADDL.
+ARM-INSTRUCTION: SMULL-encode ( 1 00 11011 0 01 Rm 0 11111 Rn Rd -- )
+
+! SSBB: Speculative Store Bypass Barrier.
+ARM-INSTRUCTION: SSBB-encode ( 1101010100 0 00 011 0011 0000 1 00 11111 -- )
+
+! ST2G: Store Allocation Tags.
+! ARMv8.5
+ARM-INSTRUCTION: ST2Gpost-encode ( 11011001 1 0 1 imm9 0 1 Xn 11111 -- )
+ARM-INSTRUCTION: ST2Gpre-encode ( 11011001 1 0 1 imm9 1 1 Xn 11111 -- )
+ARM-INSTRUCTION: ST2Gsoff-encode ( 11011001 1 0 1 imm9 1 0 Xn 11111 -- )
+
+! STADD, STADDL: Atomic add on word or doubleword in memory, without return: an alias of LDADD, LDADDA, LDADDAL, LDADDL.
+ARM-INSTRUCTION: STADD-encode ( 1 bw 111 0 00 0 0 1 Rs 0 000 00 Rn 11111 -- )
+ARM-INSTRUCTION: STADDL-encode ( 1 bw 111 0 00 0 1 1 Rs 0 000 00 Rn 11111 -- )
+
+! STADDB, STADDLB: Atomic add on byte in memory, without return: an alias of LDADDB, LDADDAB, LDADDALB, LDADDLB.
+! ARMv8.1
+ARM-INSTRUCTION: STADDB-encode ( 00 111 0 00 0 0 1 Rs 0 000 00 Rn 11111 -- )
+ARM-INSTRUCTION: STADDLB-encode ( 00 111 0 00 0 1 1 Rs 0 000 00 Rn 11111 -- )
+
+! STADDH, STADDLH: Atomic add on halfword in memory, without return: an alias of LDADDH, LDADDAH, LDADDALH, LDADDLH.
+ARM-INSTRUCTION: STADDH-encode ( 01 111 0 00 0 0 1 Rs 0 000 00 Rn 11111 -- )
+ARM-INSTRUCTION: STADDLH-encode ( 01 111 0 00 0 1 1 Rs 0 000 00 Rn 11111 -- )
+
+! STCLR, STCLRL: Atomic bit clear on word or doubleword in memory, without return: an alias of LDCLR, LDCLRA, LDCLRAL, LDCLRL.
+! ARMv8.1
+ARM-INSTRUCTION: STCLR-encode ( 1 bw 111 0 00 0 0 1 Rs 0 001 00 Rn 11111 -- )
+ARM-INSTRUCTION: STCLRL-encode ( 1 bw 111 0 00 0 0 1 Rs 0 001 00 Rn 11111 -- )
+
+! STCLRB, STCLRLB: Atomic bit clear on byte in memory, without return: an alias of LDCLRB, LDCLRAB, LDCLRALB, LDCLRLB.
+! ARMv8.1
+ARM-INSTRUCTION: STCLRB-encode ( 00 111 0 00 0 0 1 Rs 0 001 00 Rn 11111 -- )
+ARM-INSTRUCTION: STCLRLB-encode ( 00 111 0 00 0 1 1 Rs 0 001 00 Rn 11111 -- )
+
+! STCLRH, STCLRLH: Atomic bit clear on halfword in memory, without return: an alias of LDCLRH, LDCLRAH, LDCLRALH, LDCLRLH.
+! ARMv8.1
+ARM-INSTRUCTION: STCLRH-encode ( 01 111 0 00 0 0 1 Rs 0 001 00 Rn 11111 -- )
+ARM-INSTRUCTION: STCLRLH-encode ( 01 111 0 00 0 1 1 Rs 0 001 00 Rn 11111 -- )
+
+! STEOR, STEORL: Atomic exclusive OR on word or doubleword in memory, without return: an alias of LDEOR, LDEORA, LDEORAL, LDEORL.
+! ARMv8.1
+ARM-INSTRUCTION: STEOR-encode ( 1 bw 111 0 00 0 0 1 Rs 0 010 00 Rn 11111 -- )
+ARM-INSTRUCTION: STEORL-encode ( 1 bw 111 0 00 0 1 1 Rs 0 010 00 Rn 11111 -- )
+
+! STEORB, STEORLB: Atomic exclusive OR on byte in memory, without return: an alias of LDEORB, LDEORAB, LDEORALB, LDEORLB.
+! ARMv8.1
+ARM-INSTRUCTION: STEORB-encode ( 00 111 0 00 0 0 1 Rs 0 010 00 Rn 11111 -- )
+ARM-INSTRUCTION: STEORLB-encode ( 00 111 0 00 0 1 1 Rs 0 010 00 Rn 11111 -- )
+
+! STEORH, STEORLH: Atomic exclusive OR on halfword in memory, without return: an alias of LDEORH, LDEORAH, LDEORALH, LDEORLH.
+! ARMv8.1
+ARM-INSTRUCTION: STEORH-encode ( 01 111 0 00 0 0 1 Rs 0 010 00 Rn 11111 -- )
+ARM-INSTRUCTION: STEORLH-encode ( 01 111 0 00 0 1 1 Rs 0 010 00 Rn 11111 -- )
+
+! STG: Store Allocation Tag.
+! ARMv8.5
+ARM-INSTRUCTION: STGpost-encode ( 11011001 0 0 1 imm9 0 1 Xn 11111 -- )
+ARM-INSTRUCTION: STGpre-encode ( 11011001 0 0 1 imm9 1 1 Xn 11111 -- )
+ARM-INSTRUCTION: STGsoff-encode ( 11011001 0 0 1 imm9 1 0 Xn 11111 -- )
+
+! STGP: Store Allocation Tag and Pair of registers.
+! ARMv8.5
+ARM-INSTRUCTION: STGPpost-encode ( 0 1 101 0 001 0 simm7 Xt2 Xn Xt -- )
+ARM-INSTRUCTION: STGPpre-encode ( 0 1 101 0 011 0 simm7 Xt2 Xn Xt -- )
+ARM-INSTRUCTION: STGPsoff-encode ( 0 1 101 0 010 0 simm7 Xt2 Xn Xt -- )
+
+! STGV: Store Tag Vector.
+! ARMv8.5
+ARM-INSTRUCTION: STGV-encode ( 11011001 1 0 1 0 0 0 0 0 0 0 0 0 0 0 Xn Xt -- )
+
+! STLLR: Store LORelease Register.
+! ARMv8.1
+ARM-INSTRUCTION: STLLR-encode ( 1 bw 001000 1 0 0 11111 0 11111 Rn Rt -- )
+
+! STLLRB: Store LORelease Register Byte.
+! ARMv8.1
+ARM-INSTRUCTION: STLLRB-encode ( 00 001000 1 0 0 11111 0 11111 Rn Rt -- )
+
+! STLLRH: Store LORelease Register Halfword.
+ARM-INSTRUCTION: STLLRH-encode ( 01 001000 1 0 0 11111 0 11111 Rn Rt -- )
+
+! STLR: Store-Release Register.
+ARM-INSTRUCTION: STLR-encode ( 1 bw 001000 1 0 0 11111 1 11111 Rn Rt -- )
+
+! STLRB: Store-Release Register Byte.
+ARM-INSTRUCTION: STLRB-encode ( 00 001000 1 0 0 11111 1 11111 Rn Rt -- )
+
+! STLRH: Store-Release Register Halfword.
+ARM-INSTRUCTION: STLRH-encode ( 01 001000 1 0 0 11111 1 11111 Rn Rt -- )
+
+! STLUR: Store-Release Register (unscaled).
+ARM-INSTRUCTION: STLUR-encode ( 1 bw 011001 00 0 imm9 00 Rn Rt -- )
+
+! STLURB: Store-Release Register Byte (unscaled).
+ARM-INSTRUCTION: STLURB-encode ( 00 011001 00 0 imm9 00 Rn Rt -- )
+
+! STLURH: Store-Release Register Halfword (unscaled).
+ARM-INSTRUCTION: STLURH-encode ( 01 011001 00 0 imm9 00 Rn Rt -- )
+
+! STLXP: Store-Release Exclusive Pair of registers.
+ARM-INSTRUCTION: STLXP-encode ( 1 bw 001000 0 0 1 Rs 1 Rt2 Rn Rt -- )
+
+! STLXR: Store-Release Exclusive Register.
+ARM-INSTRUCTION: STLXR-encode ( 1 bw 001000 0 0 0 Rs 1 11111 Rn Rt -- )
+
+! STLXRB: Store-Release Exclusive Register Byte.
+ARM-INSTRUCTION: STLXRB-encode ( 00 001000 0 0 0 Rs 1 11111 Rn Rt -- )
+
+! STLXRH: Store-Release Exclusive Register Halfword.
+ARM-INSTRUCTION: STLXRH-encode ( 01 001000 0 0 0 Rs 1 11111 Rn Rt -- )
+
+! STNP: Store Pair of Registers, with non-temporal hint.
+ARM-INSTRUCTION: STNP-encode ( bw 0 101 0 000 0 imm7 Rt2 Rn Rt -- )
+
+! STP: Store Pair of Registers.
+ARM-INSTRUCTION: STPpost-encode ( bw 0 101 0 001 0 imm7 Rt2 Rn Rt -- )
+ARM-INSTRUCTION: STPpre-encode ( bw 0 101 0 011 0 imm7 Rt2 Rn Rt -- )
+ARM-INSTRUCTION: STPsoff-encode ( bw 0 101 0 010 0 imm7 Rt2 Rn Rt -- )
+
+! STR (immediate): Store Register (immediate).
+ARM-INSTRUCTION: STRpost-encode ( 1 bw 111 0 00 00 0 imm9 01 Rn Rt -- )
+ARM-INSTRUCTION: STRpre-encode ( 1 bw 111 0 00 00 0 imm9 11 Rn Rt -- )
+ARM-INSTRUCTION: STRuoff-encode ( 1 bw 111 0 01 00 imm12 Rn Rt -- )
+
+! STR (register): Store Register (register).
+ARM-INSTRUCTION: STRr-encode ( 1 bw 111 0 00 00 1 Rm option3 S 10 Rn Rt -- )
+
+! STRB (immediate): Store Register Byte (immediate).
+ARM-INSTRUCTION: STRBpost-encode ( 00 111 0 00 00 0 imm9 01 Rn Rt -- )
+ARM-INSTRUCTION: STRBpre-encode ( 00 111 0 00 00 0 imm9 11 Rn Rt -- )
+ARM-INSTRUCTION: STRBuoff-encode ( 00 111 0 01 00 imm12 Rn Rt -- )
+
+! STRB (register): Store Register Byte (register).
+ARM-INSTRUCTION: STRBer-encode ( 00 111 0 00 00 1 Rm option3 S 10 Rn Rt -- )
+ARM-INSTRUCTION: STRBsr-encode ( 00 111 0 00 00 1 Rm 011 S 10 Rn Rt -- )
+
+! STRH (immediate): Store Register Halfword (immediate).
+ARM-INSTRUCTION: STRHpost-encode ( 01 111 0 00 00 0 imm9 01 Rn Rt -- )
+ARM-INSTRUCTION: STRHpre-encode ( 01 111 0 00 00 0 imm9 11 Rn Rt -- )
+ARM-INSTRUCTION: STRHuoff-encode ( 01 111 0 01 00 imm12 Rn Rt -- )
+
+! STRH (register): Store Register Halfword (register).
+ARM-INSTRUCTION: STRHr-encode ( 01 111 0 00 00 1 Rm option3 S 10 Rn Rt -- )
+
+! STSET, STSETL: Atomic bit set on word or doubleword in memory, without return: an alias of LDSET, LDSETA, LDSETAL, LDSETL.
+! ARMv8.1
+ARM-INSTRUCTION: STSET-encode ( 1 bw 111 0 00 0 0 1 Rs 0 011 00 Rn 11111 -- )
+ARM-INSTRUCTION: STSETL-encode ( 1 bw 111 0 00 0 1 1 Rs 0 011 00 Rn 11111 -- )
+
+! STSETB, STSETLB: Atomic bit set on byte in memory, without return: an alias of LDSETB, LDSETAB, LDSETALB, LDSETLB.
+! ARMv8.1
+ARM-INSTRUCTION: STSETB-encode ( 00 111 0 00 0 0 1 Rs 0 011 00 Rn 11111 -- )
+ARM-INSTRUCTION: STSETLB-encode ( 00 111 0 00 0 1 1 Rs 0 011 00 Rn 11111 -- )
+
+! STSETH, STSETLH: Atomic bit set on halfword in memory, without return: an alias of LDSETH, LDSETAH, LDSETALH, LDSETLH.
+! ARMv8.1
+ARM-INSTRUCTION: STSETH-encode ( 01 111 0 00 0 0 1 Rs 0 011 00 Rn 11111 -- )
+ARM-INSTRUCTION: STSETLH-encode ( 01 111 0 00 0 1 1 Rs 0 011 00 Rn 11111 -- )
+
+! STSMAX, STSMAXL: Atomic signed maximum on word or doubleword in memory, without return: an alias of LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL.
+! ARMv8.1
+ARM-INSTRUCTION: STSMAX-encode ( 1 bw 111 0 00 0 0 1 Rs 0 100 00 Rn 11111 -- )
+ARM-INSTRUCTION: STSMAXL-encode ( 1 bw 111 0 00 0 1 1 Rs 0 100 00 Rn 11111 -- )
+
+! STSMAXB, STSMAXLB: Atomic signed maximum on byte in memory, without return: an alias of LDSMAXB, LDSMAXAB, LDSMAXALB, LDSMAXLB.
+! ARMv8.1
+ARM-INSTRUCTION: STSMAXB-encode ( 00 111 0 00 0 0 1 Rs 0 100 00 Rn 11111 -- )
+ARM-INSTRUCTION: STSMAXLB-encode ( 00 111 0 00 0 1 1 Rs 0 100 00 Rn 11111 -- )
+
+! STSMAXH, STSMAXLH: Atomic signed maximum on halfword in memory, without return: an alias of LDSMAXH, LDSMAXAH, LDSMAXALH, LDSMAXLH
+! ARMv8.1
+ARM-INSTRUCTION: STSMAXH-encode ( 01 111 0 00 0 0 1 Rs 0 100 00 Rn 11111 -- )
+ARM-INSTRUCTION: STSMAXLH-encode ( 01 111 0 00 0 1 1 Rs 0 100 00 Rn 11111 -- )
+
+! STSMIN, STSMINL: Atomic signed minimum on word or doubleword in memory, without return: an alias of LDSMIN, LDSMINA, LDSMINAL, LDSMINL.
+! ARMv8.1
+ARM-INSTRUCTION: STSMIN-encode ( 1 bw 111 0 00 0 0 1 Rs 0 101 00 Rn 11111 -- )
+ARM-INSTRUCTION: STSMINL-encode ( 1 bw 111 0 00 0 0 1 Rs 0 101 00 Rn 11111 -- )
+
+! STSMINB, STSMINLB: Atomic signed minimum on byte in memory, without return: an alias of LDSMINB, LDSMINAB, LDSMINALB, LDSMINLB.
+ARM-INSTRUCTION: STSMINB-encode ( 00 111 0 00 0 0 1 Rs 0 101 00 Rn 11111 -- )
+ARM-INSTRUCTION: STSMINLB-encode ( 00 111 0 00 0 1 1 Rs 0 101 00 Rn 11111 -- )
+
+! STSMINH, STSMINLH: Atomic signed minimum on halfword in memory, without return: an alias of LDSMINH, LDSMINAH, LDSMINALH, LDSMINLH.
+ARM-INSTRUCTION: STSMINH-encode ( 01 111 0 00 0 0 1 Rs 0 101 00 Rn 11111 -- )
+ARM-INSTRUCTION: STSMINLH-encode ( 01 111 0 00 0 1 1 Rs 0 101 00 Rn 11111 -- )
+
+! STTR: Store Register (unprivileged).
+ARM-INSTRUCTION: STTR-encode ( 1 bw 111 0 00 00 0 imm9 10 Rn Rt -- )
+
+! STTRB: Store Register Byte (unprivileged).
+ARM-INSTRUCTION: STTRB-encode ( 00 111 0 00 00 0 imm9 10 Rn Rt -- )
+
+! STTRH: Store Register Halfword (unprivileged).
+ARM-INSTRUCTION: STTRH-encode ( 01 111 0 00 00 0 imm9 10 Rn Rt -- )
+
+! STUMAX, STUMAXL: Atomic unsigned maximum on word or doubleword in memory, without return: an alias of LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL.
+! ARMv8.1
+ARM-INSTRUCTION: STUMAX-encode ( 1 bw 111 0 00 0 0 1 Rs 0 110 00 Rn 11111 -- )
+ARM-INSTRUCTION: STUMAXL-encode ( 1 bw 111 0 00 0 1 1 Rs 0 110 00 Rn 11111 -- )
+
+! STUMAXB, STUMAXLB: Atomic unsigned maximum on byte in memory, without return: an alias of LDUMAXB, LDUMAXAB, LDUMAXALB, LDUMAXLB.
+ARM-INSTRUCTION: STUMAXB-encode ( 00 111 0 00 0 0 1 Rs 0 110 00 Rn 11111 -- )
+ARM-INSTRUCTION: STUMAXLB-encode ( 00 111 0 00 0 1 1 Rs 0 110 00 Rn 11111 -- )
+
+! STUMAXH, STUMAXLH: Atomic unsigned maximum on halfword in memory, without return: an alias of LDUMAXH, LDUMAXAH, LDUMAXALH, LDUMAXLH.
+ARM-INSTRUCTION: STUMAXH-encode ( 01 111 0 00 0 0 1 Rs 0 110 00 Rn 11111 -- )
+ARM-INSTRUCTION: STUMAXLH-encode ( 01 111 0 00 0 1 1 Rs 0 110 00 Rn 11111 -- )
+
+! STUMIN, STUMINL: Atomic unsigned minimum on word or doubleword in memory, without return: an alias of LDUMIN, LDUMINA, LDUMINAL, LDUMINL.
+! ARMv8.1
+ARM-INSTRUCTION: STUMIN-encode ( 1 bw 111 0 00 0 0 1 Rs 0 111 00 Rn 11111 -- )
+ARM-INSTRUCTION: STUMINL-encode ( 1 bw 111 0 00 0 1 1 Rs 0 111 00 Rn 11111 -- )
+
+! STUMINB, STUMINLB: Atomic unsigned minimum on byte in memory, without return: an alias of LDUMINB, LDUMINAB, LDUMINALB, LDUMINLB.
+! ARMv8.1
+ARM-INSTRUCTION: STUMINB-encode ( 00 111 0 00 0 0 1 Rs 0 111 00 Rn 11111 -- )
+ARM-INSTRUCTION: STUMINLB-encode ( 00 111 0 00 0 1 1 Rs 0 111 00 Rn 11111 -- )
+
+! STUMINH, STUMINLH: Atomic unsigned minimum on halfword in memory, without return: an alias of LDUMINH, LDUMINAH, LDUMINALH, LDUMINLH.
+ARM-INSTRUCTION: STUMINH-encode ( 01 111 0 00 0 0 1 Rs 0 111 00 Rn 11111 -- )
+ARM-INSTRUCTION: STUMINLH-encode ( 01 111 0 00 0 1 1 Rs 0 111 00 Rn 11111 -- )
+
+! STUR: Store Register (unscaled).
+ARM-INSTRUCTION: STUR-encode ( 1 bw 111 0 00 00 0 imm9 00 Rn Rt -- )
+
+! STURB: Store Register Byte (unscaled).
+ARM-INSTRUCTION: STURB-encode ( 00 111 0 00 00 0 imm9 00 Rn Rt -- )
+
+! STURH: Store Register Halfword (unscaled).
+ARM-INSTRUCTION: STURH-encode ( 01 111 0 00 00 0 imm9 00 Rn Rt -- )
+
+! STXP: Store Exclusive Pair of registers.
+ARM-INSTRUCTION: STXP-encode ( 1 bw 001000 0 0 1 Rs 0 Rt2 Rn Rt -- )
+
+! STXR: Store Exclusive Register.
+ARM-INSTRUCTION: STXR-encode ( 1 bw 001000 0 0 0 Rs 0 11111 Rn Rt -- )
+
+! STXRB: Store Exclusive Register Byte.
+ARM-INSTRUCTION: STXRB-encode ( 00 001000 0 0 0 Rs 0 11111 Rn Rt -- )
+
+! STXRH: Store Exclusive Register Halfword.
+ARM-INSTRUCTION: STXRH-encode ( 01 001000 0 0 0 Rs 0 11111 Rn Rt -- )
+
+! STZ2G: Store Allocation Tags, Zeroing.
+! ARMv8.5
+ARM-INSTRUCTION: STZ2Gpost-encode ( 11011001 1 1 1 imm9 0 1 Xn 11111 -- )
+ARM-INSTRUCTION: STZ2Gpre-encode ( 11011001 1 1 1 imm9 1 1 Xn 11111 -- )
+ARM-INSTRUCTION: STZ2Gsoff-encode ( 11011001 1 1 1 imm9 1 0 Xn 11111 -- )
+
+! STZG: Store Allocation Tag, Zeroing.
+! ARMv8.5
+ARM-INSTRUCTION: STZGpost-encode ( 11011001 0 1 1 imm9 0 1 Xn 11111 -- )
+ARM-INSTRUCTION: STZGpre-encode ( 11011001 0 1 1 imm9 1 1 Xn 11111 -- )
+ARM-INSTRUCTION: STZGsoff-encode ( 11011001 0 1 1 imm9 1 0 Xn 11111 -- )
+
+! SUB (extended register): Subtract (extended register).
+ARM-INSTRUCTION: SUBer-encode ( bw 1 0 01011 00 1 Rm option3 imm3 Rn Rd -- )
+
+! SUB (immediate): Subtract (immediate).
+ARM-INSTRUCTION: SUBi-encode ( bw 1 0 10001 shift2 imm12 Rn Rd -- )
+
+! SUB (shifted register): Subtract (shifted register).
+ARM-INSTRUCTION: SUBsr-encode ( bw 1 0 01011 shift2 0 Rm imm6 Rn Rd -- )
+
+! SUBG: Subtract with Tag.
+! ARMv8.5
+ARM-INSTRUCTION: SUBG-encode ( 1 1 0 100011 0 uimm6 00 uimm4 Xn Xd -- )
+
+! SUBP: Subtract Pointer.
+! ARMv8.5
+ARM-INSTRUCTION: SUBP-encode ( 1 0 0 11010110 Xm 0 0 0 0 0 0 Xn Xd -- )
+
+! SUBPS: Subtract Pointer, setting Flags.
+! ARMv8.5
+ARM-INSTRUCTION: SUBPS-encode ( 1 0 1 11010110 Xm 0 0 0 0 0 0 Xn Xd -- )
+
+! SUBS (extended register): Subtract (extended register), setting flags.
+ARM-INSTRUCTION: SUBSer-encode ( bw 1 1 01011 00 1 Rm option3 imm3 Rn Rd -- )
+
+! SUBS (immediate): Subtract (immediate), setting flags.
+ARM-INSTRUCTION: SUBSimm-encode ( bw 1 1 10001 shift2 imm12 Rn Rd -- )
+
+! SUBS (shifted register): Subtract (shifted register), setting flags.
+ARM-INSTRUCTION: SUBSsr-encode ( bw 1 1 01011 shift2 0 Rm imm6 Rn Rd -- )
+
+! SVC: Supervisor Call.
+ARM-INSTRUCTION: SVC-encode ( 11010100 000 imm16 000 01 -- )
+
+! SWP, SWPA, SWPAL, SWPL: Swap word or doubleword in memory
+! ARMv8.1
+ARM-INSTRUCTION: SWP-encode ( 1 bw 111 0 00 0 0 1 Rs 1 000 00 Rn Rt -- )
+ARM-INSTRUCTION: SWPA-encode ( 1 bw 111 0 00 1 0 1 Rs 1 000 00 Rn Rt -- )
+ARM-INSTRUCTION: SWPAL-encode ( 1 bw 111 0 00 1 1 1 Rs 1 000 00 Rn Rt -- )
+ARM-INSTRUCTION: SWPL-encode ( 1 bw 111 0 00 0 1 1 Rs 1 000 00 Rn Rt -- )
+
+! SWPB, SWPAB, SWPALB, SWPLB: Swap byte in memory.
+! ARMv8.1
+ARM-INSTRUCTION: SWPAB-encode ( 00 111 0 00 1 0 1 Rs 1 000 00 Rn Rt -- )
+ARM-INSTRUCTION: SWPALB-encode ( 00 111 0 00 1 1 1 Rs 1 000 00 Rn Rt -- )
+ARM-INSTRUCTION: SWPB-encode ( 00 111 0 00 0 0 1 Rs 1 000 00 Rn Rt -- )
+ARM-INSTRUCTION: SWPLB-encode ( 00 111 0 00 0 1 1 Rs 1 000 00 Rn Rt -- )
+
+! SWPH, SWPAH, SWPALH, SWPLH: Swap halfword in memory.
+ARM-INSTRUCTION: SWPAH-encode ( 01 111 0 00 1 0 1 Rs 1 000 00 Rn Rt -- )
+ARM-INSTRUCTION: SWPALH-encode ( 01 111 0 00 1 1 1 Rs 1 000 00 Rn Rt -- )
+ARM-INSTRUCTION: SWPH-encode ( 01 111 0 00 0 0 1 Rs 1 000 00 Rn Rt -- )
+ARM-INSTRUCTION: SWPLH-encode ( 01 111 0 00 0 1 1 Rs 1 000 00 Rn Rt -- )
+
+! SXTB: Signed Extend Byte: an alias of SBFM.
+ARM-INSTRUCTION: SXTB-encode ( bw 00 100110 0 000000 000111 Rn Rd -- )
+
+! SXTH: Sign Extend Halfword: an alias of SBFM.
+ARM-INSTRUCTION: SXTH-encode ( bw 00 100110 0 000000 001111 Rn Rd -- )
+
+! SXTW: Sign Extend Word: an alias of SBFM.
+ARM-INSTRUCTION: SXTW-encode ( 1 00 100110 1 000000 011111 Rn Rd -- )
+
+! SYS: System instruction.
+ARM-INSTRUCTION: SYS-encode ( 1101010100 0 01 op3 CRn CRm op3 Rt -- )
+
+! SYSL: System instruction with result.
+ARM-INSTRUCTION: SYSL-encode ( 1101010100 1 01 op3 CRn CRm op3 Rt -- )
+
+! TBNZ: Test bit and Branch if Nonzero.
+ARM-INSTRUCTION: TBNZW-encode ( 0 011011 1 b40 imm14 Rt -- )
+ARM-INSTRUCTION: TBNZX-encode ( 1 011011 1 b40 imm14 Rt -- )
+
+! TBZ: Test bit and Branch if Zero.
+ARM-INSTRUCTION: TBHZW-encode ( 0 011011 0 b40 imm14 Rt -- )
+ARM-INSTRUCTION: TBHZX-encode ( 1 011011 0 b40 imm14 Rt -- )
+
+! TLBI: TLB Invalidate operation: an alias of SYS.
+ARM-INSTRUCTION: TLBI-encode ( 1101010100 0 01 op3 1000 CRm op3 Rt -- )
+
+! TSB CSYNC: Trace Synchronization Barrier.
+! ARMv8.4
+ARM-INSTRUCTION: TSB-CSYNC-encode ( 1101010100 0 00 011 0010 0010 010 11111 -- )
+
+! TST (immediate): Test bits (immediate): an alias of ANDS (immediate).
+ARM-INSTRUCTION: TSTi-encode ( bw 11 100100 (N)immrimms Rn 11111 -- )
+
+! TST (shifted register): Test (shifted register): an alias of ANDS (shifted register).
+ARM-INSTRUCTION: TSTsr-encode ( bw 11 01010 shift2 0 Rm imm6 Rn 11111 -- )
+
+! UBFIZ: Unsigned Bitfield Insert in Zero: an alias of UBFM.
+ARM-INSTRUCTION: UBFIZ-encode ( bw 10 100110 0 immr imms Rn Rd -- )
+
+! UBFM: Unsigned Bitfield Move.
+ARM-INSTRUCTION: UBFM-encode ( bw 10 100110 0 immr imms Rn Rd -- )
+
+! UBFX: Unsigned Bitfield Extract: an alias of UBFM.
+ARM-INSTRUCTION: UBFX-encode ( bw 10 100110 0 immr imms Rn Rd -- )
+
+! UDF: Permanently Undefined.
+ARM-INSTRUCTION: UDF-encode ( 0000000000000000 imm16 -- )
+
+! UDIV: Unsigned Divide.
+ARM-INSTRUCTION: UDIV-encode ( bw 0 0 11010110 Rm 00001 0 Rn Rd -- )
+
+! UMADDL: Unsigned Multiply-Add Long.
+ARM-INSTRUCTION: UMADDL-encode ( 1 00 11011 1 01 Rm 0 Ra Rn Rd -- )
+
+! UMNEGL: Unsigned Multiply-Negate Long: an alias of UMSUBL.
+ARM-INSTRUCTION: UMNEGL-encode ( 1 00 11011 1 01 Rm 1 11111 Rn Rd -- )
+
+! UMSUBL: Unsigned Multiply-Subtract Long.
+ARM-INSTRUCTION: UMSUBL-encode ( 1 00 11011 1 01 Rm 1 Ra Rn Rd -- )
+
+! UMULH: Unsigned Multiply High.
+ARM-INSTRUCTION: UMULH-encode ( 1 00 11011 1 10 Rm 0 11111 Rn Rd -- )
+
+! UMULL: Unsigned Multiply Long: an alias of UMADDL.
+ARM-INSTRUCTION: UMULL-encode ( 1 00 11011 1 01 Rm 0 11111 Rn Rd -- )
+
+! UXTB: Unsigned Extend Byte: an alias of UBFM.
+ARM-INSTRUCTION: UXTB-encode ( 0 10 100110 0 000000 000111 Rn Rd -- )
+
+! UXTH: Unsigned Extend Halfword: an alias of UBFM.
+ARM-INSTRUCTION: UXTH-encode ( 0 10 100110 0 000000 000111 Rn Rd -- )
+
+! WFE: Wait For Event.
+ARM-INSTRUCTION: WFE-encode ( 1101010100 0 00 011 0010 0000 010 11111 -- )
+
+! WFI: Wait For Interrupt.
+ARM-INSTRUCTION: WFI-encode ( 1101010100 0 00 011 0010 0000 011 11111 -- )
+
+! XAFlag: Convert floating-point condition flags from external format to ARM format.
+ARM-INSTRUCTION: XAFlag-encode ( 1101010100 0 00 000 0100 0000 001 11111 -- )
+
+! XPACD, XPACI, XPACLRI: Strip Pointer Authentication Code.
+! ARMv8.3
+ARM-INSTRUCTION: XPACD-encode ( 1 1 0 11010110 00001 0 1 000 1 11111 Rd -- )
+ARM-INSTRUCTION: XPACI-encode ( 1 1 0 11010110 00001 0 1 000 0 11111 Rd -- )
+ARM-INSTRUCTION: XPACLRI-encode ( 1101010100 0 00 011 0010 0000 111 11111 -- )
+
+! YIELD: YIELD.
+ARM-INSTRUCTION: YIELD-encode ( 1101010100 0 00 011 0010 0000 001 11111 -- )
HOOK: ds-reg cpu ( -- reg )
HOOK: rs-reg cpu ( -- reg )
-
-ALIAS: eh? f
+++ /dev/null
-! Copyright (C) 2023 Doug Coleman.
-! Copyright (C) 2023 Giftpflanze.
-! See https://factorcode.org/license.txt for BSD license.
-USING: cpu.arm.assembler cpu.arm.assembler.opcodes kernel math ;
-IN: cpu.arm.assembler.32
-
-: ADC ( Rm Rn Rd -- ) ADC32-encode ;
-: ADCS ( Rm Rn Rd -- ) ADCS32-encode ;
-
-: ADDi ( uimm24 Rn Rd -- ) [ split-imm ] 2dip ADDi32-encode ;
-
-: ASRi ( uimm6 Rn Rd -- ) [ 6 ?ubits ] 2dip ASRi32-encode ;
-
-: CMPi ( uimm24 Rd -- ) [ split-imm ] dip CMPi32-encode ;
-
-: LSLi ( uimm6 Rn Rd -- ) [ 6 ?ubits ] 2dip LSLi32-encode ;
-: LSRi ( uimm6 Rn Rd -- ) [ 6 ?ubits ] 2dip LSRi32-encode ;
-
-: STRuoff ( uimm14 Rn Rt -- ) [ 2 ?>> 12 ?ubits ] 2dip STRuoff32-encode ;
-
-: SUBi ( uimm24 Rn Rd -- ) [ split-imm ] 2dip SUBi32-encode ;
+++ /dev/null
-Doug Coleman
+++ /dev/null
-! Copyright (C) 2023 Doug Coleman.
-! See https://factorcode.org/license.txt for BSD license.
-USING: cpu.arm.assembler.64 cpu.arm.assembler.opcodes make
-tools.test ;
-IN: cpu.arm.assembler.64.tests
-
-{ { 0x10 0x02 0x00 0x91 } } [ [ 0 X16 X16 ADDi ] { } make ] unit-test
-{ { 0x10 0x22 0x00 0x91 } } [ [ 8 X16 X16 ADDi ] { } make ] unit-test
-{ { 0x10 0xe2 0x3f 0x91 } } [ [ 0xff8 X16 X16 ADDi ] { } make ] unit-test
-
-! mov x29, #0x0
-{ { 0x1d 0x00 0x80 0xd2 } } [ [ 0 X29 MOVwi ] { } make ] unit-test
-{ { 0x1e 0x00 0x80 0xd2 } } [ [ 0 X30 MOVwi ] { } make ] unit-test
-{ { 0xe5 0x03 0x00 0xaa } } [ [ X0 X5 MOVr ] { } make ] unit-test
-
-{ { 0x20 0xfc 0x6c 0xd3 } } [ [ 44 X1 X0 LSRi ] { } make ] unit-test
-
-{ { 0xfd 0x7b 0xbf 0xa9 } } [ [ -16 SP X30 X29 STPpre ] { } make ] unit-test
-{ { 0xf0 0x7b 0xbf 0xa9 } } [ [ -16 SP X30 X16 STPpre ] { } make ] unit-test
-
-{ { 0x11 0xfe 0x47 0xf9 } } [ [ 4088 X16 X17 LDRuoff ] { } make ] unit-test
-{ { 0x11 0x02 0x40 0xf9 } } [ [ 0 X16 X17 LDRuoff ] { } make ] unit-test
-! ldr x17, [x16, #8]
-{ { 0x11 0x06 0x40 0xf9 } } [ [ 8 X16 X17 LDRuoff ] { } make ] unit-test
-
-! ldr x1, [sp]
-{ { 0xe1 0x03 0x40 0xf9 } } [ [ 0 SP X1 LDRuoff ] { } make ] unit-test
-
-{ { 0x08 0xed 0x7c 0x92 } } [ [ -16 X8 X8 ANDi ] { } make ] unit-test
+++ /dev/null
-! Copyright (C) 2023 Doug Coleman.
-! Copyright (C) 2023 Giftpflanze.
-! See https://factorcode.org/license.txt for BSD license.
-USING: cpu.arm.assembler cpu.arm.assembler.opcodes kernel
-math.bitwise ;
-IN: cpu.arm.assembler.64
-
-: encode-bitmask ( imm64 -- Nimmrimms ) 64 (encode-bitmask) ;
-
-: ADC ( Rm Rn Rd -- ) ADC64-encode ;
-: ADCS ( Rm Rn Rd -- ) ADCS64-encode ;
-
-: ADDi ( uimm24 Rn Rd -- ) [ split-imm ] 2dip ADDi64-encode ;
-: ADDr ( Rm Rn Rd -- ) [ 3 0 ] 2dip ADDer64-encode ;
-
-: ANDi ( imm64 Rn Rd -- ) [ encode-bitmask ] 2dip ANDi64-encode ;
-: ANDr ( Rm Rn Rd -- ) [ [ 0 ] dip 0 ] 2dip ANDsr64-encode ;
-
-: ASRi ( uimm6 Rn Rd -- ) [ 6 ?ubits ] 2dip ASRi64-encode ;
-: ASRr ( Rm Rn Rd -- ) ASRr64-encode ;
-
-: BIC ( Rm Rn Rd -- ) [ [ 0 ] dip 0 ] 2dip BIC64-encode ;
-
-: CBNZ ( simm21 Rt -- ) [ 2 ?>> 19 ?sbits ] dip CBNZ64-encode ;
-
-: CLZ ( Rn Rd -- ) CLZ64-encode ;
-
-: CMPi ( imm24 Rd -- ) [ split-imm ] dip CMPi64-encode ;
-: CMPr ( Rm Rn -- ) [ 3 0 ] dip CMPer64-encode ;
-
-! cond is EQ NE CS HS CC LO MI PL VS VC HI LS GE LT GT LE AL NV
-: CSEL ( Rm Rn Rd cond -- ) -rot CSEL64-encode ;
-: CSET ( Rd cond -- ) swap CSET64-encode ;
-: CSETM ( Rd cond -- ) swap CSETM64-encode ;
-
-: EORi ( imm64 Rn Rd -- ) [ encode-bitmask ] 2dip EORi64-encode ;
-: EORr ( Rm Rn Rd -- ) [ [ 0 ] dip 0 ] 2dip EORsr64-encode ;
-
-: FCVTZSsi ( Rn Rd var -- ) >ftype -rot FCVTZSsi64-encode ;
-
-: LDPpost ( simm10 Rn Rt2 Rt -- ) [ 3 ?>> 7 ?sbits ] 3dip swapd LDPpost64-encode ;
-: LDPpre ( simm10 Rn Rt2 Rt -- ) [ 3 ?>> 7 ?sbits ] 3dip swapd LDPpre64-encode ;
-: LDPsoff ( simm10 Rn Rt2 Rt -- ) [ 3 ?>> 7 ?sbits ] 3dip swapd LDPsoff64-encode ;
-
-: LDRl ( simm21 Rt -- ) [ 2 ?>> 19 ?sbits ] dip LDRl64-encode ;
-: LDRpost ( simm9 Rn Rt -- ) [ 9 ?sbits ] 2dip LDRpost64-encode ;
-: LDRpre ( simm9 Rn Rt -- ) [ 9 ?sbits ] 2dip LDRpre64-encode ;
-: LDRr ( Rm Rn Rt -- ) [ 3 0 ] 2dip LDRr64-encode ;
-: LDRuoff ( uimm15 Rn Rt -- ) [ 3 ?>> 12 ?ubits ] 2dip LDRuoff64-encode ;
-
-: LDUR ( simm9 Rn Rt -- ) [ 9 ?sbits ] 2dip LDUR64-encode ;
-
-: LSLi ( uimm6 Rn Rd -- ) [ 6 ?ubits ] 2dip LSLi64-encode ;
-: LSLr ( Rm Rn Rd -- ) LSLr64-encode ;
-
-: LSRi ( uimm6 Rn Rd -- ) [ 6 ?ubits ] 2dip LSRi64-encode ;
-: LSRr ( Rm Rn Rd -- ) LSRr64-encode ;
-
-: MOVr ( Rn Rd -- ) MOVr64-encode ;
-: MOVsp ( Rn Rd -- ) [ 0 ] 2dip MOVsp64-encode ;
-: MOVwi ( imm16 Rd -- ) [ [ 0 ] dip 16 bits ] dip MOVwi64-encode ;
-: MOVZ ( lsl imm16 Rd -- ) [ 16 bits ] dip MOVZ64-encode ;
-: MOVK ( lsl imm16 Rd -- ) [ 16 bits ] dip MOVK64-encode ;
-
-: MSUB ( Ra Rm Rn Rd -- ) [ swap ] 2dip MSUB64-encode ;
-
-: MUL ( Rm Rn Rd -- ) MUL64-encode ;
-
-: MVN ( Rm Rd -- ) [ [ 0 ] dip 0 ] dip MVN64-encode ;
-
-: NEG ( Rm Rd -- ) [ [ 0 ] dip 0 ] dip NEG64-encode ;
-
-: ORRi ( imm64 Rn Rd -- ) [ encode-bitmask ] 2dip ORRi64-encode ;
-: ORRr ( Rm Rn Rd -- ) [ [ 0 ] dip 0 ] 2dip ORRsr64-encode ;
-
-: SCVTFsi ( Rn Rd var -- ) >ftype -rot SCVTFsi64-encode ;
-
-: SDIV ( Rm Rn Rd -- ) SDIV64-encode ;
-
-: STADD ( Rs Rn -- ) STADD64-encode ;
-
-: STPpost ( simm10 Rn Rt2 Rt -- ) [ 3 ?>> 7 ?sbits ] 3dip swapd STPpost64-encode ;
-: STPpre ( simm10 Rn Rt2 Rt -- ) [ 3 ?>> 7 ?sbits ] 3dip swapd STPpre64-encode ;
-: STPsoff ( simm10 Rn Rt2 Rt -- ) [ 3 ?>> 7 ?sbits ] 3dip swapd STPsoff64-encode ;
-
-: STRpre ( simm9 Rn Rt -- ) [ 9 ?sbits ] 2dip STRpre64-encode ;
-: STRpost ( simm9 Rn Rt -- ) [ 9 ?sbits ] 2dip STRpost64-encode ;
-: STRr ( Rm Rn Rt -- ) [ 3 0 ] 2dip STRr64-encode ;
-: STRuoff ( uimm15 Rn Rt -- ) [ 3 ?>> 12 ?ubits ] 2dip STRuoff64-encode ;
-
-: SUBi ( uimm24 Rn Rd -- ) [ split-imm ] 2dip SUBi64-encode ;
-: SUBr ( Rm Rn Rd -- ) [ 3 0 ] 2dip SUBer64-encode ;
-
-: TSTi ( imm64 Rn -- ) [ encode-bitmask ] dip TSTi64-encode ;
+++ /dev/null
-Doug Coleman
-Giftpflanze
+++ /dev/null
-! Copyright (C) 2020 Doug Coleman.
-! See https://factorcode.org/license.txt for BSD license.
-USING: cpu.arm.assembler cpu.arm.assembler.opcodes make tools.test ;
-IN: cpu.arm.assembler.tests
-
-! useful for testing maybe: https://armconverter.com/
-
-{ { 0x2e 0x01 0x10 0x94 } } [ [ 0x04004b8 BL ] { } make ] unit-test
-{ { 0x20 0x02 0x1f 0xd6 } } [ [ X17 BR ] { } make ] unit-test
-
-{ { 0xc0 0x03 0x5f 0xd6 } } [ [ f RET ] { } make ] unit-test
+++ /dev/null
-! Copyright (C) 2020 Doug Coleman.
-! Copyright (C) 2023 Giftpflanze.
-! See https://factorcode.org/license.txt for BSD license.
-USING: assocs combinators cpu.arm.assembler.opcodes
-generalizations grouping kernel math math.bitwise math.parser
-sequences shuffle ;
-IN: cpu.arm.assembler
-
-! pre-index mode: computed addres is the base-register + offset
-! ldr X1, [X2, #4]!
-! post-index mode: computed address is the base-register
-! ldr X1, [X2], #4
-! in both modes, the base-register is updated
-
-ERROR: arm64-encoding-imm original n-bits-requested truncated ;
-: ?ubits ( x n -- x )
- 2dup bits dup reach =
- [ 2drop ] [ arm64-encoding-imm ] if ; inline
-
-: ?sbits ( x n -- x )
- 2dup >signed dup reach =
- [ drop bits ] [ arm64-encoding-imm ] if ; inline
-
-ERROR: scaling-error original n-bits-shifted rest ;
-: ?>> ( x n -- x )
- 2dup bits [ neg shift ] [ scaling-error ] if-zero ;
-
-! Some instructions allow an immediate literal of n bits
-! or n bits shifted. This means there are invalid immediate
-! values, e.g. imm12 of 1, 4096, but not 4097
-ERROR: imm-out-of-range imm n ;
-: imm-lower? ( imm n -- ? ) on-bits unmask 0 > not ;
-
-: imm-upper? ( imm n -- ? )
- [ on-bits ] [ shift ] bi unmask 0 > not ;
-
-: (split-imm) ( imm n -- imm upper? )
- {
- { [ 2dup imm-lower? ] [ drop f ] }
- { [ 2dup imm-upper? ] [ drop t ] }
- [ imm-out-of-range ]
- } cond ;
-
-: split-imm ( imm -- shift imm ) 12 (split-imm) 1 0 ? swap ;
-
-! Logical immediates
-
-ERROR: illegal-bitmask-immediate n ;
-: ?bitmask ( imm imm-size -- imm )
- dupd on-bits 0 [ = ] bi-curry@ bi or
- [ dup illegal-bitmask-immediate ] when ;
-
-: element-size ( imm imm-size -- imm element-size )
- [ 2dup 2/ [ neg shift ] 2keep '[ _ on-bits bitand ] same? ]
- [ 2/ ] while ;
-
-: bit-transitions ( imm element-size -- seq )
- [ >bin ] dip CHAR: 0 pad-head 2 circular-clump ;
-
-ERROR: illegal-bitmask-element n ;
-: ?element ( imm element-size -- element )
- [ bits ] keep dupd bit-transitions
- [ first2 = not ] count 2 =
- [ dup illegal-bitmask-element ] unless ;
-
-: >Nimms ( element element-size -- N imms )
- [ bit-count 1 - ] [ log2 1 + ] bi*
- 7 [ on-bits ] bi@ bitxor bitor
- 6 toggle-bit [ -6 shift ] [ 6 bits ] bi ;
-
-: >immr ( element element-size -- immr )
- [ bit-transitions "10" swap index 1 + ] keep mod ;
-
-: (encode-bitmask) ( imm imm-size -- (N)immrimms )
- [ bits ] [ ?bitmask ] [ element-size ] tri
- [ ?element ] keep [ >Nimms ] [ >immr ] 2bi
- { 12 0 6 } bitfield* ;
-
-! Floating-point variants
-
-SYMBOLS: H S D ;
-
-: >ftype ( symbol -- n ) { { H 3 } { S 0 } { D 1 } } at ; inline
-
-
-: ADDV ( Rn Rd size Q -- ) -roll -rot ADDV-encode ;
-
-: ADR ( simm21 Rd -- ) [ [ 2 bits ] [ -2 shift 19 ?sbits ] bi ] dip ADR-encode ;
-
-: ADRP ( simm21 Rd -- ) [ 4096 / [ 2 bits ] [ -2 shift 19 ?sbits ] bi ] dip ADRP-encode ;
-
-! B but that is breakpoint
-: Br ( simm28 -- ) 2 ?>> 26 ?sbits B-encode ;
-: B.cond ( simm21 cond -- ) [ 2 ?>> 19 ?sbits ] dip B.cond-encode ;
-: BL ( simm28 -- ) 2 ?>> 26 ?sbits BL-encode ;
-: BR ( Rn -- ) BR-encode ;
-: BLR ( Rn -- ) BLR-encode ;
-
-: BRK ( uimm16 -- ) 16 ?ubits BRK-encode ;
-
-: CNT ( Vn Vd size Q -- ) -roll -rot CNT-encode ;
-
-: DUPgen ( Rn Rd size Q -- ) -roll 2^ -rot DUPgen-encode ;
-
-: FADDs ( Rm Rn Rd var -- ) >ftype -roll FADDs-encode ;
-: FCVT ( Rn Rd svar dvar -- ) [ >ftype ] bi@ 2swap FCVT-encode ;
-: FDIVs ( Rm Rn Rd var -- ) >ftype -roll FDIVs-encode ;
-: FMAXs ( Rm Rn Rd var -- ) >ftype -roll FMAXs-encode ;
-: FMINs ( Rm Rn Rd var -- ) >ftype -roll FMINs-encode ;
-: FMULs ( Rm Rn Rd var -- ) >ftype -roll FMULs-encode ;
-: FSQRTs ( Rn Rd var -- ) >ftype -rot FSQRTs-encode ;
-: FSUBs ( Rm Rn Rd var -- ) >ftype -roll FSUBs-encode ;
-
-: FMOVgen ( Rn Rd sf ftype rmode opcode -- ) 4 2 mnswap FMOVgen-encode ;
-
-: FPCR ( -- op0 op1 CRn CRm op2 ) 3 3 4 4 0 ;
-: FPSR ( -- op0 op1 CRn CRm op2 ) 3 3 4 4 1 ;
-
-: HLT ( uimm16 -- ) 16 ?ubits HLT-encode ;
-
-: LDRBr ( Rm Rn Rt -- ) [ 0 ] 2dip LDRBsr-encode ;
-: LDRBuoff ( uimm12 Rn Rt -- ) [ 12 ?ubits ] 2dip LDRBuoff-encode ;
-: LDRHuoff ( uimm13 Rn Rt -- ) [ 1 ?>> 12 ?ubits ] 2dip LDRHuoff-encode ;
-
-: MRS ( op0 op1 CRn CRm op2 Rt -- ) MRS-encode ;
-: MSRr ( op0 op1 CRn CRm op2 Rt -- ) MSRr-encode ;
-
-: NZCV ( -- op0 op1 CRn CRm op2 ) 3 3 4 2 0 ;
-
-: RET ( Rn/f -- ) X30 or RET-encode ;
-
-: SVC ( uimm16 -- ) 16 ?ubits SVC-encode ;
+++ /dev/null
-Doug Coleman
-Giftpflanze
+++ /dev/null
-Doug Coleman
-Giftpflanze
+++ /dev/null
-! Copyright (C) 2020 Doug Coleman.
-! See https://factorcode.org/license.txt for BSD license.
-USING: cpu.arm.assembler cpu.arm.assembler.opcodes make math
-math.bitwise tools.test ;
-IN: cpu.arm.assembler.opcodes.tests
-
-{ { 0x41 0x0 0x3 0x1a } } [ [ X3 X2 X1 ADC32-encode ] { } make ] unit-test
-{ { 0x41 0x0 0x3 0x3a } } [ [ X3 X2 X1 ADCS32-encode ] { } make ] unit-test
-{ { 0x41 0x0 0x3 0x5a } } [ [ X3 X2 X1 SBC32-encode ] { } make ] unit-test
-{ { 0x41 0x0 0x3 0x7a } } [ [ X3 X2 X1 SBCS32-encode ] { } make ] unit-test
-{ { 0x41 0x0 0x3 0x9a } } [ [ X3 X2 X1 ADC64-encode ] { } make ] unit-test
-{ { 0x41 0x0 0x3 0xba } } [ [ X3 X2 X1 ADCS64-encode ] { } make ] unit-test
-{ { 0x41 0x0 0x3 0xda } } [ [ X3 X2 X1 SBC64-encode ] { } make ] unit-test
-{ { 0x41 0x0 0x3 0xfa } } [ [ X3 X2 X1 SBCS64-encode ] { } make ] unit-test
-
-{ { 0xfd 0x03 0x00 0x91 } } [ [ 0 31 X29 MOVsp64-encode ] { } make ] unit-test
-
-! stp x29, x30, [sp, #-16]!
-{ { 0xfd 0x7b 0xbf 0xa9 } } [ [ -16 8 / 7 bits X30 SP X29 STPpre64-encode ] { } make ] unit-test
-
-{ { 0 0 0 0x10 } } [ [ 0 X0 ADR ] { } make ] unit-test
-{ { 0 0 0 0x30 } } [ [ 1 X0 ADR ] { } make ] unit-test
-
-{ { 0x90 0x20 0x00 0xb0 } } [ [ 0x411000 X16 ADRP ] { } make ] unit-test
+++ /dev/null
-! Copyright (C) 2020 Doug Coleman.
-! Copyright (C) 2023 Giftpflanze.
-! See https://factorcode.org/license.txt for BSD license.
-USING: accessors assocs classes.error classes.parser effects
-effects.parser endian kernel lexer make math math.bitwise
-math.parser multiline parser sequences vocabs.parser words
-words.symbol ;
-IN: cpu.arm.assembler.opcodes
-
-! https://developer.arm.com/documentation/ddi0487/latest/
-! https://static.docs.arm.com/ddi0487/fb/DDI0487F_b_armv8_arm.pdf ! initial work
-! https://static.docs.arm.com/ddi0487/fb/DDI0487G_a_armv8_arm.pdf ! 3/13/21
-
-<<
-SYNTAX: REGISTERS:
- ";"
- [
- create-word-in
- [ define-symbol ]
- [ dup name>> 1 tail string>number "ordinal" set-word-prop ] bi
- ] each-token ;
->>
-
-<<
-GENERIC: register ( obj -- n )
-M: word register "ordinal" word-prop ;
-M: integer register ;
-: error-word ( word -- new-class )
- name>> "-range" append create-class-in dup save-location
- tuple
- { "value" }
- [ define-error-class ] keepdd ;
-
-: make-checker-word ( word n -- )
- [ drop dup error-word ]
- [ nip swap '[ dup _ on-bits > [ _ execute( value -- * ) ] when ] ]
- [ 2drop ( n -- n ) ] 2tri
- define-declared ;
-
-SYNTAX: FIELD:
- scan-new-word scan-object
- [ "width" set-word-prop ] 2keep
- make-checker-word ;
-
-: make-register-checker-word ( word n -- )
- [ drop dup error-word '[ _ execute( value -- * ) ] ]
- [ nip swap '[ register dup _ on-bits > _ when ] ]
- [ 2drop ( n -- n ) ] 2tri
- define-declared ;
-
-SYNTAX: REGISTER-FIELD:
- scan-new-word scan-object
- [ "width" set-word-prop ] 2keep
- make-register-checker-word ;
->>
-
-<<
-FIELD: op1 1
-FIELD: op2 2
-FIELD: op3 3
-FIELD: op4 4
-FIELD: op5 5
-FIELD: op6 6
-FIELD: op7 7
-FIELD: op8 8
-FIELD: op9 9
-FIELD: op10 10
-
-FIELD: opc1 1
-FIELD: opc2 2
-FIELD: opc3 3
-FIELD: opc4 4
-
-FIELD: option1 1
-FIELD: option2 2
-FIELD: option3 3
-FIELD: option4 4
-FIELD: option5 5
-
-FIELD: a1 1
-FIELD: b1 1
-FIELD: c1 1
-FIELD: d1 1
-FIELD: e1 1
-FIELD: f1 1
-FIELD: g1 1
-FIELD: h1 1
-
-FIELD: A 1
-FIELD: D 1
-FIELD: L 1
-FIELD: M 1
-FIELD: N 1
-FIELD: Q 1
-FIELD: S 1
-FIELD: U 1
-FIELD: Z 1
-
-FIELD: sf 1
-FIELD: ftype 2
-FIELD: rmode 2
-
-FIELD: size1 1
-FIELD: size2 2
-
-FIELD: shift2 2
-
-FIELD: b40 5
-
-FIELD: immr 6
-FIELD: imms 6
-FIELD: immrimms 12
-FIELD: Nimmrimms 13
-FIELD: imm3 3
-FIELD: imm4 4
-FIELD: imm5 5
-FIELD: imm6 6
-FIELD: imm7 7
-FIELD: imm9 9
-FIELD: imm12 12
-FIELD: imm13 13
-FIELD: imm14 14
-FIELD: imm16 16
-FIELD: imm19 19
-FIELD: imm26 26
-
-FIELD: simm7 7
-FIELD: uimm4 4
-FIELD: uimm6 6
-
-FIELD: immlo2 2
-FIELD: immhi19 19
-
-FIELD: cond4 4
-FIELD: CRm 4
-FIELD: CRn 4
-FIELD: nzcv 4
-FIELD: hw2 2
-FIELD: mask4 4
-
-REGISTER-FIELD: Ra 5
-REGISTER-FIELD: Rm 5
-REGISTER-FIELD: Rn 5
-REGISTER-FIELD: Rd 5
-REGISTER-FIELD: Rs 5
-REGISTER-FIELD: Rt 5
-REGISTER-FIELD: Rt2 5
-REGISTER-FIELD: Xd 5
-REGISTER-FIELD: Xm 5
-REGISTER-FIELD: Xn 5
-REGISTER-FIELD: Xt 5
-REGISTER-FIELD: Xt2 5
-
-! General purpose registers, 64bit
-REGISTERS: X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12
-X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25
-X26 X27 X28 X29 X30 ;
-
-! Lower registers, shared with X0..X30, 32bit
-REGISTERS: W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12
-W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 W25
-W26 W27 W28 W29 W30 ;
-
-! https://static.docs.arm.com/ddi0487/fb/DDI0487F_b_armv8_arm.pdf pgA1-42
-! Neon registers (SIMD Scalar) Q/D/S/H/B 128/64/32/16/8 bits
-REGISTERS: V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12
-V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 V25
-V26 V27 V28 V29 V30 V31 ;
-
-REGISTERS: B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12
-B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25
-B26 B27 B28 B29 B30 B31 ;
-
-REGISTERS: H0 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12
-H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25
-H26 H27 H28 H29 H30 H31 ;
-
-REGISTERS: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12
-S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25
-S26 S27 S28 S29 S30 S31 ;
-
-REGISTERS: D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12
-D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25
-D26 D27 D28 D29 D30 D31 ;
-
-REGISTERS: Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12
-Q13 Q14 Q15 Q16 Q17 Q18 Q19 Q20 Q21 Q22 Q23 Q24 Q25
-Q26 Q27 Q28 Q29 Q30 Q31 ;
-
-CONSTANT: SP 31
-CONSTANT: WSP 31
-CONSTANT: WZR 31
-CONSTANT: XZR 31
-
-! Zero/discard register 31, ZR WZR XZR - reads 0 always, writes to it succeed
-! Stack Pointer register 31 WSP SP
-! SINGLETONS: WZR XZR ; ! alias for register 31
-! SINGLETONS: WSP SP ; ! alias for register 31 which does not exist
-! Rn - register
-
-! PSTATE EL0: NZCV, DAIF,
-
-! EL - exception level. application 0, OS (priv) 1, hypervisor 2, low-level 3
-
-! Stack Pointer EL0 is 64bit, rest are 32bit
-SINGLETONS: SP_EL0 SP_EL1 SP_EL2 SP_EL3 ;
-
-! Exception link registers, 64bit
-SINGLETONS: ELR_EL1 ELR_EL2 ELR_EL3 ;
-
-! Saved program status registers, exception level, 64bit
-SINGLETONS: SPSR_EL1 SPSR_EL2 SPSR_EL3 ;
-
-! Program counter, 64bit
-! SINGLETONS: PC ; ! not accessible (?)
-
-! Flags: N negative, Z zero, C carry, V overflow, SS software step, IL illegal execution
-! D debug, A SError system error, I IRQ normal interrupt, F FIQ fast interrupt
-
-! Distinct L1 I-cache (instruction) and D-cache (data), unified L2 cache
-! 4kb page size alignment, unaligned accepted
-
-! PCS Procedure Call Standard X0-X7 parameters/results registers
-! X9-X15 caller-saved temp regs (use)
-! X19-X29 callee-saved (preserved)
-! X8 indirect result register, syscalls register
-! X16 X17 are IP0 and IP1, intra-procedure temp regs (avoid)
-! X18 platform-register (avoid)
-! X29 FP frame pointer register (avoid)
-! X30 LR link register (avoid)
-
-![[
-(bits(N), bit) LSL_C(bits(N) x, integer shift)
- assert shift > 0;
- shift = if shift > N then N else shift;
- extended_x = x : Zeros(shift);
- result = extended_x<N-1:0>;
- carry_out = extended_x<N>;
- return (result, carry_out);
-]]
-
-! Instructions
-
-! https://community.element14.com/products/devtools/technicallibrary/m/files/10863
-! pg 16
-! cond code set in previous arm assembly instruction
-: EQ ( -- n ) 0b0000 ; inline ! Z set: equal
-: NE ( -- n ) 0b0001 ; inline ! Z clear: not equal
-: CS ( -- n ) 0b0010 ; inline ! C set: unsigned higher or same
-: HS ( -- n ) 0b0010 ; inline !
-: CC ( -- n ) 0b0011 ; inline ! C clear: unsigned lower
-: LO ( -- n ) 0b0011 ; inline !
-: MI ( -- n ) 0b0100 ; inline ! N set: negative
-: PL ( -- n ) 0b0101 ; inline ! N clear: positive or zero
-: VS ( -- n ) 0b0110 ; inline ! V set: overflow
-: VC ( -- n ) 0b0111 ; inline ! V clear: no overflow
-: HI ( -- n ) 0b1000 ; inline ! C set and Z clear: unsigned higher
-: LS ( -- n ) 0b1001 ; inline ! C clear or Z set: unsigned lower or same
-: GE ( -- n ) 0b1010 ; inline ! N equals V: greater or equal
-: LT ( -- n ) 0b1011 ; inline ! N not equal to V: less than
-: GT ( -- n ) 0b1100 ; inline ! Z clear AND (N equals V): greater than
-: LE ( -- n ) 0b1101 ; inline ! Z set OR (N not equal to V): less than or equal
-: AL ( -- n ) 0b1110 ; inline ! always
-: NV ( -- n ) 0b1111 ; inline ! always
-
-! Arrangement specifiers
-
-: 8B ( -- size Q ) 0 0 ; inline
-: 16B ( -- size Q ) 0 1 ; inline
-: 4H ( -- size Q ) 1 0 ; inline
-: 8H ( -- size Q ) 1 1 ; inline
-: 2S ( -- size Q ) 2 0 ; inline
-: 4S ( -- size Q ) 2 1 ; inline
-: 2D ( -- size Q ) 3 1 ; inline
-
-! FMOVgen variants
-
-: HW ( -- sf ftype rmode opcode ) 0 3 0 6 ; inline
-: HX ( -- sf ftype rmode opcode ) 1 3 0 6 ; inline
-: WH ( -- sf ftype rmode opcode ) 0 3 0 7 ; inline
-: WS ( -- sf ftype rmode opcode ) 0 0 0 7 ; inline
-: SW ( -- sf ftype rmode opcode ) 0 0 0 6 ; inline
-: XH ( -- sf ftype rmode opcode ) 1 3 0 7 ; inline
-: XD ( -- sf ftype rmode opcode ) 1 1 0 7 ; inline
-: XD[1] ( -- sf ftype rmode opcode ) 1 2 0 7 ; inline
-: DX ( -- sf ftype rmode opcode ) 1 1 0 6 ; inline
-: D[1]X ( -- sf ftype rmode opcode ) 1 2 0 6 ; inline
-
-
-ERROR: no-field-word vocab name ;
-
-TUPLE: integer-literal value width ;
-C: <integer-literal> integer-literal
-
-! handle 1xx0 where x = dontcare
-: make-integer-literal ( string -- integer-literal )
- [ "0b" prepend { { CHAR: x CHAR: 0 } } substitute string>number ]
- [ length ] bi <integer-literal> ;
-
-: ?lookup-word ( name vocab -- word )
- 2dup lookup-word
- [ 2nip ]
- [ over [ "01x" member? ] all? [ drop make-integer-literal ] [ no-field-word ] if ] if* ;
-
-GENERIC: width ( obj -- n )
-M: word width "width" word-prop ;
-M: integer-literal width width>> ;
-
-GENERIC: value ( obj -- n )
-M: integer-literal value value>> ;
-M: object value ;
-
-: arm-bitfield ( seq -- assoc )
- [ current-vocab name>> ?lookup-word ] map
- [ dup width ] map>alist
- dup values [ f = ] any? [ throw ] when ;
-
-ERROR: bad-instruction values ;
->>
-
-<<
-SYNTAX: ARM-INSTRUCTION:
- scan-new-word
- scan-effect
- [
- in>> arm-bitfield
- [ keys [ value ] map ]
- [ values 32 [ - ] accumulate* ] bi zip
- dup last second 0 = [ bad-instruction ] unless
- '[ _ bitfield* 4 >le % ]
- ] [ in>> [ string>number ] reject { } <effect> ] bi define-declared ;
->>
-
-! ADC: Add with Carry.
-! ADCS: Add with Carry, setting flags.
-ARM-INSTRUCTION: ADC32-encode ( 0 0 0 11010000 Rm 000000 Rn Rd -- )
-ARM-INSTRUCTION: ADCS32-encode ( 0 0 1 11010000 Rm 000000 Rn Rd -- )
-ARM-INSTRUCTION: ADC64-encode ( 1 0 0 11010000 Rm 000000 Rn Rd -- )
-ARM-INSTRUCTION: ADCS64-encode ( 1 0 1 11010000 Rm 000000 Rn Rd -- )
-
-! ADD (extended register): Add (extended register).
-ARM-INSTRUCTION: ADDer32-encode ( 0 0 0 01011 00 1 Rm option3 imm3 Rn Rd -- )
-ARM-INSTRUCTION: ADDer64-encode ( 1 0 0 01011 00 1 Rm option3 imm3 Rn Rd -- )
-
-! ADD (immediate): Add (immediate).
-ARM-INSTRUCTION: ADDi32-encode ( 0 0 0 10001 shift2 imm12 Rn Rd -- )
-ARM-INSTRUCTION: ADDi64-encode ( 1 0 0 10001 shift2 imm12 Rn Rd -- )
-
-! ADD (shifted register): Add (shifted register).
-ARM-INSTRUCTION: ADDsr32-encode ( 0 0 0 01011 shift2 0 Rm imm6 Rn Rd -- )
-ARM-INSTRUCTION: ADDsr64-encode ( 1 0 0 01011 shift2 0 Rm imm6 Rn Rd -- )
-
-! ADDG: Add with Tag.
-ARM-INSTRUCTION: ADDG-encode ( 1 0 0 100011 0 uimm6 00 uimm4 Xn Xd -- )
-
-! ADDS (extended register): Add (extended register), setting flags.
-ARM-INSTRUCTION: ADDSer32-encode ( 0 0 1 01011 00 1 Rm option3 imm3 Rn Rd -- )
-ARM-INSTRUCTION: ADDSer64-encode ( 1 0 1 01011 00 1 Rm option3 imm3 Rn Rd -- )
-
-! ADDS (immediate): Add (immediate), setting flags.
-ARM-INSTRUCTION: ADDSi32-encode ( 0 0 1 10001 shift2 imm12 Rn Rd -- )
-ARM-INSTRUCTION: ADDSi64-encode ( 1 0 1 10001 shift2 imm12 Rn Rd -- )
-
-! ADDS (shifted register): Add (shifted register), setting flags.
-ARM-INSTRUCTION: ADDSsr32-encode ( 0 0 1 01011 shift2 0 Rm imm6 Rn Rd -- )
-ARM-INSTRUCTION: ADDSsr64-encode ( 1 0 1 01011 shift2 0 Rm imm6 Rn Rd -- )
-
-! ADDV: Add across Vector.
-ARM-INSTRUCTION: ADDV-encode ( 0 Q 0 01110 size2 11000 11011 10 Rn Rd -- )
-
-! ADR: Form PC-relative address.
-! ADRP: Form PC-relative address to 4KB page.
-ARM-INSTRUCTION: ADR-encode ( 0 immlo2 10000 immhi19 Rd -- )
-ARM-INSTRUCTION: ADRP-encode ( 1 immlo2 10000 immhi19 Rd -- )
-
-! AND (immediate): Bitwise AND (immediate).
-ARM-INSTRUCTION: ANDi32-encode ( 0 00 100100 0 immrimms Rn Rd -- )
-ARM-INSTRUCTION: ANDi64-encode ( 1 00 100100 Nimmrimms Rn Rd -- )
-
-! AND (shifted register): Bitwise AND (shifted register).
-ARM-INSTRUCTION: ANDsr32-encode ( 0 00 01010 shift2 0 Rm imm6 Rn Rd -- )
-ARM-INSTRUCTION: ANDsr64-encode ( 1 00 01010 shift2 0 Rm imm6 Rn Rd -- )
-
-! ANDS (immediate): Bitwise AND (immediate), setting flags.
-ARM-INSTRUCTION: ANDSi32-encode ( 0 11 100100 0 immrimms Rn Rd -- )
-ARM-INSTRUCTION: ANDSi64-encode ( 1 11 100100 Nimmrimms Rn Rd -- )
-
-! ANDS (shifted register): Bitwise AND (shifted register), setting flags.
-ARM-INSTRUCTION: ANDSsr32-encode ( 0 11 01010 shift2 0 Rm imm6 Rn Rd -- )
-ARM-INSTRUCTION: ANDSsr64-encode ( 1 11 01010 shift2 0 Rm imm6 Rn Rd -- )
-
-! ASR (immediate): Arithmetic Shift Right (immediate): an alias of SBFM.
-ARM-INSTRUCTION: ASRi32-encode ( 0 00 100110 0 immr 011111 Rn Rd -- )
-ARM-INSTRUCTION: ASRi64-encode ( 1 00 100110 1 immr 111111 Rn Rd -- )
-
-! ASR (register): Arithmetic Shift Right (register): an alias of ASRV.
-ARM-INSTRUCTION: ASRr32-encode ( 0 0 0 11010110 Rm 0010 10 Rn Rd -- )
-ARM-INSTRUCTION: ASRr64-encode ( 1 0 0 11010110 Rm 0010 10 Rn Rd -- )
-
-! ASRV: Arithmetic Shift Right Variable.
-ARM-INSTRUCTION: ASRV32-encode ( 0 0 0 11010110 Rm 0010 10 Rn Rd -- )
-ARM-INSTRUCTION: ASRV64-encode ( 1 0 0 11010110 Rm 0010 10 Rn Rd -- )
-
-! AT: Address Translate: an alias of SYS.
-ARM-INSTRUCTION: AT-encode ( 1101010100 0 01 op3 0111 1000 op3 Rt -- )
-
-! AUTDA, AUTDZA: Authenticate Data address, using key A.
-! AUTDB, AUTDZB: Authenticate Data address, using key B.
-ARM-INSTRUCTION: AUTDA-encode ( 1 1 0 11010110 00001 0 0 0 110 Rn Rd -- )
-ARM-INSTRUCTION: AUTDZA-encode ( 1 1 0 11010110 00001 0 0 1 110 11111 Rd -- )
-ARM-INSTRUCTION: AUTDB-encode ( 1 1 0 11010110 00001 0 0 0 111 Rn Rd -- )
-ARM-INSTRUCTION: AUTDZB-encode ( 1 1 0 11010110 00001 0 0 1 111 11111 Rd -- )
-
-! AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZA: Authenticate Instruction address, using key A.
-! ARMv8.3
-ARM-INSTRUCTION: AUTIA-encode ( 1 1 0 11010110 00001 0 0 0 100 Rn Rd -- )
-ARM-INSTRUCTION: AUTIZA-encode ( 1 1 0 11010110 00001 0 0 1 100 11111 Rd -- )
-! ARMv8.3
-ARM-INSTRUCTION: AUTIA1716-encode ( 1101010100 0 00 011 0010 0001 100 11111 -- )
-ARM-INSTRUCTION: AUTIASP-encode ( 1101010100 0 00 011 0010 0011 101 11111 -- )
-ARM-INSTRUCTION: AUTIAAZ-encode ( 1101010100 0 00 011 0010 0011 100 11111 -- )
-
-! AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZB: Authenticate Instruction address, using key B.
-! ARMv8.3
-ARM-INSTRUCTION: AUTIB-encode ( 1 1 0 11010110 00001 0 0 0 101 Rn Rd -- )
-ARM-INSTRUCTION: AUTIZB-encode ( 1 1 0 11010110 00001 0 0 1 101 11111 Rd -- )
-! ARMv8.3
-ARM-INSTRUCTION: AUTIB1716-encode ( 1101010100 0 00 011 0010 0001 110 11111 -- )
-ARM-INSTRUCTION: AUTIBSP-encode ( 1101010100 0 00 011 0010 0011 111 11111 -- )
-ARM-INSTRUCTION: AUTIBZ-encode ( 1101010100 0 00 011 0010 0011 110 11111 -- )
-
-! AXFlag: Convert floating-point condition flags from ARM to external format.
-ARM-INSTRUCTION: AXFlag-encode ( 1101010100 0 00 000 0100 0000 010 11111 -- )
-
-! B: Branch.
-ARM-INSTRUCTION: B-encode ( 0 00101 imm26 -- )
-
-! B.cond: Branch conditionally.
-ARM-INSTRUCTION: B.cond-encode ( 0101010 0 imm19 0 cond4 -- )
-
-! BFC: Bitfield Clear: an alias of BFM.
-ARM-INSTRUCTION: BFC32-encode ( 0 01 100110 0 immrimms 11111 Rd -- )
-ARM-INSTRUCTION: BFC64-encode ( 1 01 100110 Nimmrimms 11111 Rd -- )
-
-! BFI: Bitfield Insert: an alias of BFM.
-ARM-INSTRUCTION: BFI32-encode ( 0 01 100110 0 immrimms Rn Rd -- )
-ARM-INSTRUCTION: BFI64-encode ( 1 01 100110 Nimmrimms Rn Rd -- )
-
-! BFM: Bitfield Move.
-ARM-INSTRUCTION: BFM32-encode ( 0 01 100110 0 immrimms Rn Rd -- )
-ARM-INSTRUCTION: BFM64-encode ( 1 01 100110 Nimmrimms Rn Rd -- )
-
-! BFXIL: Bitfield extract and insert at low end: an alias of BFM.
-ARM-INSTRUCTION: BFXIL32-encode ( 0 01 100110 0 immrimms Rn Rd -- )
-ARM-INSTRUCTION: BFXIL64-encode ( 1 01 100110 Nimmrimms Rn Rd -- )
-
-! BIC (shifted register): Bitwise Bit Clear (shifted register).
-ARM-INSTRUCTION: BIC32-encode ( 0 00 01010 shift2 1 Rm imm6 Rn Rd -- )
-ARM-INSTRUCTION: BIC64-encode ( 1 00 01010 shift2 1 Rm imm6 Rn Rd -- )
-! BICS (shifted register): Bitwise Bit Clear (shifted register), setting flags.
-ARM-INSTRUCTION: BICS32-encode ( 0 11 01010 shift2 1 Rm imm6 Rn Rd -- )
-ARM-INSTRUCTION: BICS64-encode ( 1 11 01010 shift2 1 Rm imm6 Rn Rd -- )
-
-! BL: Branch with Link.
-ARM-INSTRUCTION: BL-encode ( 1 00101 imm26 -- )
-! BLR: Branch with Link to Register.
-ARM-INSTRUCTION: BLR-encode ( 1101011 0 0 01 11111 0000 0 0 Rn 00000 -- )
-
-! BLRAA, BLRAAZ, BLRAB, BLRABZ: Branch with Link to Register, with pointer authentication.
-ARM-INSTRUCTION: BLRAA-encode ( 1101011 0 0 01 11111 0000 1 0 Rn Rm -- )
-ARM-INSTRUCTION: BLRAAZ-encode ( 1101011 1 0 01 11111 0000 1 0 Rn 11111 -- )
-ARM-INSTRUCTION: BLRAB-encode ( 1101011 0 0 01 11111 0000 1 1 Rn Rm -- )
-ARM-INSTRUCTION: BLRABZ-encode ( 1101011 1 0 01 11111 0000 1 1 Rn 11111 -- )
-
-! BR: Branch to Register.
-ARM-INSTRUCTION: BR-encode ( 1101011 0 0 00 11111 0000 0 0 Rn 00000 -- )
-
-! BRAA, BRAAZ, BRAB, BRABZ: Branch to Register, with pointer authentication.
-ARM-INSTRUCTION: BRAA-encode ( 1101011 0 0 00 11111 0000 1 0 Rn 11111 -- )
-ARM-INSTRUCTION: BRAAZ-encode ( 1101011 1 0 00 11111 0000 1 0 Rn Rm -- )
-ARM-INSTRUCTION: BRAB-encode ( 1101011 0 0 00 11111 0000 1 1 Rn 11111 -- )
-ARM-INSTRUCTION: BRABZ-encode ( 1101011 1 0 00 11111 0000 1 1 Rn Rm -- )
-
-! BRK: Breakpoint instruction.
-ARM-INSTRUCTION: BRK-encode ( 11010100 001 imm16 000 00 -- )
-
-! BTI: Branch Target Identification.
-ARM-INSTRUCTION: BTI-encode ( 1101010100 0 00 011 0010 0100 000 11111 -- )
-
-! CAS, CASA, CASAL, CASL: Compare and Swap word or doubleword in memory.
-ARM-INSTRUCTION: CAS32-encode ( 10 001000 1 0 1 Rs 0 11111 Rn Rt -- )
-ARM-INSTRUCTION: CASA32-encode ( 10 001000 1 1 1 Rs 0 11111 Rn Rt -- )
-ARM-INSTRUCTION: CASAL32-encode ( 10 001000 1 1 1 Rs 1 11111 Rn Rt -- )
-ARM-INSTRUCTION: CASL32-encode ( 10 001000 1 0 1 Rs 1 11111 Rn Rt -- )
-ARM-INSTRUCTION: CAS64-encode ( 11 001000 1 0 1 Rs 0 11111 Rn Rt -- )
-ARM-INSTRUCTION: CASA64-encode ( 11 001000 1 1 1 Rs 0 11111 Rn Rt -- )
-ARM-INSTRUCTION: CASAL64-encode ( 11 001000 1 1 1 Rs 1 11111 Rn Rt -- )
-ARM-INSTRUCTION: CASL64-encode ( 11 001000 1 0 1 Rs 1 11111 Rn Rt -- )
-
-! CASB, CASAB, CASALB, CASLB: Compare and Swap byte in memory.
-ARM-INSTRUCTION: CASAB-encode ( 00 001000 1 1 1 Rs 0 11111 Rn Rt -- )
-ARM-INSTRUCTION: CASALB-encode ( 00 001000 1 1 1 Rs 1 11111 Rn Rt -- )
-ARM-INSTRUCTION: CASB-encode ( 00 001000 1 0 1 Rs 0 11111 Rn Rt -- )
-ARM-INSTRUCTION: CASLB-encode ( 00 001000 1 0 1 Rs 1 11111 Rn Rt -- )
-
-! CASH, CASAH, CASALH, CASLH: Compare and Swap halfword in memory.
-ARM-INSTRUCTION: CASAH-encode ( 01 001000 1 1 1 Rs 0 11111 Rn Rt -- )
-ARM-INSTRUCTION: CASALH-encode ( 01 001000 1 1 1 Rs 1 11111 Rn Rt -- )
-ARM-INSTRUCTION: CASH-encode ( 01 001000 1 0 1 Rs 0 11111 Rn Rt -- )
-ARM-INSTRUCTION: CASLH-encode ( 01 001000 1 0 1 Rs 1 11111 Rn Rt -- )
-
-! CASP, CASPA, CASPAL, CASPL: Compare and Swap Pair of words or doublewords in memory.
-ARM-INSTRUCTION: CASP32-encode ( 0 0 001000 0 0 1 Rs 0 11111 Rn Rt -- )
-ARM-INSTRUCTION: CASPA32-encode ( 0 0 001000 0 1 1 Rs 0 11111 Rn Rt -- )
-ARM-INSTRUCTION: CASPAL32-encode ( 0 0 001000 0 1 1 Rs 1 11111 Rn Rt -- )
-ARM-INSTRUCTION: CASPL32-encode ( 0 0 001000 0 0 1 Rs 1 11111 Rn Rt -- )
-ARM-INSTRUCTION: CASP64-encode ( 0 1 001000 0 0 1 Rs 0 11111 Rn Rt -- )
-ARM-INSTRUCTION: CASPA64-encode ( 0 1 001000 0 1 1 Rs 0 11111 Rn Rt -- )
-ARM-INSTRUCTION: CASPAL64-encode ( 0 1 001000 0 1 1 Rs 1 11111 Rn Rt -- )
-ARM-INSTRUCTION: CASPL64-encode ( 0 1 001000 0 0 1 Rs 1 11111 Rn Rt -- )
-
-! CBNZ: Compare and Branch on Nonzero.
-ARM-INSTRUCTION: CBNZ32-encode ( 0 011010 1 imm19 Rt -- )
-ARM-INSTRUCTION: CBNZ64-encode ( 1 011010 1 imm19 Rt -- )
-
-! CBZ: Compare and Branch on Zero.
-ARM-INSTRUCTION: CBZ32-encode ( 0 011010 0 imm19 Rt -- )
-ARM-INSTRUCTION: CBZ64-encode ( 1 011010 0 imm19 Rt -- )
-
-! CCMN (immediate): Conditional Compare Negative (immediate).
-ARM-INSTRUCTION: CCMNi32-encode ( 0 0 1 11010010 imm5 cond4 1 0 Rn 0 nzcv -- )
-ARM-INSTRUCTION: CCMNi64-encode ( 1 0 1 11010010 imm5 cond4 1 0 Rn 0 nzcv -- )
-! CCMN (register): Conditional Compare Negative (register).
-ARM-INSTRUCTION: CCMNr32-encode ( 0 0 1 11010010 Rm cond4 0 0 Rn 0 nzcv -- )
-ARM-INSTRUCTION: CCMNr64-encode ( 1 0 1 11010010 Rm cond4 0 0 Rn 0 nzcv -- )
-! CCMP (immediate): Conditional Compare (immediate).
-ARM-INSTRUCTION: CCMPi32-encode ( 0 1 1 11010010 imm5 cond4 1 0 Rn 0 nzcv -- )
-ARM-INSTRUCTION: CCMPi64-encode ( 1 1 1 11010010 imm5 cond4 1 0 Rn 0 nzcv -- )
-! CCMP (register): Conditional Compare (register).
-ARM-INSTRUCTION: CCMPr32-encode ( 0 1 1 11010010 Rm cond4 0 0 Rn 0 nzcv -- )
-ARM-INSTRUCTION: CCMPr64-encode ( 1 1 1 11010010 Rm cond4 0 0 Rn 0 nzcv -- )
-
-! CFINV: Invert Carry Flag.
-ARM-INSTRUCTION: CFINV-encode ( 1101010100 0 0 0 000 0100 0000 000 11111 -- )
-
-! CFP: Control Flow Prediction Restriction by Context: an alias of SYS.
-ARM-INSTRUCTION: CFP-encode ( 1101010100 0 01 011 0111 0011 100 Rt -- )
-
-! CINC: Conditional Increment: an alias of CSINC.
-ARM-INSTRUCTION: CINC32-encode ( 0 0 0 11010100 Rm cond4 0 1 Rn Rd -- )
-ARM-INSTRUCTION: CINC64-encode ( 1 0 0 11010100 Rm cond4 0 1 Rn Rd -- )
-
-! CINV: Conditional Invert: an alias of CSINV.
-ARM-INSTRUCTION: CINV32-encode ( 0 0 0 11010100 Rm cond4 0 0 Rn Rd -- )
-ARM-INSTRUCTION: CINV64-encode ( 1 0 0 11010100 Rm cond4 0 0 Rn Rd -- )
-
-! CLREX: Clear Exclusive.
-ARM-INSTRUCTION: CLREX-encode ( 1101010100 0 00 011 0011 CRm 010 11111 -- )
-
-! CLS: Count Leading Sign bits.
-ARM-INSTRUCTION: CLS32-encode ( 0 1 0 11010110 00000 00010 1 Rn Rd -- )
-ARM-INSTRUCTION: CLS64-encode ( 1 1 0 11010110 00000 00010 1 Rn Rd -- )
-! CLZ: Count Leading Zeros.
-ARM-INSTRUCTION: CLZ32-encode ( 0 1 0 11010110 00000 00010 0 Rn Rd -- )
-ARM-INSTRUCTION: CLZ64-encode ( 1 1 0 11010110 00000 00010 0 Rn Rd -- )
-
-! CMN (extended register): Compare Negative (extended register): an alias of ADDS (extended register).
-ARM-INSTRUCTION: CMNer32-encode ( 0 0 1 01011 00 1 Rm option3 imm3 Rn Rd -- )
-ARM-INSTRUCTION: CMNer64-encode ( 1 0 1 01011 00 1 Rm option3 imm3 Rn Rd -- )
-! CMN (immediate): Compare Negative (immediate): an alias of ADDS (immediate).
-ARM-INSTRUCTION: CMNi32-encode ( 0 0 1 10001 shift2 imm12 Rn 11111 -- )
-ARM-INSTRUCTION: CMNi64-encode ( 1 0 1 10001 shift2 imm12 Rn 11111 -- )
-! CMN (shifted register): Compare Negative (shifted register): an alias of ADDS (shifted register).
-ARM-INSTRUCTION: CMNsr32-encode ( 0 0 1 01011 shift2 0 Rm imm6 Rn 11111 -- )
-ARM-INSTRUCTION: CMNsr64-encode ( 1 0 1 01011 shift2 0 Rm imm6 Rn 11111 -- )
-
-! CMP (extended register): Compare (extended register): an alias of SUBS (extended register).
-ARM-INSTRUCTION: CMPer32-encode ( 0 1 1 01011 00 1 Rm option3 imm3 Rn 11111 -- )
-ARM-INSTRUCTION: CMPer64-encode ( 1 1 1 01011 00 1 Rm option3 imm3 Rn 11111 -- )
-! CMP (immediate): Compare (immediate): an alias of SUBS (immediate).
-ARM-INSTRUCTION: CMPi32-encode ( 0 1 1 10001 shift2 imm12 Rn 11111 -- )
-ARM-INSTRUCTION: CMPi64-encode ( 1 1 1 10001 shift2 imm12 Rn 11111 -- )
-! CMP (shifted register): Compare (shifted register): an alias of SUBS (shifted register).
-ARM-INSTRUCTION: CMPsr32-encode ( 0 1 1 01011 shift2 0 Rm imm6 Rn Rd -- )
-ARM-INSTRUCTION: CMPsr64-encode ( 1 1 1 01011 shift2 0 Rm imm6 Rn Rd -- )
-
-! CMPP: Compare with Tag: an alias of SUBPS.
-ARM-INSTRUCTION: CMPP-encode ( 1 0 1 11010110 Xm 0 0 0 0 0 0 Xn Xd -- )
-
-! CNEG: Conditional Negate: an alias of CSNEG.
-ARM-INSTRUCTION: CNEG32-encode ( 0 1 0 11010100 Rm cond4 0 1 Rn Rd -- )
-ARM-INSTRUCTION: CNEG64-encode ( 1 1 0 11010100 Rm cond4 0 1 Rn Rd -- )
-
-! CNT: Population Count per byte.
-ARM-INSTRUCTION: CNT-encode ( 0 Q 0 01110 size2 10000 00101 10 Rn Rd -- )
-
-! CPP: Cache Prefetch Prediction Restriction by Context: an alias of SYS.
-ARM-INSTRUCTION: CPP-encode ( 1101010100 0 01 011 0111 0011 111 Rt -- )
-
-! CRC32B, CRC32H, CRC32W, CRC32X: CRC32 checksum.
-ARM-INSTRUCTION: CRC32B32-encode ( 0 0 0 11010110 Rm 010 0 00 Rn Rd -- )
-ARM-INSTRUCTION: CRC32B64-encode ( 1 0 0 11010110 Rm 010 0 00 Rn Rd -- )
-ARM-INSTRUCTION: CRC32H32-encode ( 0 0 0 11010110 Rm 010 0 01 Rn Rd -- )
-ARM-INSTRUCTION: CRC32H64-encode ( 1 0 0 11010110 Rm 010 0 01 Rn Rd -- )
-ARM-INSTRUCTION: CRC32W32-encode ( 0 0 0 11010110 Rm 010 0 10 Rn Rd -- )
-ARM-INSTRUCTION: CRC32W64-encode ( 1 0 0 11010110 Rm 010 0 10 Rn Rd -- )
-ARM-INSTRUCTION: CRC32X32-encode ( 0 0 0 11010110 Rm 010 0 11 Rn Rd -- )
-ARM-INSTRUCTION: CRC32X64-encode ( 1 0 0 11010110 Rm 010 0 11 Rn Rd -- )
-
-! CRC32CB, CRC32CH, CRC32CW, CRC32CX: CRC32C checksum.
-ARM-INSTRUCTION: CRC32CB32-encode ( 0 0 0 11010110 Rm 010 1 00 Rn Rd -- )
-ARM-INSTRUCTION: CRC32CB64-encode ( 1 0 0 11010110 Rm 010 1 00 Rn Rd -- )
-ARM-INSTRUCTION: CRC32CH32-encode ( 0 0 0 11010110 Rm 010 1 01 Rn Rd -- )
-ARM-INSTRUCTION: CRC32CH64-encode ( 1 0 0 11010110 Rm 010 1 01 Rn Rd -- )
-ARM-INSTRUCTION: CRC32CW32-encode ( 0 0 0 11010110 Rm 010 1 10 Rn Rd -- )
-ARM-INSTRUCTION: CRC32CW64-encode ( 1 0 0 11010110 Rm 010 1 10 Rn Rd -- )
-ARM-INSTRUCTION: CRC32CX32-encode ( 0 0 0 11010110 Rm 010 1 11 Rn Rd -- )
-ARM-INSTRUCTION: CRC32CX64-encode ( 1 0 0 11010110 Rm 010 1 11 Rn Rd -- )
-
-! CSDB: Consumption of Speculative Data Barrier.
-ARM-INSTRUCTION: CSDB-encode ( 1101010100 0 00 011 0010 0010 100 11111 -- )
-! CSEL: Conditional Select.
-ARM-INSTRUCTION: CSEL32-encode ( 0 0 0 11010100 Rm cond4 0 0 Rn Rd -- )
-ARM-INSTRUCTION: CSEL64-encode ( 1 0 0 11010100 Rm cond4 0 0 Rn Rd -- )
-! CSET: Conditional Set: an alias of CSINC.
-ARM-INSTRUCTION: CSET32-encode ( 0 0 0 11010100 11111 cond4 0 1 11111 Rd -- )
-ARM-INSTRUCTION: CSET64-encode ( 1 0 0 11010100 11111 cond4 0 1 11111 Rd -- )
-! CSETM: Conditional Set Mask: an alias of CSINV.
-ARM-INSTRUCTION: CSETM32-encode ( 0 0 0 11010100 11111 cond4 0 0 11111 Rd -- )
-ARM-INSTRUCTION: CSETM64-encode ( 1 0 0 11010100 11111 cond4 0 0 11111 Rd -- )
-
-! CSINC: Conditional Select Increment.
-ARM-INSTRUCTION: CSINC32-encode ( 0 0 0 11010100 Rm cond4 0 1 Rn Rd -- )
-ARM-INSTRUCTION: CSINC64-encode ( 1 0 0 11010100 Rm cond4 0 1 Rn Rd -- )
-
-! CSINV: Conditional Select Invert.
-ARM-INSTRUCTION: CSINV32-encode ( 0 0 0 11010100 Rm cond4 0 0 Rn Rd -- )
-ARM-INSTRUCTION: CSINV64-encode ( 1 0 0 11010100 Rm cond4 0 0 Rn Rd -- )
-
-! CSNEG: Conditional Select Negation.
-ARM-INSTRUCTION: CSNEG32-encode ( 0 1 0 11010100 Rm cond4 0 1 Rn Rd -- )
-ARM-INSTRUCTION: CSNEG64-encode ( 1 1 0 11010100 Rm cond4 0 1 Rn Rd -- )
-
-! DC: Data Cache operation: an alias of SYS.
-ARM-INSTRUCTION: DC-encode ( 1101010100 0 01 op3 0111 CRm op3 Rt -- )
-
-! DCPS1: Debug Change PE State to EL1..
-ARM-INSTRUCTION: DCPS1-encode ( 11010100 101 imm16 000 01 -- )
-! DCPS2: Debug Change PE State to EL2..
-ARM-INSTRUCTION: DCPS2-encode ( 11010100 101 imm16 000 10 -- )
-! DCPS3: Debug Change PE State to EL3.
-ARM-INSTRUCTION: DCPS3-encode ( 11010100 101 imm16 000 11 -- )
-
-! DMB: Data Memory Barrier.
-ARM-INSTRUCTION: DMB-encode ( 1101010100 0 00 011 0011 CRm 1 01 11111 -- )
-
-! DRPS: Debug restore process state.
-ARM-INSTRUCTION: DPRS-encode ( 1101011 0101 11111 000000 11111 00000 -- )
-
-! DSB: Data Synchronization Barrier.
-ARM-INSTRUCTION: DSB-encode ( 1101010100 0 00 011 0011 CRm 1 00 11111 -- )
-
-! DUP (general): Duplicate general-purpose register to vector.
-ARM-INSTRUCTION: DUPgen-encode ( 0 Q 0 01110000 imm5 0 0001 1 Rn Rd -- )
-
-! DVP: Data Value Prediction Restriction by Context: an alias of SYS.
-ARM-INSTRUCTION: DVP-encode ( 1101010100 0 01 011 0111 0011 101 Rt -- )
-
-! EON (shifted register): Bitwise Exclusive OR NOT (shifted register).
-ARM-INSTRUCTION: EONsr32-encode ( 0 10 01010 shift2 1 Rm imm6 Rn Rd -- )
-ARM-INSTRUCTION: EONsr64-encode ( 1 10 01010 shift2 1 Rm imm6 Rn Rd -- )
-
-! EOR (immediate): Bitwise Exclusive OR (immediate).
-ARM-INSTRUCTION: EORi32-encode ( 0 10 100100 0 immrimms Rn Rd -- )
-ARM-INSTRUCTION: EORi64-encode ( 1 10 100100 Nimmrimms Rn Rd -- )
-
-! EOR (shifted register): Bitwise Exclusive OR (shifted register).
-ARM-INSTRUCTION: EORsr32-encode ( 0 10 01010 shift2 0 Rm imm6 Rn Rd -- )
-ARM-INSTRUCTION: EORsr64-encode ( 1 10 01010 shift2 0 Rm imm6 Rn Rd -- )
-
-! ERET: Exception Return.
-ARM-INSTRUCTION: ERET-encode ( 1101011 0 100 11111 0000 0 0 11111 00000 -- )
-
-! ERETAA, ERETAB: Exception Return, with pointer authentication.
-! ARMv8.3
-ARM-INSTRUCTION: ERETAA-encode ( 1101011 0 100 11111 0000 1 0 11111 00000 -- )
-ARM-INSTRUCTION: ERETAB-encode ( 1101011 0 100 11111 0000 1 1 11111 11111 -- )
-
-! ESB: Error Synchronization Barrier.
-! ARMv8.2
-ARM-INSTRUCTION: ESB-encode ( 1101010100 0 00 011 0010 0010 000 11111 -- )
-
-! EXTR: Extract register.
-ARM-INSTRUCTION: EXTR32-encode ( 0 00 100111 0 0 Rm imms Rn Rd -- )
-ARM-INSTRUCTION: EXTR64-encode ( 1 00 100111 1 0 Rm imms Rn Rd -- )
-
-! FADD (scalar): Floating-point Add (scalar).
-ARM-INSTRUCTION: FADDs-encode ( 0 0 0 11110 ftype 1 Rm 001 0 10 Rn Rd -- )
-
-! FCVT: Floating-point Convert percision (scalar).
-ARM-INSTRUCTION: FCVT-encode ( 0 0 0 11110 ftype 1 0001 opc2 10000 Rn Rd -- )
-
-! FCVTZS (scalar, integer): Floating-point Convert to Signed integer, rounding toward Zero (scalar).
-ARM-INSTRUCTION: FCVTZSsi64-encode ( 1 0 0 11110 ftype 1 11 000 000000 Rn Rd -- )
-
-! FDIV (scalar): Floating-point Divide (scalar).
-ARM-INSTRUCTION: FDIVs-encode ( 0 0 0 11110 ftype 1 Rm 0001 10 Rn Rd -- )
-
-! FMAX (scalar): Floating-point Maximum (scalar).
-ARM-INSTRUCTION: FMAXs-encode ( 0 0 0 11110 ftype 1 Rm 01 00 10 Rn Rd -- )
-
-! FMIN (scalar): Floating-point Minimum (scalar).
-ARM-INSTRUCTION: FMINs-encode ( 0 0 0 11110 ftype 1 Rm 01 01 10 Rn Rd -- )
-
-! FMOV (general): Floating-point Move to or from general-purpose register without conversion.
-ARM-INSTRUCTION: FMOVgen-encode ( sf 0 0 11110 ftype 1 rmode opc3 000000 Rn Rd -- )
-
-! FMUL (scalar): Floating-point Multiply (scalar).
-ARM-INSTRUCTION: FMULs-encode ( 0 0 0 11110 ftype 1 Rm 0 000 10 Rn Rd -- )
-
-! FSQRT (scalar): Floating-point Square Root (scalar).
-ARM-INSTRUCTION: FSQRTs-encode ( 0 0 0 11110 ftype 1 0000 11 10000 Rn Rd -- )
-
-! FSUB (scalar): Floating-point Subtract (scalar).
-ARM-INSTRUCTION: FSUBs-encode ( 0 0 0 11110 ftype 1 Rm 001 1 10 Rn Rd -- )
-
-! GMI: Tag Mask Insert.
-ARM-INSTRUCTION: GMI-encode ( 1 0 0 11010110 Xm 0 0 0 1 0 1 Xn Xd -- )
-
-! HINT: Hint instruction.
-ARM-INSTRUCTION: HINT-encode ( 1101010100 0 00 011 0010 CRm op3 11111 -- )
-
-! HLT: Halt instruction.
-ARM-INSTRUCTION: HLT-encode ( 11010100 010 imm16 000 00 -- )
-
-! HVC: Hypervisor Call.
-ARM-INSTRUCTION: HVC-encode ( 11010100 000 imm16 000 10 -- )
-
-! IC: Instruction Cache operation: an alias of SYS.
-ARM-INSTRUCTION: IC-encode ( 1101010100 0 01 op3 0111 CRm op3 Rt -- )
-
-! IRG: Insert Random Tag.
-ARM-INSTRUCTION: IRG-encode ( 1 0 0 11010110 Xm 0 0 0 1 0 0 Xn Xd -- )
-
-! ISB: Instruction Synchronization Barrier.
-ARM-INSTRUCTION: ISB-encode ( 1101010100 0 00 011 0011 CRm 1 10 11111 -- )
-
-! LDADD, LDADDA, LDADDAL, LDADDL: Atomic add on word or doubleword in memory.
-ARM-INSTRUCTION: LDADD32-encode ( 10 111 0 00 0 0 1 Rs 0 000 00 Rn Rt -- )
-ARM-INSTRUCTION: LDADDA32-encode ( 10 111 0 00 1 0 1 Rs 0 000 00 Rn Rt -- )
-ARM-INSTRUCTION: LDADDAL32-encode ( 10 111 0 00 1 1 1 Rs 0 000 00 Rn Rt -- )
-ARM-INSTRUCTION: LDADDL32-encode ( 10 111 0 00 0 1 1 Rs 0 000 00 Rn Rt -- )
-ARM-INSTRUCTION: LDADD64-encode ( 11 111 0 00 0 0 1 Rs 0 000 00 Rn Rt -- )
-ARM-INSTRUCTION: LDADDA64-encode ( 11 111 0 00 1 0 1 Rs 0 000 00 Rn Rt -- )
-ARM-INSTRUCTION: LDADDAL64-encode ( 11 111 0 00 1 1 1 Rs 0 000 00 Rn Rt -- )
-ARM-INSTRUCTION: LDADDL64-encode ( 11 111 0 00 0 1 1 Rs 0 000 00 Rn Rt -- )
-
-! LDADDB, LDADDAB, LDADDALB, LDADDLB: Atomic add on byte in memory.
-ARM-INSTRUCTION: LDADDAB-encode ( 00 111 0 00 1 0 1 Rs 0 000 00 Rn Rt -- )
-ARM-INSTRUCTION: LDADDALB-encode ( 00 111 0 00 1 1 1 Rs 0 000 00 Rn Rt -- )
-ARM-INSTRUCTION: LDADDB-encode ( 00 111 0 00 0 0 1 Rs 0 000 00 Rn Rt -- )
-ARM-INSTRUCTION: LDADDLB-encode ( 00 111 0 00 0 1 1 Rs 0 000 00 Rn Rt -- )
-
-! LDADDH, LDADDAH, LDADDALH, LDADDLH: Atomic add on halfword in memory.
-ARM-INSTRUCTION: LDADDAH-encode ( 01 111 0 00 1 0 1 Rs 0 000 00 Rn Rt -- )
-ARM-INSTRUCTION: LDADDALH-encode ( 01 111 0 00 1 1 1 Rs 0 000 00 Rn Rt -- )
-ARM-INSTRUCTION: LDADDH-encode ( 01 111 0 00 0 0 1 Rs 0 000 00 Rn Rt -- )
-ARM-INSTRUCTION: LDADDLH-encode ( 01 111 0 00 0 1 1 Rs 0 000 00 Rn Rt -- )
-
-! LDAPR: Load-Acquire RCpc Register.
-! ARMv8.3
-ARM-INSTRUCTION: LDAPR32-encode ( 10 111 0 00 1 0 1 11111 1 100 00 Rn Rt -- )
-ARM-INSTRUCTION: LDAPR64-encode ( 11 111 0 00 1 0 1 11111 1 100 00 Rn Rt -- )
-! LDAPRB: Load-Acquire RCpc Register Byte.
-ARM-INSTRUCTION: LDAPRB-encode ( 00 111 0 00 1 0 1 11111 1 100 00 Rn Rt -- )
-! LDAPRH: Load-Acquire RCpc Register Halfword.
-ARM-INSTRUCTION: LDAPRH-encode ( 01 111 0 00 1 0 1 11111 1 100 00 Rn Rt -- )
-
-! LDAPUR: Load-Acquire RCpc Register (unscaled).
-ARM-INSTRUCTION: LDAPUR32-encode ( 10 011001 01 0 imm9 00 Rn Rt -- )
-ARM-INSTRUCTION: LDAPUR64-encode ( 11 011001 01 0 imm9 00 Rn Rt -- )
-! LDAPURB: Load-Acquire RCpc Register Byte (unscaled).
-ARM-INSTRUCTION: LDAPURB-encode ( 00 011001 01 0 imm9 00 Rn Rt -- )
-! LDAPURH: Load-Acquire RCpc Register Halfword (unscaled).
-ARM-INSTRUCTION: LDAPURH-encode ( 01 011001 01 0 imm9 00 Rn Rt -- )
-! LDAPURSB: Load-Acquire RCpc Register Signed Byte (unscaled).
-ARM-INSTRUCTION: LDAPURSB32-encode ( 00 011001 11 0 imm9 00 Rn Rt -- )
-ARM-INSTRUCTION: LDAPURSB64-encode ( 00 011001 10 0 imm9 00 Rn Rt -- )
-! LDAPURSH: Load-Acquire RCpc Register Signed Halfword (unscaled).
-ARM-INSTRUCTION: LDAPURSH32-encode ( 01 011001 11 0 imm9 00 Rn Rt -- )
-ARM-INSTRUCTION: LDAPURSH64-encode ( 01 011001 10 0 imm9 00 Rn Rt -- )
-! LDAPURSW: Load-Acquire RCpc Register Signed Word (unscaled).
-ARM-INSTRUCTION: LDAPURSW-encode ( 10 011001 10 0 imm9 00 Rn Rt -- )
-! LDAR: Load-Acquire Register.
-ARM-INSTRUCTION: LDAR32-encode ( 10 001000 1 1 0 11111 1 11111 Rn Rt -- )
-ARM-INSTRUCTION: LDAR64-encode ( 11 001000 1 1 0 11111 1 11111 Rn Rt -- )
-! LDARB: Load-Acquire Register Byte.
-ARM-INSTRUCTION: LDARB-encode ( 00 001000 1 1 0 11111 1 11111 Rn Rt -- )
-! LDARH: Load-Acquire Register Halfword.
-ARM-INSTRUCTION: LDARH-encode ( 01 001000 1 1 0 11111 1 11111 Rn Rt -- )
-! LDAXP: Load-Acquire Exclusive Pair of Registers.
-ARM-INSTRUCTION: LDAXP32-encode ( 1 0 001000 0 1 1 11111 1 Rt2 Rn Rt -- )
-ARM-INSTRUCTION: LDAXP64-encode ( 1 1 001000 0 1 1 11111 1 Rt2 Rn Rt -- )
-! LDAXR: Load-Acquire Exclusive Register.
-ARM-INSTRUCTION: LDAXR32-encode ( 10 001000 0 1 0 11111 1 11111 Rn Rt -- )
-ARM-INSTRUCTION: LDAXR64-encode ( 11 001000 0 1 0 11111 1 11111 Rn Rt -- )
-! LDAXRB: Load-Acquire Exclusive Register Byte.
-ARM-INSTRUCTION: LDAXRB-encode ( 00 001000 0 1 0 11111 1 11111 Rn Rt -- )
-! LDAXRH: Load-Acquire Exclusive Register Halfword.
-ARM-INSTRUCTION: LDAXRH-encode ( 01 001000 0 1 0 11111 1 11111 Rn Rt -- )
-
-! LDCLR, LDCLRA, LDCLRAL, LDCLRL: Atomic bit clear on word or doubleword in memory.
-ARM-INSTRUCTION: LDCLR32-encode ( 10 111 0 00 0 0 1 Rs 0 001 00 Rn Rt -- )
-ARM-INSTRUCTION: LDCLRA32-encode ( 10 111 0 00 1 0 1 Rs 0 001 00 Rn Rt -- )
-ARM-INSTRUCTION: LDCLRAL32-encode ( 10 111 0 00 1 1 1 Rs 0 001 00 Rn Rt -- )
-ARM-INSTRUCTION: LDCLRL32-encode ( 10 111 0 00 0 1 1 Rs 0 001 00 Rn Rt -- )
-ARM-INSTRUCTION: LDCLR64-encode ( 11 111 0 00 0 0 1 Rs 0 001 00 Rn Rt -- )
-ARM-INSTRUCTION: LDCLRA64-encode ( 11 111 0 00 1 0 1 Rs 0 001 00 Rn Rt -- )
-ARM-INSTRUCTION: LDCLRAL64-encode ( 11 111 0 00 1 1 1 Rs 0 001 00 Rn Rt -- )
-ARM-INSTRUCTION: LDCLRL64-encode ( 11 111 0 00 0 1 1 Rs 0 001 00 Rn Rt -- )
-
-! LDCLRB, LDCLRAB, LDCLRALB, LDCLRLB: Atomic bit clear on byte in memory.
-ARM-INSTRUCTION: LDCLRAB-encode ( 00 111 0 00 1 0 1 Rs 0 001 00 Rn Rt -- )
-ARM-INSTRUCTION: LDCLRALB-encode ( 00 111 0 00 1 1 1 Rs 0 001 00 Rn Rt -- )
-ARM-INSTRUCTION: LDCLRB-encode ( 00 111 0 00 0 0 1 Rs 0 001 00 Rn Rt -- )
-ARM-INSTRUCTION: LDCLRLB-encode ( 00 111 0 00 0 1 1 Rs 0 001 00 Rn Rt -- )
-
-! LDCLRH, LDCLRAH, LDCLRALH, LDCLRLH: Atomic bit clear on halfword in memory.
-ARM-INSTRUCTION: LDCLRAH-encode ( 01 111 0 00 1 0 1 Rs 0 001 00 Rn Rt -- )
-ARM-INSTRUCTION: LDCLRALH-encode ( 01 111 0 00 1 1 1 Rs 0 001 00 Rn Rt -- )
-ARM-INSTRUCTION: LDCLRA-encode ( 01 111 0 00 0 0 1 Rs 0 001 00 Rn Rt -- )
-ARM-INSTRUCTION: LDCLRLH-encode ( 01 111 0 00 0 1 1 Rs 0 001 00 Rn Rt -- )
-
-! LDEOR, LDEORA, LDEORAL, LDEORL: Atomic exclusive OR on word or doubleword in memory.
-ARM-INSTRUCTION: LDEOR32-encode ( 10 111 0 00 0 0 1 Rs 0 010 00 Rn Rt -- )
-ARM-INSTRUCTION: LDEORA32-encode ( 10 111 0 00 1 0 1 Rs 0 010 00 Rn Rt -- )
-ARM-INSTRUCTION: LDEORAL32-encode ( 10 111 0 00 1 1 1 Rs 0 010 00 Rn Rt -- )
-ARM-INSTRUCTION: LDEORL32-encode ( 10 111 0 00 0 1 1 Rs 0 010 00 Rn Rt -- )
-ARM-INSTRUCTION: LDEOR64-encode ( 11 111 0 00 0 0 1 Rs 0 010 00 Rn Rt -- )
-ARM-INSTRUCTION: LDEORA64-encode ( 11 111 0 00 1 0 1 Rs 0 010 00 Rn Rt -- )
-ARM-INSTRUCTION: LDEORAL64-encode ( 11 111 0 00 1 1 1 Rs 0 010 00 Rn Rt -- )
-ARM-INSTRUCTION: LDEORL64-encode ( 11 111 0 00 0 1 1 Rs 0 010 00 Rn Rt -- )
-
-! LDEORB, LDEORAB, LDEORALB, LDEORLB: Atomic exclusive OR on byte in memory.
-ARM-INSTRUCTION: LDEORAB-encode ( 00 111 0 00 1 0 1 Rs 0 010 00 Rn Rt -- )
-ARM-INSTRUCTION: LDEORALB-encode ( 00 111 0 00 1 1 1 Rs 0 010 00 Rn Rt -- )
-ARM-INSTRUCTION: LDEORB-encode ( 00 111 0 00 0 0 1 Rs 0 010 00 Rn Rt -- )
-ARM-INSTRUCTION: LDEORLB-encode ( 00 111 0 00 0 1 1 Rs 0 010 00 Rn Rt -- )
-
-! LDEORH, LDEORAH, LDEORALH, LDEORLH: Atomic exclusive OR on halfword in memory.
-! ARMv8.1
-ARM-INSTRUCTION: LDEORAH-encode ( 01 111 0 00 1 0 1 Rs 0 010 00 Rn Rt -- )
-ARM-INSTRUCTION: LDEORALH-encode ( 01 111 0 00 1 1 1 Rs 0 010 00 Rn Rt -- )
-ARM-INSTRUCTION: LDEORH-encode ( 01 111 0 00 0 0 1 Rs 0 010 00 Rn Rt -- )
-ARM-INSTRUCTION: LDEORLH-encode ( 01 111 0 00 0 1 1 Rs 0 010 00 Rn Rt -- )
-
-! LDG: Load Allocation Tag.
-! ARMv8.5
-ARM-INSTRUCTION: LDG-encode ( 11011001 0 1 1 imm9 0 0 Xn Xt -- )
-! LDGV: Load Tag Multiple.
-! ARMv8.5
-ARM-INSTRUCTION: LDGM-encode ( 11011001 1 1 1 0 0 0 0 0 0 0 0 0 0 0 Xn Xt -- )
-
-! LDLAR: Load LOAcquire Register.
-! ARMv8.1
-ARM-INSTRUCTION: LDLAR32-encode ( 10 001000 1 1 0 11111 0 11111 Rn Rt -- )
-ARM-INSTRUCTION: LDLAR64-encode ( 11 001000 1 1 0 11111 0 11111 Rn Rt -- )
-! LDLARB: Load LOAcquire Register Byte.
-ARM-INSTRUCTION: LDLARB-encode ( 00 001000 1 1 0 11111 0 11111 Rn Rt -- )
-! LDLARH: Load LOAcquire Register Halfword.
-ARM-INSTRUCTION: LDLARH-encode ( 01 001000 1 1 0 11111 0 11111 Rn Rt -- )
-
-! LDNP: Load Pair of Registers, with non-temporal hint.
-ARM-INSTRUCTION: LDNP32-encode ( 00 101 0 000 1 imm7 Rt2 Rn Rt -- )
-ARM-INSTRUCTION: LDNP64-encode ( 10 101 0 000 1 imm7 Rt2 Rn Rt -- )
-
-! LDP: Load Pair of Registers.
-ARM-INSTRUCTION: LDPpost32-encode ( 00 101 0 001 1 imm7 Rt2 Rn Rt -- )
-ARM-INSTRUCTION: LDPpost64-encode ( 10 101 0 001 1 imm7 Rt2 Rn Rt -- )
-ARM-INSTRUCTION: LDPpre32-encode ( 00 101 0 011 1 imm7 Rt2 Rn Rt -- )
-ARM-INSTRUCTION: LDPpre64-encode ( 10 101 0 011 1 imm7 Rt2 Rn Rt -- )
-ARM-INSTRUCTION: LDPsoff32-encode ( 00 101 0 010 1 imm7 Rt2 Rn Rt -- )
-ARM-INSTRUCTION: LDPsoff64-encode ( 10 101 0 010 1 imm7 Rt2 Rn Rt -- )
-
-! LDPSW: Load Pair of Registers Signed Word.
-ARM-INSTRUCTION: LDPSWpost-encode ( 01 101 0 001 1 imm7 Rt2 Rn Rt -- )
-ARM-INSTRUCTION: LDPSWpre-encode ( 01 101 0 011 1 imm7 Rt2 Rn Rt -- )
-ARM-INSTRUCTION: LDPSWsoff-encode ( 01 101 0 010 1 imm7 Rt2 Rn Rt -- )
-
-! LDR (immediate): Load Register (immediate).
-ARM-INSTRUCTION: LDRpost32-encode ( 10 111 0 00 01 0 imm9 01 Rn Rt -- )
-ARM-INSTRUCTION: LDRpost64-encode ( 11 111 0 00 01 0 imm9 01 Rn Rt -- )
-ARM-INSTRUCTION: LDRpre32-encode ( 10 111 0 00 01 0 imm9 11 Rn Rt -- )
-ARM-INSTRUCTION: LDRpre64-encode ( 11 111 0 00 01 0 imm9 11 Rn Rt -- )
-ARM-INSTRUCTION: LDRuoff32-encode ( 10 111 0 01 01 imm12 Rn Rt -- )
-ARM-INSTRUCTION: LDRuoff64-encode ( 11 111 0 01 01 imm12 Rn Rt -- )
-
-! LDR (literal): Load Register (literal).
-ARM-INSTRUCTION: LDRl32-encode ( 00 011 0 00 imm19 Rt -- )
-ARM-INSTRUCTION: LDRl64-encode ( 01 011 0 00 imm19 Rt -- )
-
-! LDR (register): Load Register (register).
-ARM-INSTRUCTION: LDRr32-encode ( 10 111 0 00 01 1 Rm option3 S 1 0 Rn Rt -- )
-ARM-INSTRUCTION: LDRr64-encode ( 11 111 0 00 01 1 Rm option3 S 1 0 Rn Rt -- )
-
-! LDRAA, LDRAB: Load Register, with pointer authentication.
-! ARMv8.3
-ARM-INSTRUCTION: LDRAAoff-encode ( 11 111 0 00 0 S 1 imm9 0 1 Rn Rt -- )
-ARM-INSTRUCTION: LDRAApre-encode ( 11 111 0 00 0 S 1 imm9 1 1 Rn Rt -- )
-ARM-INSTRUCTION: LDRABoff-encode ( 11 111 0 00 1 S 1 imm9 0 1 Rn Rt -- )
-ARM-INSTRUCTION: LDRABpre-encode ( 11 111 0 00 1 S 1 imm9 1 1 Rn Rt -- )
-
-! LDRB (immediate): Load Register Byte (immediate).
-ARM-INSTRUCTION: LDRBpost-encode ( 00 111 0 00 01 0 imm9 01 Rn Rt -- )
-ARM-INSTRUCTION: LDRBpre-encode ( 00 111 0 00 01 0 imm9 11 Rn Rt -- )
-ARM-INSTRUCTION: LDRBuoff-encode ( 00 111 0 01 01 imm12 Rn Rt -- )
-
-! LDRB (register): Load Register Byte (register).
-! option: 010: UXTW, 110 SXTW, 111 SXTX, S shift 0/1
-ARM-INSTRUCTION: LDRBer-encode ( 00 111 0 00 01 1 Rm option3 S 10 Rn Rt -- )
-ARM-INSTRUCTION: LDRBsr-encode ( 00 111 0 00 01 1 Rm 011 S 10 Rn Rt -- )
-
-! LDRH (immediate): Load Register Halfword (immediate).
-ARM-INSTRUCTION: LDRHpost-encode ( 01 111 0 00 01 0 imm9 01 Rn Rt -- )
-ARM-INSTRUCTION: LDRHpre-encode ( 01 111 0 00 01 0 imm9 11 Rn Rt -- )
-ARM-INSTRUCTION: LDRHuoff-encode ( 01 111 0 01 01 imm12 Rn Rt -- )
-
-! LDRH (register): Load Register Halfword (register).
-ARM-INSTRUCTION: LDRHr-encode ( 01 111 0 00 01 1 Rm option3 S 10 Rn Rt -- )
-
-! LDRSB (immediate): Load Register Signed Byte (immediate).
-ARM-INSTRUCTION: LDRSBpost32-encode ( 00 111 0 00 11 0 imm9 01 Rn Rt -- )
-ARM-INSTRUCTION: LDRSBpost64-encode ( 00 111 0 00 10 0 imm9 01 Rn Rt -- )
-ARM-INSTRUCTION: LDRSBpre32-encode ( 00 111 0 00 11 0 imm9 11 Rn Rt -- )
-ARM-INSTRUCTION: LDRSBpre64-encode ( 00 111 0 00 10 0 imm9 11 Rn Rt -- )
-ARM-INSTRUCTION: LDRSBuoff32-encode ( 00 111 0 01 11 imm12 Rn Rt -- )
-ARM-INSTRUCTION: LDRSBuoff64-encode ( 00 111 0 01 10 imm12 Rn Rt -- )
-
-! LDRSB (register): Load Register Signed Byte (register).
-ARM-INSTRUCTION: LDRSBer32-encode ( 00 111 0 00 11 1 Rm option3 S 10 Rn Rt -- )
-ARM-INSTRUCTION: LDRSBsr32-encode ( 00 111 0 00 11 1 Rm 011 S 10 Rn Rt -- )
-ARM-INSTRUCTION: LDRSBer64-encode ( 00 111 0 00 10 1 Rm option3 S 10 Rn Rt -- )
-ARM-INSTRUCTION: LDRSBsr64-encode ( 00 111 0 00 10 1 Rm 011 S 10 Rn Rt -- )
-
-! LDRSH (immediate): Load Register Signed Halfword (immediate).
-ARM-INSTRUCTION: LDRSHpost32-encode ( 01 111 0 00 11 0 imm9 01 Rn Rt -- )
-ARM-INSTRUCTION: LDRSHpost64-encode ( 01 111 0 00 10 0 imm9 01 Rn Rt -- )
-ARM-INSTRUCTION: LDRSHpre32-encode ( 01 111 0 00 11 0 imm9 11 Rn Rt -- )
-ARM-INSTRUCTION: LDRSHpre64-encode ( 01 111 0 00 10 0 imm9 11 Rn Rt -- )
-ARM-INSTRUCTION: LDRSHuoff32-encode ( 01 111 0 01 11 imm12 Rn Rt -- )
-ARM-INSTRUCTION: LDRSHuoff64-encode ( 01 111 0 01 10 imm12 Rn Rt -- )
-
-! LDRSH (register): Load Register Signed Halfword (register).
-ARM-INSTRUCTION: LDRSHr32-encode ( 01 111 0 00 11 1 Rm option3 S 10 Rn Rt -- )
-ARM-INSTRUCTION: LDRSHr64-encode ( 01 111 0 00 10 1 Rm option3 S 10 Rn Rt -- )
-
-! LDRSW (immediate): Load Register Signed Word (immediate).
-ARM-INSTRUCTION: LDRSWpost32-encode ( 10 111 0 00 10 0 imm9 01 Rn Rt -- )
-ARM-INSTRUCTION: LDRSWpre32-encode ( 10 111 0 00 10 0 imm9 11 Rn Rt -- )
-ARM-INSTRUCTION: LDRSWuoff64-encode ( 10 111 0 01 10 imm12 Rn Rt -- )
-
-! LDRSW (literal): Load Register Signed Word (literal).
-ARM-INSTRUCTION: LDRSWl-encode ( 10 011 0 00 imm19 Rt -- )
-
-! LDRSW (register): Load Register Signed Word (register).
-ARM-INSTRUCTION: LDRSWr-encode ( 10 111 0 00 10 1 Rm option3 S 10 Rn Rt -- )
-
-! LDSET, LDSETA, LDSETAL, LDSETL: Atomic bit set on word or doubleword in memory.
-ARM-INSTRUCTION: LDSET32-encode ( 10 111 0 00 0 0 1 Rs 0 011 00 Rn Rt -- )
-ARM-INSTRUCTION: LDSETA32-encode ( 10 111 0 00 1 0 1 Rs 0 011 00 Rn Rt -- )
-ARM-INSTRUCTION: LDSETAL32-encode ( 10 111 0 00 1 1 1 Rs 0 011 00 Rn Rt -- )
-ARM-INSTRUCTION: LDSETL32-encode ( 10 111 0 00 0 1 1 Rs 0 011 00 Rn Rt -- )
-ARM-INSTRUCTION: LDSET64-encode ( 11 111 0 00 0 0 1 Rs 0 011 00 Rn Rt -- )
-ARM-INSTRUCTION: LDSETA64-encode ( 11 111 0 00 1 0 1 Rs 0 011 00 Rn Rt -- )
-ARM-INSTRUCTION: LDSETAL64-encode ( 11 111 0 00 1 1 1 Rs 0 011 00 Rn Rt -- )
-ARM-INSTRUCTION: LDSETL64-encode ( 11 111 0 00 0 1 1 Rs 0 011 00 Rn Rt -- )
-
-! LDSETB, LDSETAB, LDSETALB, LDSETLB: Atomic bit set on byte in memory.
-ARM-INSTRUCTION: LDSETAB-encode ( 00 111 0 00 1 0 1 Rs 0 011 00 Rn Rt -- )
-ARM-INSTRUCTION: LDSETALB-encode ( 00 111 0 00 1 1 1 Rs 0 011 00 Rn Rt -- )
-ARM-INSTRUCTION: LDSETB-encode ( 00 111 0 00 0 0 1 Rs 0 011 00 Rn Rt -- )
-ARM-INSTRUCTION: LDSETLB-encode ( 00 111 0 00 0 1 1 Rs 0 011 00 Rn Rt -- )
-
-! LDSETH, LDSETAH, LDSETALH, LDSETLH: Atomic bit set on halfword in memory.
-ARM-INSTRUCTION: LDSETAH-encode ( 01 111 0 00 1 0 1 Rs 0 011 00 Rn Rt -- )
-ARM-INSTRUCTION: LDSETALH-encode ( 01 111 0 00 1 1 1 Rs 0 011 00 Rn Rt -- )
-ARM-INSTRUCTION: LDSETH-encode ( 01 111 0 00 0 0 1 Rs 0 011 00 Rn Rt -- )
-ARM-INSTRUCTION: LDSETLH-encode ( 01 111 0 00 0 1 1 Rs 0 011 00 Rn Rt -- )
-
-! LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL: Atomic signed maximum on word or doubleword in memory.
-ARM-INSTRUCTION: LDSMAX32-encode ( 10 111 0 00 0 0 1 Rs 0 100 00 Rn Rt -- )
-ARM-INSTRUCTION: LDSMAXA32-encode ( 10 111 0 00 1 0 1 Rs 0 100 00 Rn Rt -- )
-ARM-INSTRUCTION: LDSMAXAL32-encode ( 10 111 0 00 1 1 1 Rs 0 100 00 Rn Rt -- )
-ARM-INSTRUCTION: LDSMAXL32-encode ( 10 111 0 00 0 1 1 Rs 0 100 00 Rn Rt -- )
-ARM-INSTRUCTION: LDSMAX64-encode ( 11 111 0 00 0 0 1 Rs 0 100 00 Rn Rt -- )
-ARM-INSTRUCTION: LDSMAXA64-encode ( 11 111 0 00 1 0 1 Rs 0 100 00 Rn Rt -- )
-ARM-INSTRUCTION: LDSMAXAL64-encode ( 11 111 0 00 1 1 1 Rs 0 100 00 Rn Rt -- )
-ARM-INSTRUCTION: LDSMAXL64-encode ( 11 111 0 00 0 1 1 Rs 0 100 00 Rn Rt -- )
-
-! LDSMAXB, LDSMAXAB, LDSMAXALB, LDSMAXLB: Atomic signed maximum on byte in memory.
-ARM-INSTRUCTION: LDSMAXAB-encode ( 00 111 0 00 1 0 1 Rs 0 100 00 Rn Rt -- )
-ARM-INSTRUCTION: LDSMAXALB-encode ( 00 111 0 00 1 1 1 Rs 0 100 00 Rn Rt -- )
-ARM-INSTRUCTION: LDSMAXB-encode ( 00 111 0 00 0 0 1 Rs 0 100 00 Rn Rt -- )
-ARM-INSTRUCTION: LDSMAXLB-encode ( 00 111 0 00 0 1 1 Rs 0 100 00 Rn Rt -- )
-
-! LDSMAXH, LDSMAXAH, LDSMAXALH, LDSMAXLH: Atomic signed maximum on halfword in memory.
-ARM-INSTRUCTION: LDSMAXAH-encode ( 00 111 0 00 1 0 1 Rs 0 100 00 Rn Rt -- )
-ARM-INSTRUCTION: LDSMAXALH-encode ( 00 111 0 00 1 1 1 Rs 0 100 00 Rn Rt -- )
-ARM-INSTRUCTION: LDSMAXH-encode ( 00 111 0 00 0 0 1 Rs 0 100 00 Rn Rt -- )
-ARM-INSTRUCTION: LDSMAXLH-encode ( 00 111 0 00 0 1 1 Rs 0 100 00 Rn Rt -- )
-
-! LDSMIN, LDSMINA, LDSMINAL, LDSMINL: Atomic signed minimum on word or doubleword in memory.
-ARM-INSTRUCTION: LDSMIN32-encode ( 10 111 0 00 0 0 1 Rs 0 101 00 Rn Rt -- )
-ARM-INSTRUCTION: LDSMINA32-encode ( 10 111 0 00 1 0 1 Rs 0 101 00 Rn Rt -- )
-ARM-INSTRUCTION: LDSMINAL32-encode ( 10 111 0 00 1 1 1 Rs 0 101 00 Rn Rt -- )
-ARM-INSTRUCTION: LDSMINL32-encode ( 10 111 0 00 0 1 1 Rs 0 101 00 Rn Rt -- )
-ARM-INSTRUCTION: LDSMIN64-encode ( 11 111 0 00 0 0 1 Rs 0 101 00 Rn Rt -- )
-ARM-INSTRUCTION: LDSMINA64-encode ( 11 111 0 00 1 0 1 Rs 0 101 00 Rn Rt -- )
-ARM-INSTRUCTION: LDSMINAL64-encode ( 11 111 0 00 1 1 1 Rs 0 101 00 Rn Rt -- )
-ARM-INSTRUCTION: LDSMINL64-encode ( 11 111 0 00 0 1 1 Rs 0 101 00 Rn Rt -- )
-
-! LDSMINB, LDSMINAB, LDSMINALB, LDSMINLB: Atomic signed minimum on byte in memory.
-! ARMv8.1
-ARM-INSTRUCTION: LDSMINAB-encode ( 00 111 0 00 1 0 1 Rs 0 101 00 Rn Rt -- )
-ARM-INSTRUCTION: LDSMINALB-encode ( 00 111 0 00 1 1 1 Rs 0 101 00 Rn Rt -- )
-ARM-INSTRUCTION: LDSMINB-encode ( 00 111 0 00 0 0 1 Rs 0 101 00 Rn Rt -- )
-ARM-INSTRUCTION: LDSMINLB-encode ( 00 111 0 00 0 1 1 Rs 0 101 00 Rn Rt -- )
-
-! LDSMINH, LDSMINAH, LDSMINALH, LDSMINLH: Atomic signed minimum on halfword in memory.
-! ARMv8.1
-ARM-INSTRUCTION: LDSMINAH-encode ( 01 111 0 00 1 0 1 Rs 0 101 00 Rn Rt -- )
-ARM-INSTRUCTION: LDSMINALH-encode ( 01 111 0 00 1 1 1 Rs 0 101 00 Rn Rt -- )
-ARM-INSTRUCTION: LDSMINH-encode ( 01 111 0 00 0 0 1 Rs 0 101 00 Rn Rt -- )
-ARM-INSTRUCTION: LDSMINLH-encode ( 01 111 0 00 0 1 1 Rs 0 101 00 Rn Rt -- )
-
-! LDTR: Load Register (unprivileged).
-ARM-INSTRUCTION: LDTR32-encode ( 10 111 0 00 01 0 imm9 10 Rn Rt -- )
-ARM-INSTRUCTION: LDTR64-encode ( 11 111 0 00 01 0 imm9 10 Rn Rt -- )
-
-! LDTRB: Load Register Byte (unprivileged).
-ARM-INSTRUCTION: LDTRB-encode ( 00 111 0 00 01 0 imm9 10 Rn Rt -- )
-
-! LDTRH: Load Register Halfword (unprivileged).
-ARM-INSTRUCTION: LDTRH-encode ( 01 111 0 00 01 0 imm9 10 Rn Rt -- )
-
-! LDTRSB: Load Register Signed Byte (unprivileged).
-ARM-INSTRUCTION: LDTRSB32-encode ( 00 111 0 00 11 0 imm9 10 Rn Rt -- )
-ARM-INSTRUCTION: LDTRSB64-encode ( 00 111 0 00 10 0 imm9 10 Rn Rt -- )
-
-! LDTRSH: Load Register Signed Halfword (unprivileged).
-ARM-INSTRUCTION: LDTRSH32-encode ( 01 111 0 00 11 0 imm9 10 Rn Rt -- )
-ARM-INSTRUCTION: LDTRSH64-encode ( 01 111 0 00 10 0 imm9 10 Rn Rt -- )
-
-! LDTRSW: Load Register Signed Word (unprivileged).
-ARM-INSTRUCTION: LDTRSW-encode ( 10 111 0 00 10 0 imm9 10 Rn Rt -- )
-
-! LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL: Atomic unsigned maximum on word or doubleword in memory.
-! ARMv8.1
-ARM-INSTRUCTION: LDUMAX32-encode ( 10 111 0 00 0 0 1 Rs 0 110 00 Rn Rt -- )
-ARM-INSTRUCTION: LDUMAXA32-encode ( 10 111 0 00 1 0 1 Rs 0 110 00 Rn Rt -- )
-ARM-INSTRUCTION: LDUMAXAL32-encode ( 10 111 0 00 1 1 1 Rs 0 110 00 Rn Rt -- )
-ARM-INSTRUCTION: LDUMAXL32-encode ( 10 111 0 00 0 1 1 Rs 0 110 00 Rn Rt -- )
-ARM-INSTRUCTION: LDUMAX64-encode ( 11 111 0 00 0 0 1 Rs 0 110 00 Rn Rt -- )
-ARM-INSTRUCTION: LDUMAXA64-encode ( 11 111 0 00 1 0 1 Rs 0 110 00 Rn Rt -- )
-ARM-INSTRUCTION: LDUMAXAL64-encode ( 11 111 0 00 1 1 1 Rs 0 110 00 Rn Rt -- )
-ARM-INSTRUCTION: LDUMAXL64-encode ( 11 111 0 00 0 1 1 Rs 0 110 00 Rn Rt -- )
-
-! LDUMAXB, LDUMAXAB, LDUMAXALB, LDUMAXLB: Atomic unsigned maximum on byte in memory.
-! ARMv8.1
-ARM-INSTRUCTION: LDUMAXAB-encode ( 00 111 0 00 1 0 1 Rs 0 110 00 Rn Rt -- )
-ARM-INSTRUCTION: LDUMAXALB-encode ( 00 111 0 00 1 1 1 Rs 0 110 00 Rn Rt -- )
-ARM-INSTRUCTION: LDUMAXB-encode ( 00 111 0 00 0 0 1 Rs 0 110 00 Rn Rt -- )
-ARM-INSTRUCTION: LDUMAXLB-encode ( 00 111 0 00 0 1 1 Rs 0 110 00 Rn Rt -- )
-
-! LDUMAXH, LDUMAXAH, LDUMAXALH, LDUMAXLH: Atomic unsigned maximum on halfword in memory.
-! ARMv8.1
-ARM-INSTRUCTION: LDUMAXAH-encode ( 01 111 0 00 1 0 1 Rs 0 110 00 Rn Rt -- )
-ARM-INSTRUCTION: LDUMAXALH-encode ( 01 111 0 00 1 1 1 Rs 0 110 00 Rn Rt -- )
-ARM-INSTRUCTION: LDUMAXH-encode ( 01 111 0 00 0 0 1 Rs 0 110 00 Rn Rt -- )
-ARM-INSTRUCTION: LDUMAXLH-encode ( 01 111 0 00 0 1 1 Rs 0 110 00 Rn Rt -- )
-
-! LDUMIN, LDUMINA, LDUMINAL, LDUMINL: Atomic unsigned minimum on word or doubleword in memory.
-! ARMv8.1
-ARM-INSTRUCTION: LDUMIN32-encode ( 10 111 0 00 0 0 1 Rs 0 111 00 Rn Rt -- )
-ARM-INSTRUCTION: LDUMINA32-encode ( 10 111 0 00 1 0 1 Rs 0 111 00 Rn Rt -- )
-ARM-INSTRUCTION: LDUMINAL32-encode ( 10 111 0 00 1 1 1 Rs 0 111 00 Rn Rt -- )
-ARM-INSTRUCTION: LDUMINL32-encode ( 10 111 0 00 0 1 1 Rs 0 111 00 Rn Rt -- )
-ARM-INSTRUCTION: LDUMIN64-encode ( 11 111 0 00 0 0 1 Rs 0 111 00 Rn Rt -- )
-ARM-INSTRUCTION: LDUMINA64-encode ( 11 111 0 00 1 0 1 Rs 0 111 00 Rn Rt -- )
-ARM-INSTRUCTION: LDUMINAL64-encode ( 11 111 0 00 1 1 1 Rs 0 111 00 Rn Rt -- )
-ARM-INSTRUCTION: LDUMINL64-encode ( 11 111 0 00 0 1 1 Rs 0 111 00 Rn Rt -- )
-
-! LDUMINB, LDUMINAB, LDUMINALB, LDUMINLB: Atomic unsigned minimum on byte in memory.
-! ARMv8.1
-ARM-INSTRUCTION: LDUMINAB-encode ( 00 111 0 00 1 0 1 Rs 0 111 00 Rn Rt -- )
-ARM-INSTRUCTION: LDUMINALB-encode ( 00 111 0 00 1 1 1 Rs 0 111 00 Rn Rt -- )
-ARM-INSTRUCTION: LDUMINB-encode ( 00 111 0 00 0 0 1 Rs 0 111 00 Rn Rt -- )
-ARM-INSTRUCTION: LDUMINLB-encode ( 00 111 0 00 0 1 1 Rs 0 111 00 Rn Rt -- )
-
-! LDUMINH, LDUMINAH, LDUMINALH, LDUMINLH: Atomic unsigned minimum on halfword in memory.
-! ARMv8.1
-ARM-INSTRUCTION: LDUMINAH-encode ( 01 111 0 00 1 0 1 Rs 0 111 00 Rn Rt -- )
-ARM-INSTRUCTION: LDUMINALH-encode ( 01 111 0 00 1 1 1 Rs 0 111 00 Rn Rt -- )
-ARM-INSTRUCTION: LDUMINH-encode ( 01 111 0 00 0 0 1 Rs 0 111 00 Rn Rt -- )
-ARM-INSTRUCTION: LDUMINLH-encode ( 01 111 0 00 0 1 1 Rs 0 111 00 Rn Rt -- )
-
-! LDUR: Load Register (unscaled).
-ARM-INSTRUCTION: LDUR32-encode ( 10 111 0 00 01 0 imm9 00 Rn Rt -- )
-ARM-INSTRUCTION: LDUR64-encode ( 11 111 0 00 01 0 imm9 00 Rn Rt -- )
-
-! LDURB: Load Register Byte (unscaled).
-ARM-INSTRUCTION: LDURB-encode ( 00 111 0 00 01 0 imm9 00 Rn Rt -- )
-
-! LDURH: Load Register Halfword (unscaled).
-ARM-INSTRUCTION: LDURH-encode ( 01 111 0 00 01 0 imm9 00 Rn Rt -- )
-
-! LDURSB: Load Register Signed Byte (unscaled).
-ARM-INSTRUCTION: LDURSB32-encode ( 00 111 0 00 10 0 imm9 00 Rn Rt -- )
-ARM-INSTRUCTION: LDURSB64-encode ( 00 111 0 00 11 0 imm9 00 Rn Rt -- )
-
-! LDURSH: Load Register Signed Halfword (unscaled).
-ARM-INSTRUCTION: LDURSH32-encode ( 01 111 0 00 10 0 imm9 00 Rn Rt -- )
-ARM-INSTRUCTION: LDURSH64-encode ( 01 111 0 00 11 0 imm9 00 Rn Rt -- )
-
-! LDURSW: Load Register Signed Word (unscaled).
-ARM-INSTRUCTION: LDURSW-encode ( 10 111 0 00 10 0 imm9 00 Rn Rt -- )
-
-! LDXP: Load Exclusive Pair of Registers.
-ARM-INSTRUCTION: LDXP32-encode ( 1 0 001000 0 1 1 11111 0 Rt2 Rn Rt -- )
-ARM-INSTRUCTION: LDXP64-encode ( 1 1 001000 0 1 1 11111 0 Rt2 Rn Rt -- )
-
-! LDXR: Load Exclusive Register.
-ARM-INSTRUCTION: LDXR32-encode ( 10 001000 0 1 0 11111 0 11111 Rn Rt -- )
-ARM-INSTRUCTION: LDXR64-encode ( 11 001000 0 1 0 11111 0 11111 Rn Rt -- )
-
-! LDXRB: Load Exclusive Register Byte.
-ARM-INSTRUCTION: LDXRB-encode ( 00 001000 0 1 0 11111 0 11111 Rn Rt -- )
-
-! LDXRH: Load Exclusive Register Halfword.
-ARM-INSTRUCTION: LDXRH-encode ( 01 001000 0 1 0 11111 0 11111 Rn Rt -- )
-
-! LSL (immediate): Logical Shift Left (immediate): an alias of UBFM.
-ARM-INSTRUCTION: LSLi32-encode ( 0 10 100110 0 immrimms Rn Rd -- )
-ARM-INSTRUCTION: LSLi64-encode ( 1 10 100110 1 immrimms Rn Rd -- )
-
-! LSL (register): Logical Shift Left (register): an alias of LSLV.
-ARM-INSTRUCTION: LSLr32-encode ( 0 0 0 11010110 Rm 0010 00 Rn Rd -- )
-ARM-INSTRUCTION: LSLr64-encode ( 1 0 0 11010110 Rm 0010 00 Rn Rd -- )
-
-! LSLV: Logical Shift Left Variable.
-ARM-INSTRUCTION: LSLV32-encode ( 0 0 0 11010110 Rm 0010 00 Rn Rd -- )
-ARM-INSTRUCTION: LSLV64-encode ( 1 0 0 11010110 Rm 0010 00 Rn Rd -- )
-
-! LSR (immediate): Logical Shift Right (immediate): an alias of UBFM.
-ARM-INSTRUCTION: LSRi32-encode ( 0 10 100110 0 immr 011111 Rn Rd -- )
-ARM-INSTRUCTION: LSRi64-encode ( 1 10 100110 1 immr 111111 Rn Rd -- )
-
-! LSR (register): Logical Shift Right (register): an alias of LSRV.
-ARM-INSTRUCTION: LSRr32-encode ( 0 0 0 11010110 Rm 0010 01 Rn Rd -- )
-ARM-INSTRUCTION: LSRr64-encode ( 1 0 0 11010110 Rm 0010 01 Rn Rd -- )
-
-! LSRV: Logical Shift Right Variable.
-ARM-INSTRUCTION: LSRV32-encode ( 0 0 0 11010110 Rm 0010 01 Rn Rd -- )
-ARM-INSTRUCTION: LSRV64-encode ( 1 0 0 11010110 Rm 0010 01 Rn Rd -- )
-
-! MADD: Multiply-Add.
-ARM-INSTRUCTION: MADD32-encode ( 0 00 11011 000 Rm 0 Ra Rn Rd -- )
-ARM-INSTRUCTION: MADD64-encode ( 1 00 11011 000 Rm 0 Ra Rn Rd -- )
-
-! MNEG: Multiply-Negate: an alias of MSUB.
-ARM-INSTRUCTION: MNEG32-encode ( 0 00 11011 000 Rm 1 11111 Rn Rd -- )
-ARM-INSTRUCTION: MNEG64-encode ( 1 00 11011 000 Rm 1 11111 Rn Rd -- )
-
-! MOV (bitmask immediate): Move (bitmask immediate): an alias of ORR (immediate).
-ARM-INSTRUCTION: MOVbi32-encode ( 0 01 100100 0 immr imms 11111 Rn -- )
-ARM-INSTRUCTION: MOVbi64-encode ( 1 01 100100 Nimmrimms 11111 Rn -- )
-
-! MOV (inverted wide immediate): Move (inverted wide immediate): an alias of MOVN.
-ARM-INSTRUCTION: MOViwi32-encode ( 0 00 100101 hw2 imm16 Rd -- )
-ARM-INSTRUCTION: MOViwi64-encode ( 1 00 100101 hw2 imm16 Rd -- )
-
-! MOV (register): Move (register): an alias of ORR (shifted register).
-ARM-INSTRUCTION: MOVr32-encode ( 0 01 01010 00 0 Rm 000000 11111 Rd -- )
-ARM-INSTRUCTION: MOVr64-encode ( 1 01 01010 00 0 Rm 000000 11111 Rd -- )
-
-! MOV (to/from SP): Move between register and stack pointer: an alias of ADD (immediate).
-ARM-INSTRUCTION: MOVsp32-encode ( 0 0 0 10001 shift2 000000000000 Rn Rd -- )
-ARM-INSTRUCTION: MOVsp64-encode ( 1 0 0 10001 shift2 000000000000 Rn Rd -- )
-
-! MOV (wide immediate): Move (wide immediate): an alias of MOVZ.
-ARM-INSTRUCTION: MOVwi32-encode ( 0 10 100101 hw2 imm16 Rd -- )
-ARM-INSTRUCTION: MOVwi64-encode ( 1 10 100101 hw2 imm16 Rd -- )
-
-! MOVK: Move wide with keep.
-ARM-INSTRUCTION: MOVK32-encode ( 0 11 100101 hw2 imm16 Rd -- )
-ARM-INSTRUCTION: MOVK64-encode ( 1 11 100101 hw2 imm16 Rd -- )
-
-! MOVN: Move wide with NOT.
-ARM-INSTRUCTION: MOVN32-encode ( 0 00 100101 hw2 imm16 Rd -- )
-ARM-INSTRUCTION: MOVN64-encode ( 1 00 100101 hw2 imm16 Rd -- )
-
-! MOVZ: Move wide with zero.
-ARM-INSTRUCTION: MOVZ32-encode ( 0 10 100101 hw2 imm16 Rd -- )
-ARM-INSTRUCTION: MOVZ64-encode ( 1 10 100101 hw2 imm16 Rd -- )
-
-! MRS: Move System Register.
-! System register name, encoded in the "o0:op1:CRn:CRm:op2"
-ARM-INSTRUCTION: MRS-encode ( 1101010100 1 op2 op3 CRn CRm op3 Rt -- )
-
-! MSR (immediate): Move immediate value to Special Register.
-ARM-INSTRUCTION: MSRi-encode ( 1101010100 0 00 op3 0100 CRm op3 11111 -- )
-
-! MSR (register): Move general-purpose register to System Register.
-ARM-INSTRUCTION: MSRr-encode ( 1101010100 0 op2 op3 CRn CRm op3 Rt -- )
-
-! MSUB: Multiply-Subtract.
-ARM-INSTRUCTION: MSUB32-encode ( 0 00 11011 000 Rm 1 Ra Rn Rd -- )
-ARM-INSTRUCTION: MSUB64-encode ( 1 00 11011 000 Rm 1 Ra Rn Rd -- )
-
-! MUL: Multiply: an alias of MADD.
-ARM-INSTRUCTION: MUL32-encode ( 0 00 11011 000 Rm 0 11111 Rn Rd -- )
-ARM-INSTRUCTION: MUL64-encode ( 1 00 11011 000 Rm 0 11111 Rn Rd -- )
-
-! MVN: Bitwise NOT: an alias of ORN (shifted register).
-ARM-INSTRUCTION: MVN32-encode ( 0 0 1 01010 shift2 1 Rm imm6 11111 Rd -- )
-ARM-INSTRUCTION: MVN64-encode ( 1 0 1 01010 shift2 1 Rm imm6 11111 Rd -- )
-
-! NEG (shifted register): Negate (shifted register): an alias of SUB (shifted register).
-ARM-INSTRUCTION: NEG32-encode ( 0 1 0 01011 shift2 0 Rm imm6 11111 Rd -- )
-ARM-INSTRUCTION: NEG64-encode ( 1 1 0 01011 shift2 0 Rm imm6 11111 Rd -- )
-
-! NEGS: Negate, setting flags: an alias of SUBS (shifted register).
-ARM-INSTRUCTION: NEGS32-encode ( 0 1 1 01011 shift2 0 Rm imm6 11111 Rd -- )
-ARM-INSTRUCTION: NEGS64-encode ( 1 1 1 01011 shift2 0 Rm imm6 11111 Rd -- )
-
-! NGC: Negate with Carry: an alias of SBC.
-ARM-INSTRUCTION: NGC32-encode ( 0 1 0 11010000 Rm 000000 11111 Rd -- )
-ARM-INSTRUCTION: NGC64-encode ( 1 1 0 11010000 Rm 000000 11111 Rd -- )
-
-! NGCS: Negate with Carry, setting flags: an alias of SBCS.
-ARM-INSTRUCTION: NGCS32-encode ( 0 1 1 11010000 Rm 000000 11111 Rd -- )
-ARM-INSTRUCTION: NGCS64-encode ( 1 1 1 11010000 Rm 000000 11111 Rd -- )
-
-! NOP: No Operation.
-ARM-INSTRUCTION: NOP ( 1101010100 0 00 011 0010 0000 000 11111 -- )
-
-! ORN (shifted register): Bitwise OR NOT (shifted register).
-ARM-INSTRUCTION: ORNsr32-encode ( 0 01 01010 shift2 1 Rm imm6 Rn Rd -- )
-ARM-INSTRUCTION: ORNsr64-encode ( 1 01 01010 shift2 1 Rm imm6 Rn Rd -- )
-
-! ORR (immediate): Bitwise OR (immediate).
-ARM-INSTRUCTION: ORRi32-encode ( 0 01 100100 0 immrimms Rn Rd -- )
-ARM-INSTRUCTION: ORRi64-encode ( 1 01 100100 Nimmrimms Rn Rd -- )
-
-! ORR (shifted register): Bitwise OR (shifted register).
-ARM-INSTRUCTION: ORRsr32-encode ( 0 01 01010 shift2 0 Rm imm6 Rn Rd -- )
-ARM-INSTRUCTION: ORRsr64-encode ( 1 01 01010 shift2 0 Rm imm6 Rn Rd -- )
-
-! PACDA, PACDZA: Pointer Authentication Code for Data address, using key A.
-! ARMv8.3
-ARM-INSTRUCTION: PACDA-encode ( 1 1 0 11010110 00001 0 0 0 010 Rn Rd -- )
-ARM-INSTRUCTION: PACDZA-encode ( 1 1 0 11010110 00001 0 0 1 010 11111 Rd -- )
-
-! PACDB, PACDZB: Pointer Authentication Code for Data address, using key B.
-! ARMv8.3
-ARM-INSTRUCTION: PACDB-encode ( 1 1 0 11010110 00001 0 0 0 011 Rn Rd -- )
-ARM-INSTRUCTION: PACDZB-encode ( 1 1 0 11010110 00001 0 0 1 011 11111 Rd -- )
-
-! PACGA: Pointer Authentication Code, using Generic key.
-! ARMv8.3
-ARM-INSTRUCTION: PACGA-encode ( 1 0 0 11010110 Rm 001100 Rn Rd -- )
-
-! PACIA, PACIA1716, PACIASP, PACIAZ, PACIZA: Pointer Authentication Code for Instruction address, using key A.
-! ARMv8.3
-ARM-INSTRUCTION: PACIA-encode ( 1 1 0 11010110 00001 0 0 0 000 Rn Rd -- )
-ARM-INSTRUCTION: PACIZA-encode ( 1 1 0 11010110 00001 0 0 1 000 Rn Rd -- )
-! ARMv8.3
-ARM-INSTRUCTION: PACIA1716-encode ( 1101010100 0 00 011 0010 0001 000 11111 -- )
-ARM-INSTRUCTION: PACIASP-encode ( 1101010100 0 00 011 0010 0011 001 11111 -- )
-ARM-INSTRUCTION: PACIAZ-encode ( 1101010100 0 00 011 0010 0011 000 11111 -- )
-
-! PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZB: Pointer Authentication Code for Instruction address, using key B.
-! ARMv8.3
-ARM-INSTRUCTION: PACIB-encode ( 1 1 0 11010110 00001 0 0 0 001 Rn Rd -- )
-ARM-INSTRUCTION: PACIZB-encode ( 1 1 0 11010110 00001 0 0 1 001 Rn Rd -- )
-! ARMv8.3
-ARM-INSTRUCTION: PACIB1716-encode ( 1101010100 0 00 011 0010 0001 010 11111 -- )
-ARM-INSTRUCTION: PACIBSP-encode ( 1101010100 0 00 011 0010 0011 011 11111 -- )
-ARM-INSTRUCTION: PACIBZ-encode ( 1101010100 0 00 011 0010 0011 010 11111 -- )
-
-! PRFM (immediate): Prefetch Memory (immediate).
-ARM-INSTRUCTION: PRFMi-encode ( 11 111 0 01 10 imm12 Rn Rt -- )
-
-! PRFM (literal): Prefetch Memory (literal).
-ARM-INSTRUCTION: PRFMl-encode ( 11 011 0 00 imm19 Rt -- )
-
-! PRFM (register): Prefetch Memory (register).
-ARM-INSTRUCTION: PRFMr-encode ( 11 111 0 00 10 1 Rm option3 S 10 Rn Rt -- )
-
-! PRFM (unscaled offset): Prefetch Memory (unscaled offset).
-ARM-INSTRUCTION: PRFMunscoff-encode ( 11 111 0 00 10 0 imm9 00 Rn Rt -- )
-
-! PSB CSYNC: Profiling Synchronization Barrier.
-! ARMv8.2
-ARM-INSTRUCTION: PSB-CSYNC-encode ( 1101010100 0 00 011 0010 0010 001 11111 -- )
-
-! PSSBB: Physical Speculative Store Bypass Barrier.
-ARM-INSTRUCTION: PSSBB-encode ( 1101010100 0 00 011 0011 0100 1 00 11111 -- )
-
-! RBIT: Reverse Bits.
-ARM-INSTRUCTION: RBIT32-encode ( 0 1 0 11010110 00000 0000 00 Rn Rd -- )
-ARM-INSTRUCTION: RBIT64-encode ( 1 1 0 11010110 00000 0000 00 Rn Rd -- )
-
-! RET: Return from subroutine.
-ARM-INSTRUCTION: RET-encode ( 1101011 0 0 10 11111 0000 0 0 Rn 00000 -- )
-
-! RETAA, RETAB: Return from subroutine, with pointer authentication.
-! ARMv8.3
-ARM-INSTRUCTION: RETAA-encode ( 1101011 0 0 10 11111 0000 1 0 11111 11111 -- )
-ARM-INSTRUCTION: RETAB-encode ( 1101011 0 0 10 11111 0000 1 1 11111 11111 -- )
-
-! REV: Reverse Bytes.
-ARM-INSTRUCTION: REVb32-encode ( 0 1 0 11010110 00000 0000 10 Rn Rd -- )
-ARM-INSTRUCTION: REVb64-encode ( 1 1 0 11010110 00000 0000 11 Rn Rd -- )
-
-! REV16: Reverse bytes in 16-bit halfwords.
-ARM-INSTRUCTION: REV16_32 ( 0 1 0 11010110 00000 0000 01 Rn Rd -- )
-ARM-INSTRUCTION: REV16_64 ( 1 1 0 11010110 00000 0000 01 Rn Rd -- )
-
-! REV32: Reverse bytes in 32-bit words.
-ARM-INSTRUCTION: REV32-encode ( 1 1 0 11010110 00000 0000 10 Rn Rd -- )
-
-! REV64: Reverse Bytes: an alias of REV.
-ARM-INSTRUCTION: REV64-encode ( 0 Q 0 01110 size2 10000 0000 0 10 Rn Rd -- )
-
-! RMIF: Rotate, Mask Insert Flags.
-! ARMv8.4
-ARM-INSTRUCTION: RMIF-encode ( 1 0 1 11010000 imm6 00001 Rn 0 mask4 -- )
-
-! ROR (immediate): Rotate right (immediate): an alias of EXTR.
-ARM-INSTRUCTION: RORi32-encode ( 0 00 100111 0 0 Rm 0 imm5 Rn Rd -- )
-ARM-INSTRUCTION: RORi64-encode ( 1 00 100111 1 0 Rm imms Rn Rd -- )
-
-! ROR (register): Rotate Right (register): an alias of RORV.
-ARM-INSTRUCTION: RORr32-encode ( 0 0 0 11010110 Rm 0010 11 Rn Rd -- )
-ARM-INSTRUCTION: RORr64-encode ( 1 0 0 11010110 Rm 0010 11 Rn Rd -- )
-
-! RORV: Rotate Right Variable.
-ARM-INSTRUCTION: RORV32-encode ( 0 0 0 11010110 Rm 0010 11 Rn Rd -- )
-ARM-INSTRUCTION: RORV64-encode ( 1 0 0 11010110 Rm 0010 11 Rn Rd -- )
-
-! SB: Speculation Barrier.
-ARM-INSTRUCTION: SB-encode ( 1101010100 0 00 011 0011 0000 1 11 11111 -- )
-
-! SBC: Subtract with Carry.
-ARM-INSTRUCTION: SBC32-encode ( 0 1 0 11010000 Rm 000000 Rn Rd -- )
-ARM-INSTRUCTION: SBC64-encode ( 1 1 0 11010000 Rm 000000 Rn Rd -- )
-
-! SBCS: Subtract with Carry, setting flags.
-ARM-INSTRUCTION: SBCS32-encode ( 0 1 1 11010000 Rm 000000 Rn Rd -- )
-ARM-INSTRUCTION: SBCS64-encode ( 1 1 1 11010000 Rm 000000 Rn Rd -- )
-
-! SBFIZ: Signed Bitfield Insert in Zero: an alias of SBFM.
-ARM-INSTRUCTION: SBFIZ32-encode ( 0 00 100110 0 immr imms Rn Rd -- )
-ARM-INSTRUCTION: SBFIZ64-encode ( 1 00 100110 1 immr imms Rn Rd -- )
-
-! SBFM: Signed Bitfield Move.
-ARM-INSTRUCTION: SBFM32-encode ( 0 00 100110 0 immr imms Rn Rd -- )
-ARM-INSTRUCTION: SBFM64-encode ( 1 00 100110 1 immr imms Rn Rd -- )
-
-! SBFX: Signed Bitfield Extract: an alias of SBFM.
-ARM-INSTRUCTION: SBFX32-encode ( 0 00 100110 0 immr imms Rn Rd -- )
-ARM-INSTRUCTION: SBFX64-encode ( 1 00 100110 1 immr imms Rn Rd -- )
-
-! SCVTF (scalar, integer): Signed integer Convert to Floting-point (scalar).
-ARM-INSTRUCTION: SCVTFsi64-encode ( 1 0 0 11110 ftype 1 00 010 000000 Rn Rd -- )
-
-! SDIV: Signed Divide.
-ARM-INSTRUCTION: SDIV32-encode ( 0 0 0 11010110 Rm 00001 1 Rn Rd -- )
-ARM-INSTRUCTION: SDIV64-encode ( 1 0 0 11010110 Rm 00001 1 Rn Rd -- )
-
-! SETF8, SETF16: Evaluation of 8 or 16 bit flag values.
-! ARMv8.4
-ARM-INSTRUCTION: SETF8-encode ( 0 0 1 11010000 000000 0 0010 Rn 0 1101 -- )
-ARM-INSTRUCTION: SETF16-encode ( 0 0 1 11010000 000000 1 0010 Rn 0 1101 -- )
-
-! SEV: Send Event.
-ARM-INSTRUCTION: SEV-encode ( 1101010100 0 00 011 0010 0000 100 11111 -- )
-
-! SEVL: Send Event Local.
-ARM-INSTRUCTION: SEVL-encode ( 1101010100 0 00 011 0010 0000 101 11111 -- )
-
-! SMADDL: Signed Multiply-Add Long.
-ARM-INSTRUCTION: SMADDL-encode ( 1 00 11011 0 01 Rm 0 Ra Rn Rd -- )
-
-! SMC: Secure Monitor Call.
-ARM-INSTRUCTION: SMC-encode ( 11010100 000 imm16 000 11 -- )
-
-! SMNEGL: Signed Multiply-Negate Long: an alias of SMSUBL.
-ARM-INSTRUCTION: SMNEGL-encode ( 1 00 11011 0 01 Rm 1 11111 Rn Rd -- )
-
-! SMSUBL: Signed Multiply-Subtract Long.
-ARM-INSTRUCTION: SMSUBL-encode ( 1 00 11011 0 01 Rm 1 Ra Rn Rd -- )
-
-! SMULH: Signed Multiply High.
-ARM-INSTRUCTION: SMULH-encode ( 1 00 11011 0 10 Rm 0 11111 Rn Rd -- )
-
-! SMULL: Signed Multiply Long: an alias of SMADDL.
-ARM-INSTRUCTION: SMULL-encode ( 1 00 11011 0 01 Rm 0 11111 Rn Rd -- )
-
-! SSBB: Speculative Store Bypass Barrier.
-ARM-INSTRUCTION: SSBB-encode ( 1101010100 0 00 011 0011 0000 1 00 11111 -- )
-
-! ST2G: Store Allocation Tags.
-! ARMv8.5
-ARM-INSTRUCTION: ST2Gpost-encode ( 11011001 1 0 1 imm9 0 1 Xn 11111 -- )
-ARM-INSTRUCTION: ST2Gpre-encode ( 11011001 1 0 1 imm9 1 1 Xn 11111 -- )
-ARM-INSTRUCTION: ST2Gsoff-encode ( 11011001 1 0 1 imm9 1 0 Xn 11111 -- )
-
-! STADD, STADDL: Atomic add on word or doubleword in memory, without return: an alias of LDADD, LDADDA, LDADDAL, LDADDL.
-ARM-INSTRUCTION: STADD32-encode ( 10 111 0 00 0 0 1 Rs 0 000 00 Rn 11111 -- )
-ARM-INSTRUCTION: STADDL32-encode ( 10 111 0 00 0 1 1 Rs 0 000 00 Rn 11111 -- )
-ARM-INSTRUCTION: STADD64-encode ( 11 111 0 00 0 0 1 Rs 0 000 00 Rn 11111 -- )
-ARM-INSTRUCTION: STADDL64-encode ( 11 111 0 00 0 1 1 Rs 0 000 00 Rn 11111 -- )
-
-! STADDB, STADDLB: Atomic add on byte in memory, without return: an alias of LDADDB, LDADDAB, LDADDALB, LDADDLB.
-! ARMv8.1
-ARM-INSTRUCTION: STADDB-encode ( 00 111 0 00 0 0 1 Rs 0 000 00 Rn 11111 -- )
-ARM-INSTRUCTION: STADDLB-encode ( 00 111 0 00 0 1 1 Rs 0 000 00 Rn 11111 -- )
-
-! STADDH, STADDLH: Atomic add on halfword in memory, without return: an alias of LDADDH, LDADDAH, LDADDALH, LDADDLH.
-ARM-INSTRUCTION: STADDH-encode ( 01 111 0 00 0 0 1 Rs 0 000 00 Rn 11111 -- )
-ARM-INSTRUCTION: STADDLH-encode ( 01 111 0 00 0 1 1 Rs 0 000 00 Rn 11111 -- )
-
-! STCLR, STCLRL: Atomic bit clear on word or doubleword in memory, without return: an alias of LDCLR, LDCLRA, LDCLRAL, LDCLRL.
-! ARMv8.1
-ARM-INSTRUCTION: STCLR32-encode ( 10 111 0 00 0 0 1 Rs 0 001 00 Rn 11111 -- )
-ARM-INSTRUCTION: STCLR64-encode ( 10 111 0 00 0 1 1 Rs 0 001 00 Rn 11111 -- )
-ARM-INSTRUCTION: STCLRL32-encode ( 11 111 0 00 0 0 1 Rs 0 001 00 Rn 11111 -- )
-ARM-INSTRUCTION: STCLRL64-encode ( 11 111 0 00 0 1 1 Rs 0 001 00 Rn 11111 -- )
-
-! STCLRB, STCLRLB: Atomic bit clear on byte in memory, without return: an alias of LDCLRB, LDCLRAB, LDCLRALB, LDCLRLB.
-! ARMv8.1
-ARM-INSTRUCTION: STCLRB-encode ( 00 111 0 00 0 0 1 Rs 0 001 00 Rn 11111 -- )
-ARM-INSTRUCTION: STCLRLB-encode ( 00 111 0 00 0 1 1 Rs 0 001 00 Rn 11111 -- )
-
-! STCLRH, STCLRLH: Atomic bit clear on halfword in memory, without return: an alias of LDCLRH, LDCLRAH, LDCLRALH, LDCLRLH.
-! ARMv8.1
-ARM-INSTRUCTION: STCLRH-encode ( 01 111 0 00 0 0 1 Rs 0 001 00 Rn 11111 -- )
-ARM-INSTRUCTION: STCLRLH-encode ( 01 111 0 00 0 1 1 Rs 0 001 00 Rn 11111 -- )
-
-! STEOR, STEORL: Atomic exclusive OR on word or doubleword in memory, without return: an alias of LDEOR, LDEORA, LDEORAL, LDEORL.
-! ARMv8.1
-ARM-INSTRUCTION: STEOR32-encode ( 10 111 0 00 0 0 1 Rs 0 010 00 Rn 11111 -- )
-ARM-INSTRUCTION: STEORL32-encode ( 10 111 0 00 0 1 1 Rs 0 010 00 Rn 11111 -- )
-ARM-INSTRUCTION: STEOR64-encode ( 11 111 0 00 0 0 1 Rs 0 010 00 Rn 11111 -- )
-ARM-INSTRUCTION: STEORL64-encode ( 11 111 0 00 0 1 1 Rs 0 010 00 Rn 11111 -- )
-
-! STEORB, STEORLB: Atomic exclusive OR on byte in memory, without return: an alias of LDEORB, LDEORAB, LDEORALB, LDEORLB.
-! ARMv8.1
-ARM-INSTRUCTION: STEORB-encode ( 00 111 0 00 0 0 1 Rs 0 010 00 Rn 11111 -- )
-ARM-INSTRUCTION: STEORLB-encode ( 00 111 0 00 0 1 1 Rs 0 010 00 Rn 11111 -- )
-
-! STEORH, STEORLH: Atomic exclusive OR on halfword in memory, without return: an alias of LDEORH, LDEORAH, LDEORALH, LDEORLH.
-! ARMv8.1
-ARM-INSTRUCTION: STEORH-encode ( 01 111 0 00 0 0 1 Rs 0 010 00 Rn 11111 -- )
-ARM-INSTRUCTION: STEORLH-encode ( 01 111 0 00 0 1 1 Rs 0 010 00 Rn 11111 -- )
-
-! STG: Store Allocation Tag.
-! ARMv8.5
-ARM-INSTRUCTION: STGpost-encode ( 11011001 0 0 1 imm9 0 1 Xn 11111 -- )
-ARM-INSTRUCTION: STGpre-encode ( 11011001 0 0 1 imm9 1 1 Xn 11111 -- )
-ARM-INSTRUCTION: STGsoff-encode ( 11011001 0 0 1 imm9 1 0 Xn 11111 -- )
-
-! STGP: Store Allocation Tag and Pair of registers.
-! ARMv8.5
-ARM-INSTRUCTION: STGPpost-encode ( 0 1 101 0 001 0 simm7 Xt2 Xn Xt -- )
-ARM-INSTRUCTION: STGPpre-encode ( 0 1 101 0 011 0 simm7 Xt2 Xn Xt -- )
-ARM-INSTRUCTION: STGPsoff-encode ( 0 1 101 0 010 0 simm7 Xt2 Xn Xt -- )
-
-! STGV: Store Tag Vector.
-! ARMv8.5
-ARM-INSTRUCTION: STGV-encode ( 11011001 1 0 1 0 0 0 0 0 0 0 0 0 0 0 Xn Xt -- )
-
-! STLLR: Store LORelease Register.
-! ARMv8.1
-ARM-INSTRUCTION: STLLR32-encode ( 10 001000 1 0 0 11111 0 11111 Rn Rt -- )
-ARM-INSTRUCTION: STLLR64-encode ( 11 001000 1 0 0 11111 0 11111 Rn Rt -- )
-
-! STLLRB: Store LORelease Register Byte.
-! ARMv8.1
-ARM-INSTRUCTION: STLLRB-encode ( 00 001000 1 0 0 11111 0 11111 Rn Rt -- )
-
-! STLLRH: Store LORelease Register Halfword.
-ARM-INSTRUCTION: STLLRH-encode ( 01 001000 1 0 0 11111 0 11111 Rn Rt -- )
-
-! STLR: Store-Release Register.
-ARM-INSTRUCTION: STLR32-encode ( 10 001000 1 0 0 11111 1 11111 Rn Rt -- )
-ARM-INSTRUCTION: STLR64-encode ( 11 001000 1 0 0 11111 1 11111 Rn Rt -- )
-
-! STLRB: Store-Release Register Byte.
-ARM-INSTRUCTION: STLRB-encode ( 00 001000 1 0 0 11111 1 11111 Rn Rt -- )
-
-! STLRH: Store-Release Register Halfword.
-ARM-INSTRUCTION: STLRH-encode ( 01 001000 1 0 0 11111 1 11111 Rn Rt -- )
-
-! STLUR: Store-Release Register (unscaled).
-ARM-INSTRUCTION: STLUR32-encode ( 10 011001 00 0 imm9 00 Rn Rt -- )
-ARM-INSTRUCTION: STLUR64-encode ( 11 011001 00 0 imm9 00 Rn Rt -- )
-
-! STLURB: Store-Release Register Byte (unscaled).
-ARM-INSTRUCTION: STLURB-encode ( 00 011001 00 0 imm9 00 Rn Rt -- )
-
-! STLURH: Store-Release Register Halfword (unscaled).
-ARM-INSTRUCTION: STLURH-encode ( 01 011001 00 0 imm9 00 Rn Rt -- )
-
-! STLXP: Store-Release Exclusive Pair of registers.
-ARM-INSTRUCTION: STLXP32-encode ( 1 0 001000 0 0 1 Rs 1 Rt2 Rn Rt -- )
-ARM-INSTRUCTION: STLXP64-encode ( 1 1 001000 0 0 1 Rs 1 Rt2 Rn Rt -- )
-
-! STLXR: Store-Release Exclusive Register.
-ARM-INSTRUCTION: STLXR32-encode ( 10 001000 0 0 0 Rs 1 11111 Rn Rt -- )
-ARM-INSTRUCTION: STLXR64-encode ( 11 001000 0 0 0 Rs 1 11111 Rn Rt -- )
-
-! STLXRB: Store-Release Exclusive Register Byte.
-ARM-INSTRUCTION: STLXRB-encode ( 00 001000 0 0 0 Rs 1 11111 Rn Rt -- )
-
-! STLXRH: Store-Release Exclusive Register Halfword.
-ARM-INSTRUCTION: STLXRH-encode ( 01 001000 0 0 0 Rs 1 11111 Rn Rt -- )
-
-! STNP: Store Pair of Registers, with non-temporal hint.
-ARM-INSTRUCTION: STNP32-encode ( 00 101 0 000 0 imm7 Rt2 Rn Rt -- )
-ARM-INSTRUCTION: STNP64-encode ( 10 101 0 000 0 imm7 Rt2 Rn Rt -- )
-
-! STP: Store Pair of Registers.
-ARM-INSTRUCTION: STPpost32-encode ( 00 101 0 001 0 imm7 Rt2 Rn Rt -- )
-ARM-INSTRUCTION: STPpost64-encode ( 10 101 0 001 0 imm7 Rt2 Rn Rt -- )
-ARM-INSTRUCTION: STPpre32-encode ( 00 101 0 011 0 imm7 Rt2 Rn Rt -- )
-ARM-INSTRUCTION: STPpre64-encode ( 10 101 0 011 0 imm7 Rt2 Rn Rt -- )
-ARM-INSTRUCTION: STPsoff32-encode ( 00 101 0 010 0 imm7 Rt2 Rn Rt -- )
-ARM-INSTRUCTION: STPsoff64-encode ( 10 101 0 010 0 imm7 Rt2 Rn Rt -- )
-
-! STR (immediate): Store Register (immediate).
-ARM-INSTRUCTION: STRpost32-encode ( 10 111 0 00 00 0 imm9 01 Rn Rt -- )
-ARM-INSTRUCTION: STRpost64-encode ( 11 111 0 00 00 0 imm9 01 Rn Rt -- )
-ARM-INSTRUCTION: STRpre32-encode ( 10 111 0 00 00 0 imm9 11 Rn Rt -- )
-ARM-INSTRUCTION: STRpre64-encode ( 11 111 0 00 00 0 imm9 11 Rn Rt -- )
-ARM-INSTRUCTION: STRuoff32-encode ( 10 111 0 01 00 imm12 Rn Rt -- )
-ARM-INSTRUCTION: STRuoff64-encode ( 11 111 0 01 00 imm12 Rn Rt -- )
-
-! STR (register): Store Register (register).
-ARM-INSTRUCTION: STRr32-encode ( 10 111 0 00 00 1 Rm option3 S 10 Rn Rt -- )
-ARM-INSTRUCTION: STRr64-encode ( 11 111 0 00 00 1 Rm option3 S 10 Rn Rt -- )
-
-! STRB (immediate): Store Register Byte (immediate).
-ARM-INSTRUCTION: STRBpost-encode ( 00 111 0 00 00 0 imm9 01 Rn Rt -- )
-ARM-INSTRUCTION: STRBpre-encode ( 00 111 0 00 00 0 imm9 11 Rn Rt -- )
-ARM-INSTRUCTION: STRBuoff-encode ( 00 111 0 01 00 imm12 Rn Rt -- )
-
-! STRB (register): Store Register Byte (register).
-ARM-INSTRUCTION: STRBer-encode ( 00 111 0 00 00 1 Rm option3 S 10 Rn Rt -- )
-ARM-INSTRUCTION: STRBsr-encode ( 00 111 0 00 00 1 Rm 011 S 10 Rn Rt -- )
-
-! STRH (immediate): Store Register Halfword (immediate).
-ARM-INSTRUCTION: STRHpost-encode ( 01 111 0 00 00 0 imm9 01 Rn Rt -- )
-ARM-INSTRUCTION: STRHpre-encode ( 01 111 0 00 00 0 imm9 11 Rn Rt -- )
-ARM-INSTRUCTION: STRHuoff-encode ( 01 111 0 01 00 imm12 Rn Rt -- )
-
-! STRH (register): Store Register Halfword (register).
-ARM-INSTRUCTION: STRHr-encode ( 01 111 0 00 00 1 Rm option3 S 10 Rn Rt -- )
-
-! STSET, STSETL: Atomic bit set on word or doubleword in memory, without return: an alias of LDSET, LDSETA, LDSETAL, LDSETL.
-! ARMv8.1
-ARM-INSTRUCTION: STSET32-encode ( 10 111 0 00 0 0 1 Rs 0 011 00 Rn 11111 -- )
-ARM-INSTRUCTION: STSETL32-encode ( 10 111 0 00 0 1 1 Rs 0 011 00 Rn 11111 -- )
-ARM-INSTRUCTION: STSET64-encode ( 11 111 0 00 0 0 1 Rs 0 011 00 Rn 11111 -- )
-ARM-INSTRUCTION: STSETL64-encode ( 11 111 0 00 0 1 1 Rs 0 011 00 Rn 11111 -- )
-
-! STSETB, STSETLB: Atomic bit set on byte in memory, without return: an alias of LDSETB, LDSETAB, LDSETALB, LDSETLB.
-! ARMv8.1
-ARM-INSTRUCTION: STSETB-encode ( 00 111 0 00 0 0 1 Rs 0 011 00 Rn 11111 -- )
-ARM-INSTRUCTION: STSETLB-encode ( 00 111 0 00 0 1 1 Rs 0 011 00 Rn 11111 -- )
-
-! STSETH, STSETLH: Atomic bit set on halfword in memory, without return: an alias of LDSETH, LDSETAH, LDSETALH, LDSETLH.
-! ARMv8.1
-ARM-INSTRUCTION: STSETH-encode ( 01 111 0 00 0 0 1 Rs 0 011 00 Rn 11111 -- )
-ARM-INSTRUCTION: STSETLH-encode ( 01 111 0 00 0 1 1 Rs 0 011 00 Rn 11111 -- )
-
-! STSMAX, STSMAXL: Atomic signed maximum on word or doubleword in memory, without return: an alias of LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL.
-! ARMv8.1
-ARM-INSTRUCTION: STSMAX32-encode ( 10 111 0 00 0 0 1 Rs 0 100 00 Rn 11111 -- )
-ARM-INSTRUCTION: STSMAXL32-encode ( 10 111 0 00 0 1 1 Rs 0 100 00 Rn 11111 -- )
-ARM-INSTRUCTION: STSMAX64-encode ( 11 111 0 00 0 0 1 Rs 0 100 00 Rn 11111 -- )
-ARM-INSTRUCTION: STSMAXL64-encode ( 11 111 0 00 0 1 1 Rs 0 100 00 Rn 11111 -- )
-
-! STSMAXB, STSMAXLB: Atomic signed maximum on byte in memory, without return: an alias of LDSMAXB, LDSMAXAB, LDSMAXALB, LDSMAXLB.
-! ARMv8.1
-ARM-INSTRUCTION: STSMAXB-encode ( 00 111 0 00 0 0 1 Rs 0 100 00 Rn 11111 -- )
-ARM-INSTRUCTION: STSMAXLB-encode ( 00 111 0 00 0 1 1 Rs 0 100 00 Rn 11111 -- )
-
-! STSMAXH, STSMAXLH: Atomic signed maximum on halfword in memory, without return: an alias of LDSMAXH, LDSMAXAH, LDSMAXALH, LDSMAXLH
-! ARMv8.1
-ARM-INSTRUCTION: STSMAXH-encode ( 01 111 0 00 0 0 1 Rs 0 100 00 Rn 11111 -- )
-ARM-INSTRUCTION: STSMAXLH-encode ( 01 111 0 00 0 1 1 Rs 0 100 00 Rn 11111 -- )
-
-! STSMIN, STSMINL: Atomic signed minimum on word or doubleword in memory, without return: an alias of LDSMIN, LDSMINA, LDSMINAL, LDSMINL.
-! ARMv8.1
-ARM-INSTRUCTION: STSMIN32-encode ( 10 111 0 00 0 0 1 Rs 0 101 00 Rn 11111 -- )
-ARM-INSTRUCTION: STSMINL32-encode ( 10 111 0 00 0 0 1 Rs 0 101 00 Rn 11111 -- )
-ARM-INSTRUCTION: STSMIN64-encode ( 11 111 0 00 0 1 1 Rs 0 101 00 Rn 11111 -- )
-ARM-INSTRUCTION: STSMINL64-encode ( 11 111 0 00 0 1 1 Rs 0 101 00 Rn 11111 -- )
-
-! STSMINB, STSMINLB: Atomic signed minimum on byte in memory, without return: an alias of LDSMINB, LDSMINAB, LDSMINALB, LDSMINLB.
-ARM-INSTRUCTION: STSMINB-encode ( 00 111 0 00 0 0 1 Rs 0 101 00 Rn 11111 -- )
-ARM-INSTRUCTION: STSMINLB-encode ( 00 111 0 00 0 1 1 Rs 0 101 00 Rn 11111 -- )
-
-! STSMINH, STSMINLH: Atomic signed minimum on halfword in memory, without return: an alias of LDSMINH, LDSMINAH, LDSMINALH, LDSMINLH.
-ARM-INSTRUCTION: STSMINH-encode ( 01 111 0 00 0 0 1 Rs 0 101 00 Rn 11111 -- )
-ARM-INSTRUCTION: STSMINLH-encode ( 01 111 0 00 0 1 1 Rs 0 101 00 Rn 11111 -- )
-
-! STTR: Store Register (unprivileged).
-ARM-INSTRUCTION: STTR32-encode ( 10 111 0 00 00 0 imm9 10 Rn Rt -- )
-ARM-INSTRUCTION: STTR64-encode ( 11 111 0 00 00 0 imm9 10 Rn Rt -- )
-
-! STTRB: Store Register Byte (unprivileged).
-ARM-INSTRUCTION: STTRB-encode ( 00 111 0 00 00 0 imm9 10 Rn Rt -- )
-
-! STTRH: Store Register Halfword (unprivileged).
-ARM-INSTRUCTION: STTRH-encode ( 01 111 0 00 00 0 imm9 10 Rn Rt -- )
-
-! STUMAX, STUMAXL: Atomic unsigned maximum on word or doubleword in memory, without return: an alias of LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL.
-! ARMv8.1
-ARM-INSTRUCTION: STUMAX32-encode ( 10 111 0 00 0 0 1 Rs 0 110 00 Rn 11111 -- )
-ARM-INSTRUCTION: STUMAXL32-encode ( 10 111 0 00 0 1 1 Rs 0 110 00 Rn 11111 -- )
-ARM-INSTRUCTION: STUMAX64-encode ( 11 111 0 00 0 0 1 Rs 0 110 00 Rn 11111 -- )
-ARM-INSTRUCTION: STUMAXL64-encode ( 11 111 0 00 0 1 1 Rs 0 110 00 Rn 11111 -- )
-
-! STUMAXB, STUMAXLB: Atomic unsigned maximum on byte in memory, without return: an alias of LDUMAXB, LDUMAXAB, LDUMAXALB, LDUMAXLB.
-ARM-INSTRUCTION: STUMAXB-encode ( 00 111 0 00 0 0 1 Rs 0 110 00 Rn 11111 -- )
-ARM-INSTRUCTION: STUMAXLB-encode ( 00 111 0 00 0 1 1 Rs 0 110 00 Rn 11111 -- )
-
-! STUMAXH, STUMAXLH: Atomic unsigned maximum on halfword in memory, without return: an alias of LDUMAXH, LDUMAXAH, LDUMAXALH, LDUMAXLH.
-ARM-INSTRUCTION: STUMAXH-encode ( 01 111 0 00 0 0 1 Rs 0 110 00 Rn 11111 -- )
-ARM-INSTRUCTION: STUMAXLH-encode ( 01 111 0 00 0 1 1 Rs 0 110 00 Rn 11111 -- )
-
-! STUMIN, STUMINL: Atomic unsigned minimum on word or doubleword in memory, without return: an alias of LDUMIN, LDUMINA, LDUMINAL, LDUMINL.
-! ARMv8.1
-ARM-INSTRUCTION: STUMIN32-encode ( 10 111 0 00 0 0 1 Rs 0 111 00 Rn 11111 -- )
-ARM-INSTRUCTION: STUMINL32-encode ( 10 111 0 00 0 1 1 Rs 0 111 00 Rn 11111 -- )
-ARM-INSTRUCTION: STUMIN64-encode ( 11 111 0 00 0 0 1 Rs 0 111 00 Rn 11111 -- )
-ARM-INSTRUCTION: STUMINL64-encode ( 11 111 0 00 0 1 1 Rs 0 111 00 Rn 11111 -- )
-
-! STUMINB, STUMINLB: Atomic unsigned minimum on byte in memory, without return: an alias of LDUMINB, LDUMINAB, LDUMINALB, LDUMINLB.
-! ARMv8.1
-ARM-INSTRUCTION: STUMINB-encode ( 00 111 0 00 0 0 1 Rs 0 111 00 Rn 11111 -- )
-ARM-INSTRUCTION: STUMINLB-encode ( 00 111 0 00 0 1 1 Rs 0 111 00 Rn 11111 -- )
-
-! STUMINH, STUMINLH: Atomic unsigned minimum on halfword in memory, without return: an alias of LDUMINH, LDUMINAH, LDUMINALH, LDUMINLH.
-ARM-INSTRUCTION: STUMINH-encode ( 01 111 0 00 0 0 1 Rs 0 111 00 Rn 11111 -- )
-ARM-INSTRUCTION: STUMINLH-encode ( 01 111 0 00 0 1 1 Rs 0 111 00 Rn 11111 -- )
-
-! STUR: Store Register (unscaled).
-ARM-INSTRUCTION: STUR32-encode ( 10 111 0 00 00 0 imm9 00 Rn Rt -- )
-ARM-INSTRUCTION: STUR64-encode ( 11 111 0 00 00 0 imm9 00 Rn Rt -- )
-
-! STURB: Store Register Byte (unscaled).
-ARM-INSTRUCTION: STURB-encode ( 00 111 0 00 00 0 imm9 00 Rn Rt -- )
-
-! STURH: Store Register Halfword (unscaled).
-ARM-INSTRUCTION: STURH-encode ( 01 111 0 00 00 0 imm9 00 Rn Rt -- )
-
-! STXP: Store Exclusive Pair of registers.
-ARM-INSTRUCTION: STXP32-encode ( 1 0 001000 0 0 1 Rs 0 Rt2 Rn Rt -- )
-ARM-INSTRUCTION: STXP64-encode ( 1 1 001000 0 0 1 Rs 0 Rt2 Rn Rt -- )
-
-! STXR: Store Exclusive Register.
-ARM-INSTRUCTION: STXR32-encode ( 10 001000 0 0 0 Rs 0 11111 Rn Rt -- )
-ARM-INSTRUCTION: STXR64-encode ( 11 001000 0 0 0 Rs 0 11111 Rn Rt -- )
-
-! STXRB: Store Exclusive Register Byte.
-ARM-INSTRUCTION: STXRB-encode ( 00 001000 0 0 0 Rs 0 11111 Rn Rt -- )
-
-! STXRH: Store Exclusive Register Halfword.
-ARM-INSTRUCTION: STXRH-encode ( 01 001000 0 0 0 Rs 0 11111 Rn Rt -- )
-
-! STZ2G: Store Allocation Tags, Zeroing.
-! ARMv8.5
-ARM-INSTRUCTION: STZ2Gpost-encode ( 11011001 1 1 1 imm9 0 1 Xn 11111 -- )
-ARM-INSTRUCTION: STZ2Gpre-encode ( 11011001 1 1 1 imm9 1 1 Xn 11111 -- )
-ARM-INSTRUCTION: STZ2Gsoff-encode ( 11011001 1 1 1 imm9 1 0 Xn 11111 -- )
-
-! STZG: Store Allocation Tag, Zeroing.
-! ARMv8.5
-ARM-INSTRUCTION: STZGpost-encode ( 11011001 0 1 1 imm9 0 1 Xn 11111 -- )
-ARM-INSTRUCTION: STZGpre-encode ( 11011001 0 1 1 imm9 1 1 Xn 11111 -- )
-ARM-INSTRUCTION: STZGsoff-encode ( 11011001 0 1 1 imm9 1 0 Xn 11111 -- )
-
-! SUB (extended register): Subtract (extended register).
-ARM-INSTRUCTION: SUBer32-encode ( 0 1 0 01011 00 1 Rm option3 imm3 Rn Rd -- )
-ARM-INSTRUCTION: SUBer64-encode ( 1 1 0 01011 00 1 Rm option3 imm3 Rn Rd -- )
-
-! SUB (immediate): Subtract (immediate).
-ARM-INSTRUCTION: SUBi32-encode ( 0 1 0 10001 shift2 imm12 Rn Rd -- )
-ARM-INSTRUCTION: SUBi64-encode ( 1 1 0 10001 shift2 imm12 Rn Rd -- )
-
-! SUB (shifted register): Subtract (shifted register).
-ARM-INSTRUCTION: SUBsr32-encode ( 0 1 0 01011 shift2 0 Rm imm6 Rn Rd -- )
-ARM-INSTRUCTION: SUBsr64-encode ( 1 1 0 01011 shift2 0 Rm imm6 Rn Rd -- )
-
-! SUBG: Subtract with Tag.
-! ARMv8.5
-ARM-INSTRUCTION: SUBG-encode ( 1 1 0 100011 0 uimm6 00 uimm4 Xn Xd -- )
-
-! SUBP: Subtract Pointer.
-! ARMv8.5
-ARM-INSTRUCTION: SUBP-encode ( 1 0 0 11010110 Xm 0 0 0 0 0 0 Xn Xd -- )
-
-! SUBPS: Subtract Pointer, setting Flags.
-! ARMv8.5
-ARM-INSTRUCTION: SUBPS-encode ( 1 0 1 11010110 Xm 0 0 0 0 0 0 Xn Xd -- )
-
-! SUBS (extended register): Subtract (extended register), setting flags.
-ARM-INSTRUCTION: SUBSer32-encode ( 0 1 1 01011 00 1 Rm option3 imm3 Rn Rd -- )
-ARM-INSTRUCTION: SUBSer64-encode ( 1 1 1 01011 00 1 Rm option3 imm3 Rn Rd -- )
-
-! SUBS (immediate): Subtract (immediate), setting flags.
-ARM-INSTRUCTION: SUBSimm32-encode ( 0 1 1 10001 shift2 imm12 Rn Rd -- )
-ARM-INSTRUCTION: SUBSimm64-encode ( 1 1 1 10001 shift2 imm12 Rn Rd -- )
-
-! SUBS (shifted register): Subtract (shifted register), setting flags.
-ARM-INSTRUCTION: SUBSsr32-encode ( 0 1 1 01011 shift2 0 Rm imm6 Rn Rd -- )
-ARM-INSTRUCTION: SUBSsr64-encode ( 1 1 1 01011 shift2 0 Rm imm6 Rn Rd -- )
-
-! SVC: Supervisor Call.
-ARM-INSTRUCTION: SVC-encode ( 11010100 000 imm16 000 01 -- )
-
-! SWP, SWPA, SWPAL, SWPL: Swap word or doubleword in memory
-! ARMv8.1
-ARM-INSTRUCTION: SWP32-encode ( 10 111 0 00 0 0 1 Rs 1 000 00 Rn Rt -- )
-ARM-INSTRUCTION: SWPA32-encode ( 10 111 0 00 1 0 1 Rs 1 000 00 Rn Rt -- )
-ARM-INSTRUCTION: SWPAL32-encode ( 10 111 0 00 1 1 1 Rs 1 000 00 Rn Rt -- )
-ARM-INSTRUCTION: SWPL32-encode ( 10 111 0 00 0 1 1 Rs 1 000 00 Rn Rt -- )
-ARM-INSTRUCTION: SWP64-encode ( 11 111 0 00 0 0 1 Rs 1 000 00 Rn Rt -- )
-ARM-INSTRUCTION: SWPA64-encode ( 11 111 0 00 1 0 1 Rs 1 000 00 Rn Rt -- )
-ARM-INSTRUCTION: SWPAL64-encode ( 11 111 0 00 1 1 1 Rs 1 000 00 Rn Rt -- )
-ARM-INSTRUCTION: SWPL64-encode ( 11 111 0 00 0 1 1 Rs 1 000 00 Rn Rt -- )
-
-! SWPB, SWPAB, SWPALB, SWPLB: Swap byte in memory.
-! ARMv8.1
-ARM-INSTRUCTION: SWPAB-encode ( 00 111 0 00 1 0 1 Rs 1 000 00 Rn Rt -- )
-ARM-INSTRUCTION: SWPALB-encode ( 00 111 0 00 1 1 1 Rs 1 000 00 Rn Rt -- )
-ARM-INSTRUCTION: SWPB-encode ( 00 111 0 00 0 0 1 Rs 1 000 00 Rn Rt -- )
-ARM-INSTRUCTION: SWPLB-encode ( 00 111 0 00 0 1 1 Rs 1 000 00 Rn Rt -- )
-
-! SWPH, SWPAH, SWPALH, SWPLH: Swap halfword in memory.
-ARM-INSTRUCTION: SWPAH-encode ( 01 111 0 00 1 0 1 Rs 1 000 00 Rn Rt -- )
-ARM-INSTRUCTION: SWPALH-encode ( 01 111 0 00 1 1 1 Rs 1 000 00 Rn Rt -- )
-ARM-INSTRUCTION: SWPH-encode ( 01 111 0 00 0 0 1 Rs 1 000 00 Rn Rt -- )
-ARM-INSTRUCTION: SWPLH-encode ( 01 111 0 00 0 1 1 Rs 1 000 00 Rn Rt -- )
-
-! SXTB: Signed Extend Byte: an alias of SBFM.
-ARM-INSTRUCTION: SXTB32-encode ( 0 00 100110 0 000000 000111 Rn Rd -- )
-ARM-INSTRUCTION: SXTB64-encode ( 1 00 100110 1 000000 000111 Rn Rd -- )
-
-! SXTH: Sign Extend Halfword: an alias of SBFM.
-ARM-INSTRUCTION: SXTH32-encode ( 0 00 100110 0 000000 001111 Rn Rd -- )
-ARM-INSTRUCTION: SXTH64-encode ( 1 00 100110 1 000000 001111 Rn Rd -- )
-
-! SXTW: Sign Extend Word: an alias of SBFM.
-ARM-INSTRUCTION: SXTW-encode ( 1 00 100110 1 000000 011111 Rn Rd -- )
-
-! SYS: System instruction.
-ARM-INSTRUCTION: SYS-encode ( 1101010100 0 01 op3 CRn CRm op3 Rt -- )
-
-! SYSL: System instruction with result.
-ARM-INSTRUCTION: SYSL-encode ( 1101010100 1 01 op3 CRn CRm op3 Rt -- )
-
-! TBNZ: Test bit and Branch if Nonzero.
-ARM-INSTRUCTION: TBNZW-encode ( 0 011011 1 b40 imm14 Rt -- )
-ARM-INSTRUCTION: TBNZX-encode ( 1 011011 1 b40 imm14 Rt -- )
-
-! TBZ: Test bit and Branch if Zero.
-ARM-INSTRUCTION: TBHZW-encode ( 0 011011 0 b40 imm14 Rt -- )
-ARM-INSTRUCTION: TBHZX-encode ( 1 011011 0 b40 imm14 Rt -- )
-
-! TLBI: TLB Invalidate operation: an alias of SYS.
-ARM-INSTRUCTION: TLBI-encode ( 1101010100 0 01 op3 1000 CRm op3 Rt -- )
-
-! TSB CSYNC: Trace Synchronization Barrier.
-! ARMv8.4
-ARM-INSTRUCTION: TSB-CSYNC-encode ( 1101010100 0 00 011 0010 0010 010 11111 -- )
-
-! TST (immediate): Test bits (immediate): an alias of ANDS (immediate).
-ARM-INSTRUCTION: TSTi32-encode ( 0 11 100100 0 immrimms Rn 11111 -- )
-ARM-INSTRUCTION: TSTi64-encode ( 1 11 100100 Nimmrimms Rn 11111 -- )
-
-! TST (shifted register): Test (shifted register): an alias of ANDS (shifted register).
-ARM-INSTRUCTION: TSTsr32-encode ( 0 11 01010 shift2 0 Rm imm6 Rn 11111 -- )
-ARM-INSTRUCTION: TSTsr64-encode ( 1 11 01010 shift2 0 Rm imm6 Rn 11111 -- )
-
-! UBFIZ: Unsigned Bitfield Insert in Zero: an alias of UBFM.
-ARM-INSTRUCTION: UBFIZ32-encode ( 0 10 100110 0 immr imms Rn Rd -- )
-ARM-INSTRUCTION: UBFIZ64-encode ( 1 10 100110 1 immr imms Rn Rd -- )
-
-! UBFM: Unsigned Bitfield Move.
-ARM-INSTRUCTION: UBFM32-encode ( 0 10 100110 0 immr imms Rn Rd -- )
-ARM-INSTRUCTION: UBFM64-encode ( 1 10 100110 1 immr imms Rn Rd -- )
-
-! UBFX: Unsigned Bitfield Extract: an alias of UBFM.
-ARM-INSTRUCTION: UBFX32-encode ( 0 10 100110 0 immr imms Rn Rd -- )
-ARM-INSTRUCTION: UBFX64-encode ( 1 10 100110 1 immr imms Rn Rd -- )
-
-! UDF: Permanently Undefined.
-ARM-INSTRUCTION: UDF-encode ( 0000000000000000 imm16 -- )
-
-! UDIV: Unsigned Divide.
-ARM-INSTRUCTION: UDIV32-encode ( 0 0 0 11010110 Rm 00001 0 Rn Rd -- )
-ARM-INSTRUCTION: UDIV64-encode ( 1 0 0 11010110 Rm 00001 0 Rn Rd -- )
-
-! UMADDL: Unsigned Multiply-Add Long.
-ARM-INSTRUCTION: UMADDL-encode ( 1 00 11011 1 01 Rm 0 Ra Rn Rd -- )
-
-! UMNEGL: Unsigned Multiply-Negate Long: an alias of UMSUBL.
-ARM-INSTRUCTION: UMNEGL-encode ( 1 00 11011 1 01 Rm 1 11111 Rn Rd -- )
-
-! UMSUBL: Unsigned Multiply-Subtract Long.
-ARM-INSTRUCTION: UMSUBL-encode ( 1 00 11011 1 01 Rm 1 Ra Rn Rd -- )
-
-! UMULH: Unsigned Multiply High.
-ARM-INSTRUCTION: UMULH-encode ( 1 00 11011 1 10 Rm 0 11111 Rn Rd -- )
-
-! UMULL: Unsigned Multiply Long: an alias of UMADDL.
-ARM-INSTRUCTION: UMULL-encode ( 1 00 11011 1 01 Rm 0 11111 Rn Rd -- )
-
-! UXTB: Unsigned Extend Byte: an alias of UBFM.
-ARM-INSTRUCTION: UXTB-encode ( 0 10 100110 0 000000 000111 Rn Rd -- )
-
-! UXTH: Unsigned Extend Halfword: an alias of UBFM.
-ARM-INSTRUCTION: UXTH-encode ( 0 10 100110 0 000000 000111 Rn Rd -- )
-
-! WFE: Wait For Event.
-ARM-INSTRUCTION: WFE-encode ( 1101010100 0 00 011 0010 0000 010 11111 -- )
-
-! WFI: Wait For Interrupt.
-ARM-INSTRUCTION: WFI-encode ( 1101010100 0 00 011 0010 0000 011 11111 -- )
-
-! XAFlag: Convert floating-point condition flags from external format to ARM format.
-ARM-INSTRUCTION: XAFlag-encode ( 1101010100 0 00 000 0100 0000 001 11111 -- )
-
-! XPACD, XPACI, XPACLRI: Strip Pointer Authentication Code.
-! ARMv8.3
-ARM-INSTRUCTION: XPACD-encode ( 1 1 0 11010110 00001 0 1 000 1 11111 Rd -- )
-ARM-INSTRUCTION: XPACI-encode ( 1 1 0 11010110 00001 0 1 000 0 11111 Rd -- )
-ARM-INSTRUCTION: XPACLRI-encode ( 1101010100 0 00 011 0010 0000 111 11111 -- )
-
-! YIELD: YIELD.
-ARM-INSTRUCTION: YIELD-encode ( 1101010100 0 00 011 0010 0000 001 11111 -- )
$nl
"Assembler opcodes are defined in CPU-specific vocabularies:"
{ $list
- { $vocab-link "cpu.arm.assembler" }
+ { $vocab-link "cpu.arm.64.assembler" }
{ $vocab-link "cpu.ppc.assembler" }
{ $vocab-link "cpu.x86.assembler" }
}
--- /dev/null
+IN: cpu.arm32.assembler.tests
+USING: cpu.arm.32.assembler math tools.test namespaces make
+sequences kernel quotations ;
+FROM: cpu.arm.32.assembler => B ;
+
+: test-opcode ( expect quot -- ) [ { } make first ] curry unit-test ;
+
+{ 0xea000000 } [ 0 B ] test-opcode
+{ 0xeb000000 } [ 0 BL ] test-opcode
+! { 0xe12fff30 } [ R0 BLX ] test-opcode
+
+{ 0xe24cc004 } [ IP IP 4 SUB ] test-opcode
+{ 0xe24cb004 } [ FP IP 4 SUB ] test-opcode
+{ 0xe087e3ac } [ LR R7 IP 7 <LSR> ADD ] test-opcode
+{ 0xe08c0109 } [ R0 IP R9 2 <LSL> ADD ] test-opcode
+{ 0x02850004 } [ R0 R5 4 EQ ADD ] test-opcode
+{ 0x00000000 } [ R0 R0 R0 EQ AND ] test-opcode
+
+{ 0xe1a0c00c } [ IP IP MOV ] test-opcode
+{ 0xe1a0c00d } [ IP SP MOV ] test-opcode
+{ 0xe3a03003 } [ R3 3 MOV ] test-opcode
+{ 0xe1a00003 } [ R0 R3 MOV ] test-opcode
+{ 0xe1e01c80 } [ R1 R0 25 <LSL> MVN ] test-opcode
+{ 0xe1e00ca1 } [ R0 R1 25 <LSR> MVN ] test-opcode
+{ 0x11a021ac } [ R2 IP 3 <LSR> NE MOV ] test-opcode
+
+{ 0xe3530007 } [ R3 7 CMP ] test-opcode
+
+{ 0xe008049a } [ R8 SL R4 MUL ] test-opcode
+
+{ 0xe5151004 } [ R1 R5 4 <-> LDR ] test-opcode
+{ 0xe41c2004 } [ R2 IP 4 <-!> LDR ] test-opcode
+{ 0xe50e2004 } [ R2 LR 4 <-> STR ] test-opcode
+
+{ 0xe7910002 } [ R0 R1 R2 <+> LDR ] test-opcode
+{ 0xe7910102 } [ R0 R1 R2 2 <LSL> <+> LDR ] test-opcode
+
+{ 0xe1d310bc } [ R1 R3 12 <+> LDRH ] test-opcode
+{ 0xe1d310fc } [ R1 R3 12 <+> LDRSH ] test-opcode
+{ 0xe1d310dc } [ R1 R3 12 <+> LDRSB ] test-opcode
+{ 0xe1c310bc } [ R1 R3 12 <+> STRH ] test-opcode
+{ 0xe19310b4 } [ R1 R3 R4 <+> LDRH ] test-opcode
+{ 0xe1f310fc } [ R1 R3 12 <!+> LDRSH ] test-opcode
+{ 0xe1b310d4 } [ R1 R3 R4 <!+> LDRSB ] test-opcode
+{ 0xe0c317bb } [ R1 R3 123 <+!> STRH ] test-opcode
+{ 0xe08310b4 } [ R1 R3 R4 <+!> STRH ] test-opcode
--- /dev/null
+! Copyright (C) 2007, 2009 Slava Pestov.
+! See https://factorcode.org/license.txt for BSD license.
+USING: accessors arrays combinators kernel make math math.bitwise
+namespaces sequences words words.symbol parser ;
+IN: cpu.arm.32.assembler
+
+! Registers
+<<
+
+SYMBOL: registers
+
+V{ } registers set-global
+
+SYNTAX: REGISTER:
+ scan-new-word
+ [ define-symbol ]
+ [ registers get length "register" set-word-prop ]
+ [ registers get push ]
+ tri ;
+
+>>
+
+REGISTER: R0
+REGISTER: R1
+REGISTER: R2
+REGISTER: R3
+REGISTER: R4
+REGISTER: R5
+REGISTER: R6
+REGISTER: R7
+REGISTER: R8
+REGISTER: R9
+REGISTER: R10
+REGISTER: R11
+REGISTER: R12
+REGISTER: R13
+REGISTER: R14
+REGISTER: R15
+
+ALIAS: SL R10 ALIAS: FP R11 ALIAS: IP R12
+ALIAS: SP R13 ALIAS: LR R14 ALIAS: PC R15
+
+<PRIVATE
+
+GENERIC: register ( register -- n )
+M: word register "register" word-prop ;
+M: f register drop 0 ;
+
+PREDICATE: register-class < word register >boolean ;
+
+PRIVATE>
+
+! Condition codes
+SYMBOL: cond-code
+
+: >CC ( n -- )
+ cond-code set ;
+
+: CC> ( -- n )
+ ! Default value is 0b1110 AL (= always)
+ cond-code [ f ] change 0b1110 or ;
+
+: EQ ( -- ) 0b0000 >CC ;
+: NE ( -- ) 0b0001 >CC ;
+: CS ( -- ) 0b0010 >CC ;
+: CC ( -- ) 0b0011 >CC ;
+: LO ( -- ) 0b0100 >CC ;
+: PL ( -- ) 0b0101 >CC ;
+: VS ( -- ) 0b0110 >CC ;
+: VC ( -- ) 0b0111 >CC ;
+: HI ( -- ) 0b1000 >CC ;
+: LS ( -- ) 0b1001 >CC ;
+: GE ( -- ) 0b1010 >CC ;
+: LT ( -- ) 0b1011 >CC ;
+: GT ( -- ) 0b1100 >CC ;
+: LE ( -- ) 0b1101 >CC ;
+: AL ( -- ) 0b1110 >CC ;
+: NV ( -- ) 0b1111 >CC ;
+
+<PRIVATE
+
+: (insn) ( n -- ) CC> 28 shift bitor , ;
+
+: insn ( bitspec -- ) bitfield (insn) ; inline
+
+! Branching instructions
+GENERIC#: (B) 1 ( target l -- )
+
+M: integer (B) { 24 { 1 25 } { 0 26 } { 1 27 } 0 } insn ;
+
+PRIVATE>
+
+: B ( target -- ) 0 (B) ;
+: BL ( target -- ) 1 (B) ;
+
+! Data processing instructions
+<PRIVATE
+
+SYMBOL: updates-cond-code
+
+PRIVATE>
+
+: S ( -- ) updates-cond-code on ;
+
+: S> ( -- ? ) updates-cond-code [ f ] change ;
+
+<PRIVATE
+
+: sinsn ( bitspec -- )
+ bitfield S> [ 20 2^ bitor ] when (insn) ; inline
+
+GENERIC#: shift-imm/reg 2 ( shift-imm/Rs Rm shift -- n )
+
+M: integer shift-imm/reg ( shift-imm Rm shift -- n )
+ { { 0 4 } 5 { register 0 } 7 } bitfield ;
+
+M: register-class shift-imm/reg ( Rs Rm shift -- n )
+ {
+ { 1 4 }
+ { 0 7 }
+ 5
+ { register 8 }
+ { register 0 }
+ } bitfield ;
+
+PRIVATE>
+
+TUPLE: IMM immed rotate ;
+C: <IMM> IMM
+
+TUPLE: shifter Rm by shift ;
+C: <shifter> shifter
+
+<PRIVATE
+
+GENERIC: shifter-op ( shifter-op -- n )
+
+M: IMM shifter-op
+ [ immed>> ] [ rotate>> ] bi { { 1 25 } 8 0 } bitfield ;
+
+M: shifter shifter-op
+ [ by>> ] [ Rm>> ] [ shift>> ] tri shift-imm/reg ;
+
+PRIVATE>
+
+: <LSL> ( Rm shift-imm/Rs -- shifter-op ) 0b00 <shifter> ;
+: <LSR> ( Rm shift-imm/Rs -- shifter-op ) 0b01 <shifter> ;
+: <ASR> ( Rm shift-imm/Rs -- shifter-op ) 0b10 <shifter> ;
+: <ROR> ( Rm shift-imm/Rs -- shifter-op ) 0b11 <shifter> ;
+: <RRX> ( Rm -- shifter-op ) 0 <ROR> ;
+
+M: register-class shifter-op 0 <LSL> shifter-op ;
+M: integer shifter-op 0 <IMM> shifter-op ;
+
+<PRIVATE
+
+: addr1 ( Rd Rn shifter-op opcode -- )
+ {
+ 21 ! opcode
+ { shifter-op 0 }
+ { register 16 } ! Rn
+ { register 12 } ! Rd
+ } sinsn ;
+
+PRIVATE>
+
+: AND ( Rd Rn shifter-op -- ) 0b0000 addr1 ;
+: EOR ( Rd Rn shifter-op -- ) 0b0001 addr1 ;
+: SUB ( Rd Rn shifter-op -- ) 0b0010 addr1 ;
+: RSB ( Rd Rn shifter-op -- ) 0b0011 addr1 ;
+: ADD ( Rd Rn shifter-op -- ) 0b0100 addr1 ;
+: ADC ( Rd Rn shifter-op -- ) 0b0101 addr1 ;
+: SBC ( Rd Rn shifter-op -- ) 0b0110 addr1 ;
+: RSC ( Rd Rn shifter-op -- ) 0b0111 addr1 ;
+: ORR ( Rd Rn shifter-op -- ) 0b1100 addr1 ;
+: BIC ( Rd Rn shifter-op -- ) 0b1110 addr1 ;
+
+: MOV ( Rd shifter-op -- ) [ f ] dip 0b1101 addr1 ;
+: MVN ( Rd shifter-op -- ) [ f ] dip 0b1111 addr1 ;
+
+! These always update the condition code flags
+<PRIVATE
+
+: (CMP) ( Rn shifter-op opcode -- ) [ f ] 3dip S addr1 ;
+
+PRIVATE>
+
+: TST ( Rn shifter-op -- ) 0b1000 (CMP) ;
+: TEQ ( Rn shifter-op -- ) 0b1001 (CMP) ;
+: CMP ( Rn shifter-op -- ) 0b1010 (CMP) ;
+: CMN ( Rn shifter-op -- ) 0b1011 (CMP) ;
+
+! Multiply instructions
+<PRIVATE
+
+: (MLA) ( Rd Rm Rs Rn a -- )
+ {
+ 21
+ { register 12 }
+ { register 8 }
+ { register 0 }
+ { register 16 }
+ { 1 7 }
+ { 1 4 }
+ } sinsn ;
+
+: (S/UMLAL) ( RdLo RdHi Rm Rs s a -- )
+ {
+ { 1 23 }
+ 22
+ 21
+ { register 8 }
+ { register 0 }
+ { register 16 }
+ { register 12 }
+ { 1 7 }
+ { 1 4 }
+ } sinsn ;
+
+PRIVATE>
+
+: MUL ( Rd Rm Rs -- ) f 0 (MLA) ;
+: MLA ( Rd Rm Rs Rn -- ) 1 (MLA) ;
+
+: SMLAL ( RdLo RdHi Rm Rs -- ) 1 1 (S/UMLAL) ;
+: SMULL ( RdLo RdHi Rm Rs -- ) 1 0 (S/UMLAL) ;
+: UMLAL ( RdLo RdHi Rm Rs -- ) 0 1 (S/UMLAL) ;
+: UMULL ( RdLo RdHi Rm Rs -- ) 0 0 (S/UMLAL) ;
+
+! Miscellaneous arithmetic instructions
+: CLZ ( Rd Rm -- )
+ {
+ { 1 24 }
+ { 1 22 }
+ { 1 21 }
+ { 0b111 16 }
+ { 0b1111 8 }
+ { 1 4 }
+ { register 0 }
+ { register 12 }
+ } sinsn ;
+
+! Status register acess instructions
+
+! Load and store instructions
+<PRIVATE
+
+GENERIC: addressing-mode-2 ( addressing-mode -- n )
+
+TUPLE: addressing base p u w ;
+C: <addressing> addressing
+
+M: addressing addressing-mode-2
+ { [ p>> ] [ u>> ] [ w>> ] [ base>> addressing-mode-2 ] } cleave
+ { 0 21 23 24 } bitfield ;
+
+M: integer addressing-mode-2 ;
+
+M: object addressing-mode-2 shifter-op { { 1 25 } 0 } bitfield ;
+
+: addr2 ( Rd Rn addressing-mode b l -- )
+ {
+ { 1 26 }
+ 20
+ 22
+ { addressing-mode-2 0 }
+ { register 16 }
+ { register 12 }
+ } insn ;
+
+PRIVATE>
+
+! Offset
+: <+> ( base -- addressing ) 1 1 0 <addressing> ;
+: <-> ( base -- addressing ) 1 0 0 <addressing> ;
+
+! Pre-indexed
+: <!+> ( base -- addressing ) 1 1 1 <addressing> ;
+: <!-> ( base -- addressing ) 1 0 1 <addressing> ;
+
+! Post-indexed
+: <+!> ( base -- addressing ) 0 1 0 <addressing> ;
+: <-!> ( base -- addressing ) 0 0 0 <addressing> ;
+
+: LDR ( Rd Rn addressing-mode -- ) 0 1 addr2 ;
+: LDRB ( Rd Rn addressing-mode -- ) 1 1 addr2 ;
+: STR ( Rd Rn addressing-mode -- ) 0 0 addr2 ;
+: STRB ( Rd Rn addressing-mode -- ) 1 0 addr2 ;
+
+! We might have to simulate these instructions since older ARM
+! chips don't have them.
+SYMBOL: have-BX?
+SYMBOL: have-BLX?
+
+<PRIVATE
+
+GENERIC#: (BX) 1 ( Rm l -- )
+
+M: register-class (BX) ( Rm l -- )
+ {
+ { 1 24 }
+ { 1 21 }
+ { 0b1111 16 }
+ { 0b1111 12 }
+ { 0b1111 8 }
+ 5
+ { 1 4 }
+ { register 0 }
+ } insn ;
+
+PRIVATE>
+
+: BX ( Rm -- ) have-BX? get [ 0 (BX) ] [ [ PC ] dip MOV ] if ;
+
+: BLX ( Rm -- ) have-BLX? get [ 1 (BX) ] [ LR PC MOV BX ] if ;
+
+! More load and store instructions
+<PRIVATE
+
+GENERIC: addressing-mode-3 ( addressing-mode -- n )
+
+: b>n/n ( b -- n n ) [ -4 shift ] [ 0xf bitand ] bi ;
+
+M: addressing addressing-mode-3
+ { [ p>> ] [ u>> ] [ w>> ] [ base>> addressing-mode-3 ] } cleave
+ { 0 21 23 24 } bitfield ;
+
+M: integer addressing-mode-3
+ b>n/n {
+ ! { 1 24 }
+ { 1 22 }
+ { 1 7 }
+ { 1 4 }
+ 0
+ 8
+ } bitfield ;
+
+M: object addressing-mode-3
+ shifter-op {
+ ! { 1 24 }
+ { 1 7 }
+ { 1 4 }
+ 0
+ } bitfield ;
+
+: addr3 ( Rn Rd addressing-mode h l s -- )
+ {
+ 6
+ 20
+ 5
+ { addressing-mode-3 0 }
+ { register 16 }
+ { register 12 }
+ } insn ;
+
+PRIVATE>
+
+: LDRH ( Rn Rd addressing-mode -- ) 1 1 0 addr3 ;
+: LDRSB ( Rn Rd addressing-mode -- ) 0 1 1 addr3 ;
+: LDRSH ( Rn Rd addressing-mode -- ) 1 1 1 addr3 ;
+: STRH ( Rn Rd addressing-mode -- ) 1 0 0 addr3 ;
+
+! Load and store multiple instructions
+
+! Semaphore instructions
+
+! Exception-generating instructions
--- /dev/null
+Slava Pestov
+++ /dev/null
-IN: cpu.arm32.assembler.tests
-USING: cpu.arm32.assembler math tools.test namespaces make
-sequences kernel quotations ;
-FROM: cpu.arm32.assembler => B ;
-
-: test-opcode ( expect quot -- ) [ { } make first ] curry unit-test ;
-
-{ 0xea000000 } [ 0 B ] test-opcode
-{ 0xeb000000 } [ 0 BL ] test-opcode
-! { 0xe12fff30 } [ R0 BLX ] test-opcode
-
-{ 0xe24cc004 } [ IP IP 4 SUB ] test-opcode
-{ 0xe24cb004 } [ FP IP 4 SUB ] test-opcode
-{ 0xe087e3ac } [ LR R7 IP 7 <LSR> ADD ] test-opcode
-{ 0xe08c0109 } [ R0 IP R9 2 <LSL> ADD ] test-opcode
-{ 0x02850004 } [ R0 R5 4 EQ ADD ] test-opcode
-{ 0x00000000 } [ R0 R0 R0 EQ AND ] test-opcode
-
-{ 0xe1a0c00c } [ IP IP MOV ] test-opcode
-{ 0xe1a0c00d } [ IP SP MOV ] test-opcode
-{ 0xe3a03003 } [ R3 3 MOV ] test-opcode
-{ 0xe1a00003 } [ R0 R3 MOV ] test-opcode
-{ 0xe1e01c80 } [ R1 R0 25 <LSL> MVN ] test-opcode
-{ 0xe1e00ca1 } [ R0 R1 25 <LSR> MVN ] test-opcode
-{ 0x11a021ac } [ R2 IP 3 <LSR> NE MOV ] test-opcode
-
-{ 0xe3530007 } [ R3 7 CMP ] test-opcode
-
-{ 0xe008049a } [ R8 SL R4 MUL ] test-opcode
-
-{ 0xe5151004 } [ R1 R5 4 <-> LDR ] test-opcode
-{ 0xe41c2004 } [ R2 IP 4 <-!> LDR ] test-opcode
-{ 0xe50e2004 } [ R2 LR 4 <-> STR ] test-opcode
-
-{ 0xe7910002 } [ R0 R1 R2 <+> LDR ] test-opcode
-{ 0xe7910102 } [ R0 R1 R2 2 <LSL> <+> LDR ] test-opcode
-
-{ 0xe1d310bc } [ R1 R3 12 <+> LDRH ] test-opcode
-{ 0xe1d310fc } [ R1 R3 12 <+> LDRSH ] test-opcode
-{ 0xe1d310dc } [ R1 R3 12 <+> LDRSB ] test-opcode
-{ 0xe1c310bc } [ R1 R3 12 <+> STRH ] test-opcode
-{ 0xe19310b4 } [ R1 R3 R4 <+> LDRH ] test-opcode
-{ 0xe1f310fc } [ R1 R3 12 <!+> LDRSH ] test-opcode
-{ 0xe1b310d4 } [ R1 R3 R4 <!+> LDRSB ] test-opcode
-{ 0xe0c317bb } [ R1 R3 123 <+!> STRH ] test-opcode
-{ 0xe08310b4 } [ R1 R3 R4 <+!> STRH ] test-opcode
+++ /dev/null
-! Copyright (C) 2007, 2009 Slava Pestov.
-! See https://factorcode.org/license.txt for BSD license.
-USING: accessors arrays combinators kernel make math math.bitwise
-namespaces sequences words words.symbol parser ;
-IN: cpu.arm32.assembler
-
-! Registers
-<<
-
-SYMBOL: registers
-
-V{ } registers set-global
-
-SYNTAX: REGISTER:
- scan-new-word
- [ define-symbol ]
- [ registers get length "register" set-word-prop ]
- [ registers get push ]
- tri ;
-
->>
-
-REGISTER: R0
-REGISTER: R1
-REGISTER: R2
-REGISTER: R3
-REGISTER: R4
-REGISTER: R5
-REGISTER: R6
-REGISTER: R7
-REGISTER: R8
-REGISTER: R9
-REGISTER: R10
-REGISTER: R11
-REGISTER: R12
-REGISTER: R13
-REGISTER: R14
-REGISTER: R15
-
-ALIAS: SL R10 ALIAS: FP R11 ALIAS: IP R12
-ALIAS: SP R13 ALIAS: LR R14 ALIAS: PC R15
-
-<PRIVATE
-
-GENERIC: register ( register -- n )
-M: word register "register" word-prop ;
-M: f register drop 0 ;
-
-PREDICATE: register-class < word register >boolean ;
-
-PRIVATE>
-
-! Condition codes
-SYMBOL: cond-code
-
-: >CC ( n -- )
- cond-code set ;
-
-: CC> ( -- n )
- ! Default value is 0b1110 AL (= always)
- cond-code [ f ] change 0b1110 or ;
-
-: EQ ( -- ) 0b0000 >CC ;
-: NE ( -- ) 0b0001 >CC ;
-: CS ( -- ) 0b0010 >CC ;
-: CC ( -- ) 0b0011 >CC ;
-: LO ( -- ) 0b0100 >CC ;
-: PL ( -- ) 0b0101 >CC ;
-: VS ( -- ) 0b0110 >CC ;
-: VC ( -- ) 0b0111 >CC ;
-: HI ( -- ) 0b1000 >CC ;
-: LS ( -- ) 0b1001 >CC ;
-: GE ( -- ) 0b1010 >CC ;
-: LT ( -- ) 0b1011 >CC ;
-: GT ( -- ) 0b1100 >CC ;
-: LE ( -- ) 0b1101 >CC ;
-: AL ( -- ) 0b1110 >CC ;
-: NV ( -- ) 0b1111 >CC ;
-
-<PRIVATE
-
-: (insn) ( n -- ) CC> 28 shift bitor , ;
-
-: insn ( bitspec -- ) bitfield (insn) ; inline
-
-! Branching instructions
-GENERIC#: (B) 1 ( target l -- )
-
-M: integer (B) { 24 { 1 25 } { 0 26 } { 1 27 } 0 } insn ;
-
-PRIVATE>
-
-: B ( target -- ) 0 (B) ;
-: BL ( target -- ) 1 (B) ;
-
-! Data processing instructions
-<PRIVATE
-
-SYMBOL: updates-cond-code
-
-PRIVATE>
-
-: S ( -- ) updates-cond-code on ;
-
-: S> ( -- ? ) updates-cond-code [ f ] change ;
-
-<PRIVATE
-
-: sinsn ( bitspec -- )
- bitfield S> [ 20 2^ bitor ] when (insn) ; inline
-
-GENERIC#: shift-imm/reg 2 ( shift-imm/Rs Rm shift -- n )
-
-M: integer shift-imm/reg ( shift-imm Rm shift -- n )
- { { 0 4 } 5 { register 0 } 7 } bitfield ;
-
-M: register-class shift-imm/reg ( Rs Rm shift -- n )
- {
- { 1 4 }
- { 0 7 }
- 5
- { register 8 }
- { register 0 }
- } bitfield ;
-
-PRIVATE>
-
-TUPLE: IMM immed rotate ;
-C: <IMM> IMM
-
-TUPLE: shifter Rm by shift ;
-C: <shifter> shifter
-
-<PRIVATE
-
-GENERIC: shifter-op ( shifter-op -- n )
-
-M: IMM shifter-op
- [ immed>> ] [ rotate>> ] bi { { 1 25 } 8 0 } bitfield ;
-
-M: shifter shifter-op
- [ by>> ] [ Rm>> ] [ shift>> ] tri shift-imm/reg ;
-
-PRIVATE>
-
-: <LSL> ( Rm shift-imm/Rs -- shifter-op ) 0b00 <shifter> ;
-: <LSR> ( Rm shift-imm/Rs -- shifter-op ) 0b01 <shifter> ;
-: <ASR> ( Rm shift-imm/Rs -- shifter-op ) 0b10 <shifter> ;
-: <ROR> ( Rm shift-imm/Rs -- shifter-op ) 0b11 <shifter> ;
-: <RRX> ( Rm -- shifter-op ) 0 <ROR> ;
-
-M: register-class shifter-op 0 <LSL> shifter-op ;
-M: integer shifter-op 0 <IMM> shifter-op ;
-
-<PRIVATE
-
-: addr1 ( Rd Rn shifter-op opcode -- )
- {
- 21 ! opcode
- { shifter-op 0 }
- { register 16 } ! Rn
- { register 12 } ! Rd
- } sinsn ;
-
-PRIVATE>
-
-: AND ( Rd Rn shifter-op -- ) 0b0000 addr1 ;
-: EOR ( Rd Rn shifter-op -- ) 0b0001 addr1 ;
-: SUB ( Rd Rn shifter-op -- ) 0b0010 addr1 ;
-: RSB ( Rd Rn shifter-op -- ) 0b0011 addr1 ;
-: ADD ( Rd Rn shifter-op -- ) 0b0100 addr1 ;
-: ADC ( Rd Rn shifter-op -- ) 0b0101 addr1 ;
-: SBC ( Rd Rn shifter-op -- ) 0b0110 addr1 ;
-: RSC ( Rd Rn shifter-op -- ) 0b0111 addr1 ;
-: ORR ( Rd Rn shifter-op -- ) 0b1100 addr1 ;
-: BIC ( Rd Rn shifter-op -- ) 0b1110 addr1 ;
-
-: MOV ( Rd shifter-op -- ) [ f ] dip 0b1101 addr1 ;
-: MVN ( Rd shifter-op -- ) [ f ] dip 0b1111 addr1 ;
-
-! These always update the condition code flags
-<PRIVATE
-
-: (CMP) ( Rn shifter-op opcode -- ) [ f ] 3dip S addr1 ;
-
-PRIVATE>
-
-: TST ( Rn shifter-op -- ) 0b1000 (CMP) ;
-: TEQ ( Rn shifter-op -- ) 0b1001 (CMP) ;
-: CMP ( Rn shifter-op -- ) 0b1010 (CMP) ;
-: CMN ( Rn shifter-op -- ) 0b1011 (CMP) ;
-
-! Multiply instructions
-<PRIVATE
-
-: (MLA) ( Rd Rm Rs Rn a -- )
- {
- 21
- { register 12 }
- { register 8 }
- { register 0 }
- { register 16 }
- { 1 7 }
- { 1 4 }
- } sinsn ;
-
-: (S/UMLAL) ( RdLo RdHi Rm Rs s a -- )
- {
- { 1 23 }
- 22
- 21
- { register 8 }
- { register 0 }
- { register 16 }
- { register 12 }
- { 1 7 }
- { 1 4 }
- } sinsn ;
-
-PRIVATE>
-
-: MUL ( Rd Rm Rs -- ) f 0 (MLA) ;
-: MLA ( Rd Rm Rs Rn -- ) 1 (MLA) ;
-
-: SMLAL ( RdLo RdHi Rm Rs -- ) 1 1 (S/UMLAL) ;
-: SMULL ( RdLo RdHi Rm Rs -- ) 1 0 (S/UMLAL) ;
-: UMLAL ( RdLo RdHi Rm Rs -- ) 0 1 (S/UMLAL) ;
-: UMULL ( RdLo RdHi Rm Rs -- ) 0 0 (S/UMLAL) ;
-
-! Miscellaneous arithmetic instructions
-: CLZ ( Rd Rm -- )
- {
- { 1 24 }
- { 1 22 }
- { 1 21 }
- { 0b111 16 }
- { 0b1111 8 }
- { 1 4 }
- { register 0 }
- { register 12 }
- } sinsn ;
-
-! Status register acess instructions
-
-! Load and store instructions
-<PRIVATE
-
-GENERIC: addressing-mode-2 ( addressing-mode -- n )
-
-TUPLE: addressing base p u w ;
-C: <addressing> addressing
-
-M: addressing addressing-mode-2
- { [ p>> ] [ u>> ] [ w>> ] [ base>> addressing-mode-2 ] } cleave
- { 0 21 23 24 } bitfield ;
-
-M: integer addressing-mode-2 ;
-
-M: object addressing-mode-2 shifter-op { { 1 25 } 0 } bitfield ;
-
-: addr2 ( Rd Rn addressing-mode b l -- )
- {
- { 1 26 }
- 20
- 22
- { addressing-mode-2 0 }
- { register 16 }
- { register 12 }
- } insn ;
-
-PRIVATE>
-
-! Offset
-: <+> ( base -- addressing ) 1 1 0 <addressing> ;
-: <-> ( base -- addressing ) 1 0 0 <addressing> ;
-
-! Pre-indexed
-: <!+> ( base -- addressing ) 1 1 1 <addressing> ;
-: <!-> ( base -- addressing ) 1 0 1 <addressing> ;
-
-! Post-indexed
-: <+!> ( base -- addressing ) 0 1 0 <addressing> ;
-: <-!> ( base -- addressing ) 0 0 0 <addressing> ;
-
-: LDR ( Rd Rn addressing-mode -- ) 0 1 addr2 ;
-: LDRB ( Rd Rn addressing-mode -- ) 1 1 addr2 ;
-: STR ( Rd Rn addressing-mode -- ) 0 0 addr2 ;
-: STRB ( Rd Rn addressing-mode -- ) 1 0 addr2 ;
-
-! We might have to simulate these instructions since older ARM
-! chips don't have them.
-SYMBOL: have-BX?
-SYMBOL: have-BLX?
-
-<PRIVATE
-
-GENERIC#: (BX) 1 ( Rm l -- )
-
-M: register-class (BX) ( Rm l -- )
- {
- { 1 24 }
- { 1 21 }
- { 0b1111 16 }
- { 0b1111 12 }
- { 0b1111 8 }
- 5
- { 1 4 }
- { register 0 }
- } insn ;
-
-PRIVATE>
-
-: BX ( Rm -- ) have-BX? get [ 0 (BX) ] [ [ PC ] dip MOV ] if ;
-
-: BLX ( Rm -- ) have-BLX? get [ 1 (BX) ] [ LR PC MOV BX ] if ;
-
-! More load and store instructions
-<PRIVATE
-
-GENERIC: addressing-mode-3 ( addressing-mode -- n )
-
-: b>n/n ( b -- n n ) [ -4 shift ] [ 0xf bitand ] bi ;
-
-M: addressing addressing-mode-3
- { [ p>> ] [ u>> ] [ w>> ] [ base>> addressing-mode-3 ] } cleave
- { 0 21 23 24 } bitfield ;
-
-M: integer addressing-mode-3
- b>n/n {
- ! { 1 24 }
- { 1 22 }
- { 1 7 }
- { 1 4 }
- 0
- 8
- } bitfield ;
-
-M: object addressing-mode-3
- shifter-op {
- ! { 1 24 }
- { 1 7 }
- { 1 4 }
- 0
- } bitfield ;
-
-: addr3 ( Rn Rd addressing-mode h l s -- )
- {
- 6
- 20
- 5
- { addressing-mode-3 0 }
- { register 16 }
- { register 12 }
- } insn ;
-
-PRIVATE>
-
-: LDRH ( Rn Rd addressing-mode -- ) 1 1 0 addr3 ;
-: LDRSB ( Rn Rd addressing-mode -- ) 0 1 1 addr3 ;
-: LDRSH ( Rn Rd addressing-mode -- ) 1 1 1 addr3 ;
-: STRH ( Rn Rd addressing-mode -- ) 1 0 0 addr3 ;
-
-! Load and store multiple instructions
-
-! Semaphore instructions
-
-! Exception-generating instructions
+++ /dev/null
-Slava Pestov
}
// Load a value from a bitfield of a PowerPC instruction
-fixnum instruction_operand::load_value_masked(cell mask, cell bits,
- cell shift) {
+fixnum instruction_operand::load_value_masked(cell mask, cell preshift,
+ cell bits, cell postshift) {
int32_t* ptr = (int32_t*)(pointer - sizeof(uint32_t));
- return (((*ptr & (int32_t)mask) << bits) >> bits) << shift;
+ return ((((*ptr & (int32_t)mask) >> preshift ) << bits) >> bits) << postshift;
}
fixnum instruction_operand::load_value(cell relative_to) {
case RC_ABSOLUTE_PPC_2_2:
return load_value_2_2();
case RC_ABSOLUTE_PPC_2:
- return load_value_masked(rel_absolute_ppc_2_mask, 16, 0);
+ return load_value_masked(rel_absolute_ppc_2_mask, 0, 16, 0);
case RC_RELATIVE_PPC_2_PC:
- return load_value_masked(rel_relative_ppc_2_mask, 16, 0) + relative_to -
- 4;
+ return load_value_masked(rel_relative_ppc_2_mask, 0, 16, 0) +
+ relative_to - 4;
case RC_RELATIVE_PPC_3_PC:
- return load_value_masked(rel_relative_ppc_3_mask, 6, 0) + relative_to - 4;
+ return load_value_masked(rel_relative_ppc_3_mask, 0, 6, 0) +
+ relative_to - 4;
case RC_RELATIVE_ARM_3:
- return load_value_masked(rel_relative_arm_3_mask, 6, 2) + relative_to +
+ return load_value_masked(rel_relative_arm_3_mask, 0, 6, 2) + relative_to +
sizeof(cell);
case RC_INDIRECT_ARM:
- return load_value_masked(rel_indirect_arm_mask, 20, 0) + relative_to;
+ return load_value_masked(rel_indirect_arm_mask, 0, 20, 0) + relative_to;
case RC_INDIRECT_ARM_PC:
- return load_value_masked(rel_indirect_arm_mask, 20, 0) + relative_to +
+ return load_value_masked(rel_indirect_arm_mask, 0, 20, 0) + relative_to +
sizeof(cell);
case RC_ABSOLUTE_2:
return *(uint16_t*)(pointer - sizeof(uint16_t));
return *(uint8_t*)(pointer - sizeof(uint8_t));
case RC_ABSOLUTE_PPC_2_2_2_2:
return load_value_2_2_2_2();
+ case RC_RELATIVE_ARM64_BRANCH:
+ return load_value_masked(rel_relative_arm64_branch_mask, 0, 4, 2) +
+ relative_to;
+ case RC_RELATIVE_ARM64_BCOND:
+ return load_value_masked(rel_relative_arm64_bcond_mask, 3, 11, 0) +
+ relative_to;
default:
critical_error("Bad rel class", rel.klass());
return 0;
// Store a value into a bitfield of a PowerPC instruction
void instruction_operand::store_value_masked(fixnum value, cell mask,
- cell shift) {
+ cell shift1, cell shift2) {
uint32_t* ptr = (uint32_t*)(pointer - sizeof(uint32_t));
- *ptr = (uint32_t)((*ptr & ~mask) | ((value >> shift) & mask));
+ *ptr = (uint32_t)((*ptr & ~mask) | ((value >> shift1 << shift2) & mask));
}
void instruction_operand::store_value(fixnum absolute_value) {
store_value_2_2(absolute_value);
break;
case RC_ABSOLUTE_PPC_2:
- store_value_masked(absolute_value, rel_absolute_ppc_2_mask, 0);
+ store_value_masked(absolute_value, rel_absolute_ppc_2_mask, 0, 0);
break;
case RC_RELATIVE_PPC_2_PC:
- store_value_masked(relative_value + 4, rel_relative_ppc_2_mask, 0);
+ store_value_masked(relative_value + 4, rel_relative_ppc_2_mask, 0, 0);
break;
case RC_RELATIVE_PPC_3_PC:
- store_value_masked(relative_value + 4, rel_relative_ppc_3_mask, 0);
+ store_value_masked(relative_value + 4, rel_relative_ppc_3_mask, 0, 0);
break;
case RC_RELATIVE_ARM_3:
store_value_masked(relative_value - sizeof(cell), rel_relative_arm_3_mask,
- 2);
+ 2, 0);
break;
case RC_INDIRECT_ARM:
- store_value_masked(relative_value, rel_indirect_arm_mask, 0);
+ store_value_masked(relative_value, rel_indirect_arm_mask, 0, 0);
break;
case RC_INDIRECT_ARM_PC:
store_value_masked(relative_value - sizeof(cell), rel_indirect_arm_mask,
- 0);
+ 0, 0);
break;
case RC_ABSOLUTE_2:
*(uint16_t*)(pointer - sizeof(uint16_t)) = (uint16_t)absolute_value;
case RC_ABSOLUTE_PPC_2_2_2_2:
store_value_2_2_2_2(absolute_value);
break;
+ case RC_RELATIVE_ARM64_BRANCH:
+ store_value_masked(relative_value, rel_relative_arm64_branch_mask, 2, 0);
+ break;
+ case RC_RELATIVE_ARM64_BCOND:
+ store_value_masked(relative_value, rel_relative_arm64_bcond_mask, 2, 5);
+ break;
default:
critical_error("Bad rel class", rel.klass());
break;
RC_RELATIVE_PPC_2_PC,
// relative address in a PowerPC B/BL instruction
RC_RELATIVE_PPC_3_PC,
- // relative address in an ARM B/BL instruction
+ // relative address in an ARM32 B/BL instruction
RC_RELATIVE_ARM_3,
- // pointer to address in an ARM LDR/STR instruction
+ // pointer to address in an ARM32 LDR/STR instruction
RC_INDIRECT_ARM,
- // pointer to address in an ARM LDR/STR instruction offset by 8 bytes
+ // pointer to address in an ARM32 LDR/STR instruction offset by 8 bytes
RC_INDIRECT_ARM_PC,
// absolute address in a 2 byte location
RC_ABSOLUTE_2,
RC_ABSOLUTE_1,
// absolute address in a PowerPC LIS/ORI/SLDI/ORIS/ORI sequence
RC_ABSOLUTE_PPC_2_2_2_2,
+ // relative address in an ARM64 B/BL instruction
+ RC_RELATIVE_ARM64_BRANCH,
+ // relative address in an ARM64 B.cond instruction
+ RC_RELATIVE_ARM64_BCOND,
};
static const cell rel_absolute_ppc_2_mask = 0x0000ffff;
static const cell rel_relative_ppc_3_mask = 0x03fffffc;
static const cell rel_indirect_arm_mask = 0x00000fff;
static const cell rel_relative_arm_3_mask = 0x00ffffff;
+static const cell rel_relative_arm64_branch_mask = 0x03ffffff;
+static const cell rel_relative_arm64_bcond_mask = 0x00ffffe0;
// code relocation table consists of a table of entries for each fixup
struct relocation_entry {
fixnum load_value_2_2();
fixnum load_value_2_2_2_2();
- fixnum load_value_masked(cell mask, cell bits, cell shift);
+ fixnum load_value_masked(cell mask, cell preshift, cell bits, cell postshift);
fixnum load_value(cell relative_to);
code_block* load_code_block();
void store_value_2_2(fixnum value);
void store_value_2_2_2_2(fixnum value);
- void store_value_masked(fixnum value, cell mask, cell shift);
+ void store_value_masked(fixnum value, cell mask, cell shift1, cell shift2);
void store_value(fixnum value);
};
obj == parent->special_objects[UNWIND_NATIVE_FRAMES_WORD];
}
-// All quotations wants a stack frame, except if they contain:
+// All quotations want a stack frame, except if they contain:
// 1) calls to the special subprimitives, see #295.
// 2) mega cache lookups, see #651
bool quotation_jit::stack_frame_p() {
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