cpu.arm.assembler: More words to encode, bounds checking

diff --git a/basis/cpu/arm/assembler/assembler.factor b/basis/cpu/arm/assembler/assembler.factor
index ecb542f6ed1766958186aa985bf88d879b866269..ed30ebff3278f88b4a0e98149851557c7ee8ea24 100644 (file)
--- a/basis/cpu/arm/assembler/assembler.factor
+++ b/basis/cpu/arm/assembler/assembler.factor
@@ -18,17 +18,17 @@ TUPLE: arm64-assembler ip labels out ;
         H{ } clone >>labels
         V{ } clone >>out ;
 
+ERROR: arm64-encoding-imm original n-bits-requested truncated ;
+: ?bits ( x n -- x ) 2dup bits dup reach = [ 2drop ] [ arm64-encoding-imm ] if ; inline
+
 : ip ( -- address ) arm64-assembler get ip>> ;
 : >out ( instruction -- ) arm64-assembler get out>> push ;
 
 : ADR ( imm21 Rd -- )
-    [ [ 2 bits ] [ -2 shift 19 bits ] bi ] dip ADR-encode >out ;
+    [ [ 2 bits ] [ -2 shift 19 ?bits ] bi ] dip ADR-encode >out ;
 
 : ADRP ( imm21 Rd -- )
-    [ [ 2 bits ] [ -2 shift 19 bits ] bi ] dip ADRP-encode >out ;
-
-: BL ( offset -- ) ip - 4 / BL-encode >out ;
-: BR ( register -- ) BR-encode >out ;
+    [ [ 2 bits ] [ -2 shift 19 ?bits ] bi ] dip ADRP-encode >out ;
 
 : LDR-pre ( imm9 Rn Rt -- ) LDRpre64-encode >out ;
 : LDR-post ( imm9 Rn Rt -- ) LDRpost64-encode >out ;
@@ -100,14 +100,14 @@ ERROR: imm-out-of-range imm n ;
 : STRr64 ( Rm Rn Rt -- )
     [ 0 0 ] 2dip STRr64-encode >out ;
 
-: ASRi32 ( imm6 Rn Rd -- ) ASRi32-encode >out ;
-: ASRi64 ( imm6 Rn Rd -- ) ASRi64-encode >out ;
-: LSLi32 ( imm6 Rn Rd -- ) LSLi32-encode >out ;
-: LSLi64 ( imm6 Rn Rd -- ) LSLi64-encode >out ;
-: LSRi32 ( imm6 Rn Rd -- ) LSRi32-encode >out ;
-: LSRi64 ( imm6 Rn Rd -- ) LSRi64-encode >out ;
+: ASRi32 ( imm6 Rn Rd -- ) [ 6 ?bits ] 2dip ASRi32-encode >out ;
+: ASRi64 ( imm6 Rn Rd -- ) [ 6 ?bits ] 2dip ASRi64-encode >out ;
+: LSLi32 ( imm6 Rn Rd -- ) [ 6 ?bits ] 2dip LSLi32-encode >out ;
+: LSLi64 ( imm6 Rn Rd -- ) [ 6 ?bits ] 2dip LSLi64-encode >out ;
+: LSRi32 ( imm6 Rn Rd -- ) [ 6 ?bits ] 2dip LSRi32-encode >out ;
+: LSRi64 ( imm6 Rn Rd -- ) [ 6 ?bits ] 2dip LSRi64-encode >out ;
 
-: SVC ( imm16 -- ) SVC-encode >out ;
+: SVC ( imm16 -- ) 16 ?bits SVC-encode >out ;
 
 : with-new-arm64-offset ( offset quot -- arm64-assembler )
     [ <arm64-assembler> \ arm64-assembler ] dip
@@ -137,4 +137,17 @@ ERROR: imm-out-of-range imm n ;
 : ADC64 ( Rm Rn Rd -- ) ADC64-encode >out ;
 : ADCS64 ( Rm Rn Rd -- ) ADCS64-encode >out ;
 
-: BRK ( imm16 -- ) BRK-encode >out ;
+: BRK ( imm16 -- ) 16 ?bits BRK-encode >out ;
+: HLT ( imm16 -- ) 16 ?bits HLT-encode >out ;
+
+: CBNZ ( imm19 Rt -- ) [ 19 ?bits ] dip CBNZ64-encode >out ;
+! cond4 is EQ NE CS HS CC LO MI PL VS VC HI LS GE LT GT LE AL NV
+: CSEL ( Rm Rn Rd cond4 -- ) -rot CSEL64-encode >out ;
+: CSET ( Rd cond4 -- ) swap CSET64-encode >out ;
+: CSETM ( Rd cond4 -- ) swap CSETM64-encode >out ;
+
+! B but that is breakpoint
+: Br ( imm26 -- ) 26 ?bits B-encode >out ;
+: B.cond ( imm19 cond4 -- ) [ 19 ?bits ] dip B.cond-encode >out ;
+: BL ( offset -- ) ip - 4 / BL-encode >out ;
+: BR ( Rn -- ) BR-encode >out ;

diff --git a/basis/cpu/arm/assembler/opcodes/opcodes.factor b/basis/cpu/arm/assembler/opcodes/opcodes.factor
index 4d87a4a4406135344b1981112102d4f46b319aef..6871fca93265b7dc6e742f321362fec1cebf4fe2 100644 (file)
--- a/basis/cpu/arm/assembler/opcodes/opcodes.factor
+++ b/basis/cpu/arm/assembler/opcodes/opcodes.factor
@@ -246,25 +246,25 @@ SINGLETONS: SPSR_EL1 SPSR_EL2 SPSR_EL3 ;
 ! https://www.element14.com/community/servlet/JiveServlet/previewBody/41836-102-1-229511/ARM.Reference_Manual.pdf
 ! pg 16
 ! cond code set in prev arm assembler
-: >CC ( x -- x ) ; 
-: EQ ( -- n ) 0000 >CC ;
-: NE ( -- n ) 0001 >CC ;
-: CS ( -- n ) 0010 >CC ;
-: HS ( -- n ) 0010 >CC ;
-: CC ( -- n ) 0011 >CC ;
-: LO ( -- n ) 0011 >CC ;
-: MI ( -- n ) 0100 >CC ;
-: PL ( -- n ) 0101 >CC ;
-: VS ( -- n ) 0110 >CC ;
-: VC ( -- n ) 0111 >CC ;
-: HI ( -- n ) 1000 >CC ;
-: LS ( -- n ) 1001 >CC ;
-: GE ( -- n ) 1010 >CC ;
-: LT ( -- n ) 1011 >CC ;
-: GT ( -- n ) 1100 >CC ;
-: LE ( -- n ) 1101 >CC ;
-: AL ( -- n ) 1110 >CC ;
-: NV ( -- n ) 1111 >CC ;
+: >CC ( x -- x ) ; inline
+: EQ ( -- n ) 0000 >CC ; inline ! Z set equal
+: NE ( -- n ) 0001 >CC ; inline ! Z clear not equal
+: CS ( -- n ) 0010 >CC ; inline ! C set unsigned higher or same
+: HS ( -- n ) 0010 >CC ; inline !
+: CC ( -- n ) 0011 >CC ; inline ! C clear unsigned lower
+: LO ( -- n ) 0011 >CC ; inline !
+: MI ( -- n ) 0100 >CC ; inline ! N set negative
+: PL ( -- n ) 0101 >CC ; inline ! N clear positive or zero
+: VS ( -- n ) 0110 >CC ; inline ! V set overflow
+: VC ( -- n ) 0111 >CC ; inline ! V clear no overflow
+: HI ( -- n ) 1000 >CC ; inline ! C set and Z clear unsigned higher
+: LS ( -- n ) 1001 >CC ; inline ! C clear or Z set unsigned lower or same
+: GE ( -- n ) 1010 >CC ; inline ! N equals V greater or equal
+: LT ( -- n ) 1011 >CC ; inline ! N not equal to V less than
+: GT ( -- n ) 1100 >CC ; inline ! Z clear AND (N equals V) greater than
+: LE ( -- n ) 1101 >CC ; inline ! Z set OR (N not equal to V) less than or equal
+: AL ( -- n ) 1110 >CC ; inline ! AL (ignored) always
+: NV ( -- n ) 1111 >CC ; inline ! no value
 
 : imm13>parts-64 ( imm13 -- imms immr N )
     [ -4 shift 4 bits ] [ 4 bits ] [ -8 shift ] tri ;
@@ -423,7 +423,7 @@ ARM-INSTRUCTION: AXFlag-encode ( 1101010100 0 00 000 0100 0000 010 11111 -- inst
 ARM-INSTRUCTION: B-encode ( 0 00101 imm26 -- instruction )
 
 ! B.cond: Branch conditionally.
-ARM-INSTRUCTION: B.cond ( 0101010 0 imm19 0 cond4 -- instruction )
+ARM-INSTRUCTION: B.cond-encode ( 0101010 0 imm19 0 cond4 -- instruction )
 
 ! BFC: Bitfield Clear: an alias of BFM.
 ARM-INSTRUCTION: BFC32-encode ( 0 01 100110 0 immrimms 11111 Rd -- instruction )