M: array c-type-unboxer-quot drop [ >c-ptr ] ;
-M: value-type c-type-reg-class drop int-regs ;
+M: value-type c-type-rep drop int-rep ;
M: value-type c-type-getter
drop [ swap <displaced-alien> ] ;
M: string-type stack-size
drop "void*" stack-size ;
-M: string-type c-type-reg-class
- drop int-regs ;
+M: string-type c-type-rep
+ drop int-rep ;
M: string-type c-type-boxer
drop "void*" c-type-boxer ;
{ unboxer-quot callable }
{ getter callable }
{ setter callable }
-{ reg-class initial: int-regs }
+{ rep initial: int-rep }
size
align
stack-align? ;
M: string c-type-unboxer-quot c-type c-type-unboxer-quot ;
-GENERIC: c-type-reg-class ( name -- reg-class )
+GENERIC: c-type-rep ( name -- rep )
-M: c-type c-type-reg-class reg-class>> ;
+M: c-type c-type-rep rep>> ;
-M: string c-type-reg-class c-type c-type-reg-class ;
+M: string c-type-rep c-type c-type-rep ;
GENERIC: c-type-getter ( name -- quot )
M: string c-type-stack-align? c-type c-type-stack-align? ;
: c-type-box ( n type -- )
- dup c-type-reg-class
- swap c-type-boxer [ "No boxer" throw ] unless*
+ [ c-type-rep ] [ c-type-boxer [ "No boxer" throw ] unless* ] bi
%box ;
: c-type-unbox ( n ctype -- )
- dup c-type-reg-class
- swap c-type-unboxer [ "No unboxer" throw ] unless*
+ [ c-type-rep ] [ c-type-unboxer [ "No unboxer" throw ] unless* ] bi
%unbox ;
GENERIC: box-parameter ( n ctype -- )
4 >>align
"box_float" >>boxer
"to_float" >>unboxer
- single-float-regs >>reg-class
+ single-float-rep >>rep
[ >float ] >>unboxer-quot
"float" define-primitive-type
8 >>align
"box_double" >>boxer
"to_double" >>unboxer
- double-float-regs >>reg-class
+ double-float-rep >>rep
[ >float ] >>unboxer-quot
"double" define-primitive-type
! Copyright (C) 2008, 2009 Slava Pestov.
! See http://factorcode.org/license.txt for BSD license.
USING: kernel math namespaces assocs hashtables sequences arrays
-accessors vectors combinators sets classes compiler.cfg
+accessors vectors combinators sets classes cpu.architecture compiler.cfg
compiler.cfg.registers compiler.cfg.instructions
compiler.cfg.copy-prop compiler.cfg.rpo compiler.cfg.liveness ;
IN: compiler.cfg.alias-analysis
call-next-method
dup [ dst>> ] [ insn-slot# ] [ insn-object ] tri
2dup live-slot dup [
- 2nip \ ##copy new-insn analyze-aliases* nip
+ 2nip int-rep \ ##copy new-insn analyze-aliases* nip
] [
drop remember-slot
] if ;
! Copyright (C) 2008, 2009 Slava Pestov.
! See http://factorcode.org/license.txt for BSD license.
USING: namespaces accessors math.order assocs kernel sequences
-combinators make classes words cpu.architecture
+combinators make classes words cpu.architecture layouts
compiler.cfg.instructions compiler.cfg.registers
compiler.cfg.stack-frame ;
IN: compiler.cfg.build-stack-frame
SYMBOL: frame-required?
-SYMBOL: spill-counts
-
GENERIC: compute-stack-frame* ( insn -- )
: request-stack-frame ( stack-frame -- )
M: _gc compute-stack-frame*
frame-required? on
- stack-frame new swap gc-root-size>> >>gc-root-size
+ stack-frame new swap gc-root-size>> cells >>gc-root-size
request-stack-frame ;
-M: _spill-counts compute-stack-frame*
- counts>> stack-frame get (>>spill-counts) ;
+M: _spill-area-size compute-stack-frame*
+ n>> stack-frame get (>>spill-area-size) ;
M: insn compute-stack-frame*
class frame-required? word-prop [
: compute-stack-frame ( insns -- )
frame-required? off
- T{ stack-frame } clone stack-frame set
+ stack-frame new stack-frame set
[ compute-stack-frame* ] each
stack-frame get dup stack-frame-size >>total-size drop ;
V{ } clone >>predecessors
\ basic-block counter >>id ;
-TUPLE: cfg { entry basic-block } word label spill-counts post-order ;
+TUPLE: cfg { entry basic-block } word label spill-area-size post-order ;
-: <cfg> ( entry word label -- cfg ) f f cfg boa ;
+: <cfg> ( entry word label -- cfg )
+ cfg new
+ swap >>label
+ swap >>word
+ swap >>entry ;
: cfg-changed ( cfg -- cfg ) f >>post-order ; inline
entry>> instructions>> ;
[ V{
- T{ ##load-immediate { dst V int-regs 1 } { val 8 } }
- T{ ##load-immediate { dst V int-regs 2 } { val 16 } }
- T{ ##add { dst V int-regs 3 } { src1 V int-regs 1 } { src2 V int-regs 2 } }
- T{ ##replace { src V int-regs 3 } { loc D 0 } }
+ T{ ##load-immediate { dst V int-rep 1 } { val 8 } }
+ T{ ##load-immediate { dst V int-rep 2 } { val 16 } }
+ T{ ##add { dst V int-rep 3 } { src1 V int-rep 1 } { src2 V int-rep 2 } }
+ T{ ##replace { src V int-rep 3 } { loc D 0 } }
} ] [ V{
- T{ ##load-immediate { dst V int-regs 1 } { val 8 } }
- T{ ##load-immediate { dst V int-regs 2 } { val 16 } }
- T{ ##add { dst V int-regs 3 } { src1 V int-regs 1 } { src2 V int-regs 2 } }
- T{ ##replace { src V int-regs 3 } { loc D 0 } }
+ T{ ##load-immediate { dst V int-rep 1 } { val 8 } }
+ T{ ##load-immediate { dst V int-rep 2 } { val 16 } }
+ T{ ##add { dst V int-rep 3 } { src1 V int-rep 1 } { src2 V int-rep 2 } }
+ T{ ##replace { src V int-rep 3 } { loc D 0 } }
} test-dce ] unit-test
[ V{ } ] [ V{
- T{ ##load-immediate { dst V int-regs 1 } { val 8 } }
- T{ ##load-immediate { dst V int-regs 2 } { val 16 } }
- T{ ##add { dst V int-regs 3 } { src1 V int-regs 1 } { src2 V int-regs 2 } }
+ T{ ##load-immediate { dst V int-rep 1 } { val 8 } }
+ T{ ##load-immediate { dst V int-rep 2 } { val 16 } }
+ T{ ##add { dst V int-rep 3 } { src1 V int-rep 1 } { src2 V int-rep 2 } }
} test-dce ] unit-test
[ V{ } ] [ V{
- T{ ##load-immediate { dst V int-regs 3 } { val 8 } }
- T{ ##allot { dst V int-regs 1 } { temp V int-regs 2 } }
+ T{ ##load-immediate { dst V int-rep 3 } { val 8 } }
+ T{ ##allot { dst V int-rep 1 } { temp V int-rep 2 } }
} test-dce ] unit-test
[ V{ } ] [ V{
- T{ ##load-immediate { dst V int-regs 3 } { val 8 } }
- T{ ##allot { dst V int-regs 1 } { temp V int-regs 2 } }
- T{ ##set-slot-imm { obj V int-regs 1 } { src V int-regs 3 } }
+ T{ ##load-immediate { dst V int-rep 3 } { val 8 } }
+ T{ ##allot { dst V int-rep 1 } { temp V int-rep 2 } }
+ T{ ##set-slot-imm { obj V int-rep 1 } { src V int-rep 3 } }
} test-dce ] unit-test
[ V{
- T{ ##load-immediate { dst V int-regs 3 } { val 8 } }
- T{ ##allot { dst V int-regs 1 } { temp V int-regs 2 } }
- T{ ##set-slot-imm { obj V int-regs 1 } { src V int-regs 3 } }
- T{ ##replace { src V int-regs 1 } { loc D 0 } }
+ T{ ##load-immediate { dst V int-rep 3 } { val 8 } }
+ T{ ##allot { dst V int-rep 1 } { temp V int-rep 2 } }
+ T{ ##set-slot-imm { obj V int-rep 1 } { src V int-rep 3 } }
+ T{ ##replace { src V int-rep 1 } { loc D 0 } }
} ] [ V{
- T{ ##load-immediate { dst V int-regs 3 } { val 8 } }
- T{ ##allot { dst V int-regs 1 } { temp V int-regs 2 } }
- T{ ##set-slot-imm { obj V int-regs 1 } { src V int-regs 3 } }
- T{ ##replace { src V int-regs 1 } { loc D 0 } }
+ T{ ##load-immediate { dst V int-rep 3 } { val 8 } }
+ T{ ##allot { dst V int-rep 1 } { temp V int-rep 2 } }
+ T{ ##set-slot-imm { obj V int-rep 1 } { src V int-rep 3 } }
+ T{ ##replace { src V int-rep 1 } { loc D 0 } }
} test-dce ] unit-test
[ V{
- T{ ##allot { dst V int-regs 1 } { temp V int-regs 2 } }
- T{ ##replace { src V int-regs 1 } { loc D 0 } }
+ T{ ##allot { dst V int-rep 1 } { temp V int-rep 2 } }
+ T{ ##replace { src V int-rep 1 } { loc D 0 } }
} ] [ V{
- T{ ##allot { dst V int-regs 1 } { temp V int-regs 2 } }
- T{ ##replace { src V int-regs 1 } { loc D 0 } }
+ T{ ##allot { dst V int-rep 1 } { temp V int-rep 2 } }
+ T{ ##replace { src V int-rep 1 } { loc D 0 } }
} test-dce ] unit-test
[ V{
- T{ ##allot { dst V int-regs 1 } { temp V int-regs 2 } }
- T{ ##replace { src V int-regs 1 } { loc D 0 } }
- T{ ##load-immediate { dst V int-regs 3 } { val 8 } }
- T{ ##set-slot-imm { obj V int-regs 1 } { src V int-regs 3 } }
+ T{ ##allot { dst V int-rep 1 } { temp V int-rep 2 } }
+ T{ ##replace { src V int-rep 1 } { loc D 0 } }
+ T{ ##load-immediate { dst V int-rep 3 } { val 8 } }
+ T{ ##set-slot-imm { obj V int-rep 1 } { src V int-rep 3 } }
} ] [ V{
- T{ ##allot { dst V int-regs 1 } { temp V int-regs 2 } }
- T{ ##replace { src V int-regs 1 } { loc D 0 } }
- T{ ##load-immediate { dst V int-regs 3 } { val 8 } }
- T{ ##set-slot-imm { obj V int-regs 1 } { src V int-regs 3 } }
+ T{ ##allot { dst V int-rep 1 } { temp V int-rep 2 } }
+ T{ ##replace { src V int-rep 1 } { loc D 0 } }
+ T{ ##load-immediate { dst V int-rep 3 } { val 8 } }
+ T{ ##set-slot-imm { obj V int-rep 1 } { src V int-rep 3 } }
} test-dce ] unit-test
! Prettyprinting
M: vreg pprint*
<block
- \ V pprint-word [ reg-class>> pprint* ] [ n>> pprint* ] bi
+ \ V pprint-word [ rep>> pprint* ] [ n>> pprint* ] bi
block> ;
: pprint-loc ( loc word -- ) <block pprint-word n>> pprint* block> ;
compiler.cfg.registers ;
V{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##peek f V int-regs 1 D 0 }
- T{ ##peek f V int-regs 2 D 0 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##peek f V int-rep 1 D 0 }
+ T{ ##peek f V int-rep 2 D 0 }
} 1 test-bb
V{
- T{ ##replace f V int-regs 2 D 0 }
+ T{ ##replace f V int-rep 2 D 0 }
} 2 test-bb
1 2 edge
V{
- T{ ##replace f V int-regs 0 D 0 }
+ T{ ##replace f V int-rep 0 D 0 }
} 3 test-bb
2 3 edge
V{ } 4 test-bb
V{ } 5 test-bb
3 { 4 5 } edges
V{
- T{ ##phi f V int-regs 2 H{ { 2 V int-regs 0 } { 3 V int-regs 1 } } }
+ T{ ##phi f V int-rep 2 H{ { 2 V int-rep 0 } { 3 V int-rep 1 } } }
} 6 test-bb
4 6 edge
5 6 edge
V{
T{ ##inc-d f 3 }
- T{ ##replace f V int-regs 0 D 1 }
+ T{ ##replace f V int-rep 0 D 1 }
} 0 test-bb
V{
- T{ ##box-float f V int-regs 0 V int-regs 1 }
+ T{ ##box-float f V int-rep 0 V int-rep 1 }
} 1 test-bb
0 1 edge
: insert-gc-check ( bb -- )
dup '[
- i i f _ uninitialized-locs \ ##gc new-insn
+ i i f f _ uninitialized-locs \ ##gc new-insn
prefix
] change-instructions drop ;
-! Copyright (C) 2008 Slava Pestov.
+! Copyright (C) 2008, 2009 Slava Pestov.
! See http://factorcode.org/license.txt for BSD license.
-USING: arrays byte-arrays kernel layouts math namespaces
+USING: accessors arrays byte-arrays kernel layouts math namespaces
sequences classes.tuple cpu.architecture compiler.cfg.registers
compiler.cfg.instructions ;
IN: compiler.cfg.hats
-: i ( -- vreg ) int-regs next-vreg ; inline
+: i ( -- vreg ) int-rep next-vreg ; inline
: ^^i ( -- vreg vreg ) i dup ; inline
: ^^i1 ( obj -- vreg vreg obj ) [ ^^i ] dip ; inline
: ^^i2 ( obj obj -- vreg vreg obj obj ) [ ^^i ] 2dip ; inline
: ^^i3 ( obj obj obj -- vreg vreg obj obj obj ) [ ^^i ] 3dip ; inline
-: d ( -- vreg ) double-float-regs next-vreg ; inline
+: d ( -- vreg ) double-float-rep next-vreg ; inline
: ^^d ( -- vreg vreg ) d dup ; inline
: ^^d1 ( obj -- vreg vreg obj ) [ ^^d ] dip ; inline
: ^^d2 ( obj obj -- vreg vreg obj obj ) [ ^^d ] 2dip ; inline
: ^^d3 ( obj obj obj -- vreg vreg obj obj obj ) [ ^^d ] 3dip ; inline
: ^^load-literal ( obj -- dst ) ^^i1 ##load-literal ; inline
-: ^^copy ( src -- dst ) ^^i1 ##copy ; inline
+: ^^copy ( src -- dst ) ^^i1 dup rep>> ##copy ; inline
: ^^slot ( obj slot tag -- dst ) ^^i3 i ##slot ; inline
: ^^slot-imm ( obj slot tag -- dst ) ^^i3 ##slot-imm ; inline
: ^^set-slot ( src obj slot tag -- ) i ##set-slot ; inline
INSN: ##integer>float < ##unary ;
! Boxing and unboxing
-INSN: ##copy < ##unary ;
-INSN: ##copy-float < ##unary ;
+INSN: ##copy < ##unary rep ;
INSN: ##unbox-float < ##unary ;
INSN: ##unbox-any-c-ptr < ##unary/temp ;
INSN: ##box-float < ##unary/temp ;
INSN: ##fixnum-sub < ##fixnum-overflow ;
INSN: ##fixnum-mul < ##fixnum-overflow ;
-INSN: ##gc temp1 temp2 live-values uninitialized-locs ;
+INSN: ##gc temp1 temp2 data-values tagged-values uninitialized-locs ;
! Instructions used by machine IR only.
INSN: _prologue stack-frame ;
TUPLE: spill-slot n ; C: <spill-slot> spill-slot
-INSN: _gc temp1 temp2 gc-roots gc-root-count gc-root-size uninitialized-locs ;
+INSN: _gc temp1 temp2 data-values tagged-values gc-root-size uninitialized-locs ;
! These instructions operate on machine registers and not
! virtual registers
-INSN: _spill src class n ;
-INSN: _reload dst class n ;
-INSN: _copy dst src class ;
-INSN: _spill-counts counts ;
+INSN: _spill src rep n ;
+INSN: _reload dst rep n ;
+INSN: _spill-area-size n ;
! Instructions that use vregs
UNION: vreg-insn
: emit-alien-cell-setter ( node -- )
[ ##set-alien-cell ] inline-alien-cell-setter ;
-: emit-alien-float-getter ( node reg-class -- )
+: emit-alien-float-getter ( node rep -- )
'[
_ {
- { single-float-regs [ ^^alien-float ] }
- { double-float-regs [ ^^alien-double ] }
+ { single-float-rep [ ^^alien-float ] }
+ { double-float-rep [ ^^alien-double ] }
} case ^^box-float
] inline-alien-getter ;
-: emit-alien-float-setter ( node reg-class -- )
+: emit-alien-float-setter ( node rep -- )
'[
_ {
- { single-float-regs [ ##set-alien-float ] }
- { double-float-regs [ ##set-alien-double ] }
+ { single-float-rep [ ##set-alien-float ] }
+ { double-float-rep [ ##set-alien-double ] }
} case
] inline-alien-float-setter ;
{ \ alien.accessors:set-alien-signed-4 [ 4 emit-alien-integer-setter ] }
{ \ alien.accessors:alien-cell [ emit-alien-cell-getter ] }
{ \ alien.accessors:set-alien-cell [ emit-alien-cell-setter ] }
- { \ alien.accessors:alien-float [ single-float-regs emit-alien-float-getter ] }
- { \ alien.accessors:set-alien-float [ single-float-regs emit-alien-float-setter ] }
- { \ alien.accessors:alien-double [ double-float-regs emit-alien-float-getter ] }
- { \ alien.accessors:set-alien-double [ double-float-regs emit-alien-float-setter ] }
+ { \ alien.accessors:alien-float [ single-float-rep emit-alien-float-getter ] }
+ { \ alien.accessors:set-alien-float [ single-float-rep emit-alien-float-setter ] }
+ { \ alien.accessors:alien-double [ double-float-rep emit-alien-float-getter ] }
+ { \ alien.accessors:set-alien-double [ double-float-rep emit-alien-float-setter ] }
} case ;
! See http://factorcode.org/license.txt for BSD license.
USING: accessors assocs combinators cpu.architecture fry heaps
kernel math math.order namespaces sequences vectors
-compiler.cfg.linear-scan.live-intervals ;
+compiler.cfg compiler.cfg.linear-scan.live-intervals ;
IN: compiler.cfg.linear-scan.allocation.state
! Start index of current live interval. We ensure that all
SYMBOL: active-intervals
: active-intervals-for ( vreg -- seq )
- reg-class>> active-intervals get at ;
+ rep>> reg-class-of active-intervals get at ;
: add-active ( live-interval -- )
dup vreg>> active-intervals-for push ;
SYMBOL: inactive-intervals
: inactive-intervals-for ( vreg -- seq )
- reg-class>> inactive-intervals get at ;
+ rep>> reg-class-of inactive-intervals get at ;
: add-inactive ( live-interval -- )
dup vreg>> inactive-intervals-for push ;
[ dup start>> unhandled-intervals get heap-push ]
bi ;
-CONSTANT: reg-classes { int-regs double-float-regs }
-
: reg-class-assoc ( quot -- assoc )
[ reg-classes ] dip { } map>assoc ; inline
-! Mapping from register classes to spill counts
-SYMBOL: spill-counts
-
-: next-spill-slot ( reg-class -- n )
- spill-counts get [ dup 1 + ] change-at ;
+: next-spill-slot ( rep -- n )
+ rep-size cfg get
+ [ swap [ align dup ] [ + ] bi ] change-spill-area-size drop ;
! Mapping from vregs to spill slots
SYMBOL: spill-slots
: assign-spill-slot ( vreg -- n )
- spill-slots get [ reg-class>> next-spill-slot ] cache ;
+ spill-slots get [ rep>> next-spill-slot ] cache ;
: init-allocator ( registers -- )
registers set
[ V{ } clone ] reg-class-assoc active-intervals set
[ V{ } clone ] reg-class-assoc inactive-intervals set
V{ } clone handled-intervals set
- [ 0 ] reg-class-assoc spill-counts set
+ cfg get 0 >>spill-area-size drop
H{ } clone spill-slots set
-1 progress set ;
! A utility used by register-status and spill-status words
: free-positions ( new -- assoc )
- vreg>> reg-class>> registers get at [ 1/0. ] H{ } map>assoc ;
+ vreg>> rep>> reg-class-of registers get at [ 1/0. ] H{ } map>assoc ;
: add-use-position ( n reg assoc -- ) [ [ min ] when* ] change-at ;
! Copyright (C) 2008, 2009 Slava Pestov.
! See http://factorcode.org/license.txt for BSD license.
USING: accessors kernel math assocs namespaces sequences heaps
-fry make combinators sets locals
+fry make combinators sets locals arrays
cpu.architecture
compiler.cfg
compiler.cfg.rpo
init-unhandled ;
: insert-spill ( live-interval -- )
- [ reg>> ] [ vreg>> reg-class>> ] [ spill-to>> ] tri _spill ;
+ [ reg>> ] [ vreg>> rep>> ] [ spill-to>> ] tri _spill ;
: handle-spill ( live-interval -- )
dup spill-to>> [ insert-spill ] [ drop ] if ;
pending-interval-heap get (expire-old-intervals) ;
: insert-reload ( live-interval -- )
- [ reg>> ] [ vreg>> reg-class>> ] [ reload-from>> ] tri _reload ;
+ [ reg>> ] [ vreg>> rep>> ] [ reload-from>> ] tri _reload ;
: handle-reload ( live-interval -- )
dup reload-from>> [ insert-reload ] [ drop ] if ;
M: vreg-insn assign-registers-in-insn
[ assign-insn-defs ] [ assign-insn-uses ] [ assign-insn-temps ] tri ;
+! TODO: needs tagged-rep
+
+: trace-on-gc ( assoc -- assoc' )
+ ! When a GC occurs, virtual registers which contain tagged data
+ ! are traced by the GC. Outputs a sequence physical registers.
+ [ drop rep>> int-rep eq? ] { } assoc-filter-as values ;
+
+: spill-on-gc? ( vreg reg -- ? )
+ [ rep>> int-rep? not ] [ spill-slot? not ] bi* and ;
+
+: spill-on-gc ( assoc -- assoc' )
+ ! When a GC occurs, virtual registers which contain untagged data,
+ ! and are stored in physical registers, are saved to their spill
+ ! slots. Outputs sequence of triples:
+ ! - physical register
+ ! - spill slot
+ ! - representation
+ [
+ [
+ 2dup spill-on-gc?
+ [ swap [ assign-spill-slot ] [ rep>> ] bi 3array , ] [ 2drop ] if
+ ] assoc-each
+ ] { } make ;
+
M: ##gc assign-registers-in-insn
- ! This works because ##gc is always the first instruction
- ! in a block.
+ ! Since ##gc is always the first instruction in a block, the set of
+ ! values live at the ##gc is just live-in.
dup call-next-method
- basic-block get register-live-ins get at >>live-values
+ basic-block get register-live-ins get at
+ [ trace-on-gc >>tagged-values ] [ spill-on-gc >>data-values ] bi
drop ;
M: insn assign-registers-in-insn drop ;
IN: compiler.cfg.linear-scan.tests
USING: tools.test random sorting sequences sets hashtables assocs
kernel fry arrays splitting namespaces math accessors vectors locals
-math.order grouping strings strings.private classes
+math.order grouping strings strings.private classes layouts
cpu.architecture
compiler.cfg
compiler.cfg.optimizer
{ T{ live-range f 0 5 } } 0 split-ranges
] unit-test
-H{ { int-regs 10 } { float-regs 20 } } clone spill-counts set
+cfg new 0 >>spill-area-size cfg set
H{ } spill-slots set
[
T{ live-interval
- { vreg T{ vreg { reg-class int-regs } { n 1 } } }
+ { vreg V single-float-rep 1 }
{ start 0 }
{ end 2 }
{ uses V{ 0 1 } }
{ ranges V{ T{ live-range f 0 2 } } }
- { spill-to 10 }
+ { spill-to 0 }
}
T{ live-interval
- { vreg T{ vreg { reg-class int-regs } { n 1 } } }
+ { vreg V single-float-rep 1 }
{ start 5 }
{ end 5 }
{ uses V{ 5 } }
{ ranges V{ T{ live-range f 5 5 } } }
- { reload-from 10 }
+ { reload-from 0 }
}
] [
T{ live-interval
- { vreg T{ vreg { reg-class int-regs } { n 1 } } }
+ { vreg V single-float-rep 1 }
{ start 0 }
{ end 5 }
{ uses V{ 0 1 5 } }
[
T{ live-interval
- { vreg T{ vreg { reg-class int-regs } { n 2 } } }
+ { vreg V single-float-rep 2 }
{ start 0 }
{ end 1 }
{ uses V{ 0 } }
{ ranges V{ T{ live-range f 0 1 } } }
- { spill-to 11 }
+ { spill-to 4 }
}
T{ live-interval
- { vreg T{ vreg { reg-class int-regs } { n 2 } } }
+ { vreg V single-float-rep 2 }
{ start 1 }
{ end 5 }
{ uses V{ 1 5 } }
{ ranges V{ T{ live-range f 1 5 } } }
- { reload-from 11 }
+ { reload-from 4 }
}
] [
T{ live-interval
- { vreg T{ vreg { reg-class int-regs } { n 2 } } }
+ { vreg V single-float-rep 2 }
{ start 0 }
{ end 5 }
{ uses V{ 0 1 5 } }
[
T{ live-interval
- { vreg T{ vreg { reg-class int-regs } { n 3 } } }
+ { vreg V single-float-rep 3 }
{ start 0 }
{ end 1 }
{ uses V{ 0 } }
{ ranges V{ T{ live-range f 0 1 } } }
- { spill-to 12 }
+ { spill-to 8 }
}
T{ live-interval
- { vreg T{ vreg { reg-class int-regs } { n 3 } } }
+ { vreg V single-float-rep 3 }
{ start 20 }
{ end 30 }
{ uses V{ 20 30 } }
{ ranges V{ T{ live-range f 20 30 } } }
- { reload-from 12 }
+ { reload-from 8 }
}
] [
T{ live-interval
- { vreg T{ vreg { reg-class int-regs } { n 3 } } }
+ { vreg V single-float-rep 3 }
{ start 0 }
{ end 30 }
{ uses V{ 0 20 30 } }
{ int-regs
V{
T{ live-interval
- { vreg T{ vreg { reg-class int-regs } { n 1 } } }
+ { vreg V int-rep 1 }
{ reg 1 }
{ start 1 }
{ end 15 }
{ uses V{ 1 3 7 10 15 } }
}
T{ live-interval
- { vreg T{ vreg { reg-class int-regs } { n 2 } } }
+ { vreg V int-rep 2 }
{ reg 2 }
{ start 3 }
{ end 8 }
{ uses V{ 3 4 8 } }
}
T{ live-interval
- { vreg T{ vreg { reg-class int-regs } { n 3 } } }
+ { vreg V int-rep 3 }
{ reg 3 }
{ start 3 }
{ end 10 }
} active-intervals set
H{ } inactive-intervals set
T{ live-interval
- { vreg T{ vreg { reg-class int-regs } { n 1 } } }
+ { vreg V int-rep 1 }
{ start 5 }
{ end 5 }
{ uses V{ 5 } }
{ int-regs
V{
T{ live-interval
- { vreg T{ vreg { reg-class int-regs } { n 1 } } }
+ { vreg V int-rep 1 }
{ reg 1 }
{ start 1 }
{ end 15 }
{ uses V{ 1 } }
}
T{ live-interval
- { vreg T{ vreg { reg-class int-regs } { n 2 } } }
+ { vreg V int-rep 2 }
{ reg 2 }
{ start 3 }
{ end 8 }
} active-intervals set
H{ } inactive-intervals set
T{ live-interval
- { vreg T{ vreg { reg-class int-regs } { n 3 } } }
+ { vreg V int-rep 3 }
{ start 5 }
{ end 5 }
{ uses V{ 5 } }
[ ] [
{
T{ live-interval
- { vreg T{ vreg { n 1 } { reg-class int-regs } } }
+ { vreg V int-rep 1 }
{ start 0 }
{ end 100 }
{ uses V{ 0 100 } }
[ ] [
{
T{ live-interval
- { vreg T{ vreg { n 1 } { reg-class int-regs } } }
+ { vreg V int-rep 1 }
{ start 0 }
{ end 10 }
{ uses V{ 0 10 } }
{ ranges V{ T{ live-range f 0 10 } } }
}
T{ live-interval
- { vreg T{ vreg { n 2 } { reg-class int-regs } } }
+ { vreg V int-rep 2 }
{ start 11 }
{ end 20 }
{ uses V{ 11 20 } }
[ ] [
{
T{ live-interval
- { vreg T{ vreg { n 1 } { reg-class int-regs } } }
+ { vreg V int-rep 1 }
{ start 0 }
{ end 100 }
{ uses V{ 0 100 } }
{ ranges V{ T{ live-range f 0 100 } } }
}
T{ live-interval
- { vreg T{ vreg { n 2 } { reg-class int-regs } } }
+ { vreg V int-rep 2 }
{ start 30 }
{ end 60 }
{ uses V{ 30 60 } }
[ ] [
{
T{ live-interval
- { vreg T{ vreg { n 1 } { reg-class int-regs } } }
+ { vreg V int-rep 1 }
{ start 0 }
{ end 100 }
{ uses V{ 0 100 } }
{ ranges V{ T{ live-range f 0 100 } } }
}
T{ live-interval
- { vreg T{ vreg { n 2 } { reg-class int-regs } } }
+ { vreg V int-rep 2 }
{ start 30 }
{ end 200 }
{ uses V{ 30 200 } }
[
{
T{ live-interval
- { vreg T{ vreg { n 1 } { reg-class int-regs } } }
+ { vreg V int-rep 1 }
{ start 0 }
{ end 100 }
{ uses V{ 0 100 } }
{ ranges V{ T{ live-range f 0 100 } } }
}
T{ live-interval
- { vreg T{ vreg { n 2 } { reg-class int-regs } } }
+ { vreg V int-rep 2 }
{ start 30 }
{ end 100 }
{ uses V{ 30 100 } }
[ ] [
{
T{ live-interval
- { vreg T{ vreg { n 1 } { reg-class int-regs } } }
+ { vreg V int-rep 1 }
{ start 0 }
{ end 20 }
{ uses V{ 0 10 20 } }
{ ranges V{ T{ live-range f 0 2 } T{ live-range f 10 20 } } }
}
T{ live-interval
- { vreg T{ vreg { n 2 } { reg-class int-regs } } }
+ { vreg V int-rep 2 }
{ start 0 }
{ end 20 }
{ uses V{ 0 10 20 } }
{ ranges V{ T{ live-range f 0 2 } T{ live-range f 10 20 } } }
}
T{ live-interval
- { vreg T{ vreg { n 3 } { reg-class int-regs } } }
+ { vreg V int-rep 3 }
{ start 4 }
{ end 8 }
{ uses V{ 6 } }
{ ranges V{ T{ live-range f 4 8 } } }
}
T{ live-interval
- { vreg T{ vreg { n 4 } { reg-class int-regs } } }
+ { vreg V int-rep 4 }
{ start 4 }
{ end 8 }
{ uses V{ 8 } }
! This guy will invoke the 'spill partially available' code path
T{ live-interval
- { vreg T{ vreg { n 5 } { reg-class int-regs } } }
+ { vreg V int-rep 5 }
{ start 4 }
{ end 8 }
{ uses V{ 8 } }
[ ] [
{
T{ live-interval
- { vreg T{ vreg { n 1 } { reg-class int-regs } } }
+ { vreg V int-rep 1 }
{ start 0 }
{ end 10 }
{ uses V{ 0 6 10 } }
! This guy will invoke the 'spill new' code path
T{ live-interval
- { vreg T{ vreg { n 5 } { reg-class int-regs } } }
+ { vreg V int-rep 5 }
{ start 2 }
{ end 8 }
{ uses V{ 8 } }
max-insns get [ dup ] H{ } map>assoc available set
[
\ live-interval new
- swap int-regs swap vreg boa >>vreg
+ swap int-rep swap vreg boa >>vreg
max-uses get random 2 max [ not-taken 2 * ] replicate natural-sort
[ >>uses ] [ first >>start ] bi
dup uses>> last >>end
[ ] [
{
T{ live-interval
- { vreg V int-regs 70 }
+ { vreg V int-rep 70 }
{ start 14 }
{ end 17 }
{ uses V{ 14 15 16 17 } }
}
T{ live-interval
- { vreg V int-regs 67 }
+ { vreg V int-rep 67 }
{ start 13 }
{ end 14 }
{ uses V{ 13 14 } }
}
T{ live-interval
- { vreg V int-regs 30 }
+ { vreg V int-rep 30 }
{ start 4 }
{ end 18 }
{ uses V{ 4 12 16 17 18 } }
}
T{ live-interval
- { vreg V int-regs 27 }
+ { vreg V int-rep 27 }
{ start 3 }
{ end 13 }
{ uses V{ 3 7 13 } }
}
T{ live-interval
- { vreg V int-regs 59 }
+ { vreg V int-rep 59 }
{ start 10 }
{ end 18 }
{ uses V{ 10 11 12 18 } }
}
T{ live-interval
- { vreg V int-regs 60 }
+ { vreg V int-rep 60 }
{ start 12 }
{ end 17 }
{ uses V{ 12 17 } }
}
T{ live-interval
- { vreg V int-regs 56 }
+ { vreg V int-rep 56 }
{ start 9 }
{ end 10 }
{ uses V{ 9 10 } }
[ ] [
{
T{ live-interval
- { vreg V int-regs 3687168 }
+ { vreg V int-rep 3687168 }
{ start 106 }
{ end 112 }
{ uses V{ 106 112 } }
}
T{ live-interval
- { vreg V int-regs 3687169 }
+ { vreg V int-rep 3687169 }
{ start 107 }
{ end 113 }
{ uses V{ 107 113 } }
}
T{ live-interval
- { vreg V int-regs 3687727 }
+ { vreg V int-rep 3687727 }
{ start 190 }
{ end 198 }
{ uses V{ 190 195 198 } }
}
T{ live-interval
- { vreg V int-regs 3686445 }
+ { vreg V int-rep 3686445 }
{ start 43 }
{ end 44 }
{ uses V{ 43 44 } }
}
T{ live-interval
- { vreg V int-regs 3686195 }
+ { vreg V int-rep 3686195 }
{ start 5 }
{ end 11 }
{ uses V{ 5 11 } }
}
T{ live-interval
- { vreg V int-regs 3686449 }
+ { vreg V int-rep 3686449 }
{ start 44 }
{ end 56 }
{ uses V{ 44 45 45 46 56 } }
}
T{ live-interval
- { vreg V int-regs 3686198 }
+ { vreg V int-rep 3686198 }
{ start 8 }
{ end 10 }
{ uses V{ 8 9 10 } }
}
T{ live-interval
- { vreg V int-regs 3686454 }
+ { vreg V int-rep 3686454 }
{ start 46 }
{ end 49 }
{ uses V{ 46 47 47 49 } }
}
T{ live-interval
- { vreg V int-regs 3686196 }
+ { vreg V int-rep 3686196 }
{ start 6 }
{ end 12 }
{ uses V{ 6 12 } }
}
T{ live-interval
- { vreg V int-regs 3686197 }
+ { vreg V int-rep 3686197 }
{ start 7 }
{ end 14 }
{ uses V{ 7 13 14 } }
}
T{ live-interval
- { vreg V int-regs 3686455 }
+ { vreg V int-rep 3686455 }
{ start 48 }
{ end 51 }
{ uses V{ 48 51 } }
}
T{ live-interval
- { vreg V int-regs 3686463 }
+ { vreg V int-rep 3686463 }
{ start 52 }
{ end 53 }
{ uses V{ 52 53 } }
}
T{ live-interval
- { vreg V int-regs 3686460 }
+ { vreg V int-rep 3686460 }
{ start 49 }
{ end 52 }
{ uses V{ 49 50 50 52 } }
}
T{ live-interval
- { vreg V int-regs 3686461 }
+ { vreg V int-rep 3686461 }
{ start 51 }
{ end 71 }
{ uses V{ 51 52 64 68 71 } }
}
T{ live-interval
- { vreg V int-regs 3686464 }
+ { vreg V int-rep 3686464 }
{ start 53 }
{ end 54 }
{ uses V{ 53 54 } }
}
T{ live-interval
- { vreg V int-regs 3686465 }
+ { vreg V int-rep 3686465 }
{ start 54 }
{ end 76 }
{ uses V{ 54 55 55 76 } }
}
T{ live-interval
- { vreg V int-regs 3686470 }
+ { vreg V int-rep 3686470 }
{ start 58 }
{ end 60 }
{ uses V{ 58 59 59 60 } }
}
T{ live-interval
- { vreg V int-regs 3686469 }
+ { vreg V int-rep 3686469 }
{ start 56 }
{ end 58 }
{ uses V{ 56 57 57 58 } }
}
T{ live-interval
- { vreg V int-regs 3686473 }
+ { vreg V int-rep 3686473 }
{ start 60 }
{ end 62 }
{ uses V{ 60 61 61 62 } }
}
T{ live-interval
- { vreg V int-regs 3686479 }
+ { vreg V int-rep 3686479 }
{ start 62 }
{ end 64 }
{ uses V{ 62 63 63 64 } }
}
T{ live-interval
- { vreg V int-regs 3686735 }
+ { vreg V int-rep 3686735 }
{ start 78 }
{ end 96 }
{ uses V{ 78 79 79 96 } }
}
T{ live-interval
- { vreg V int-regs 3686482 }
+ { vreg V int-rep 3686482 }
{ start 64 }
{ end 65 }
{ uses V{ 64 65 } }
}
T{ live-interval
- { vreg V int-regs 3686483 }
+ { vreg V int-rep 3686483 }
{ start 65 }
{ end 66 }
{ uses V{ 65 66 } }
}
T{ live-interval
- { vreg V int-regs 3687510 }
+ { vreg V int-rep 3687510 }
{ start 168 }
{ end 171 }
{ uses V{ 168 171 } }
}
T{ live-interval
- { vreg V int-regs 3687511 }
+ { vreg V int-rep 3687511 }
{ start 169 }
{ end 176 }
{ uses V{ 169 176 } }
}
T{ live-interval
- { vreg V int-regs 3686484 }
+ { vreg V int-rep 3686484 }
{ start 66 }
{ end 75 }
{ uses V{ 66 67 67 75 } }
}
T{ live-interval
- { vreg V int-regs 3687509 }
+ { vreg V int-rep 3687509 }
{ start 162 }
{ end 163 }
{ uses V{ 162 163 } }
}
T{ live-interval
- { vreg V int-regs 3686491 }
+ { vreg V int-rep 3686491 }
{ start 68 }
{ end 69 }
{ uses V{ 68 69 } }
}
T{ live-interval
- { vreg V int-regs 3687512 }
+ { vreg V int-rep 3687512 }
{ start 170 }
{ end 178 }
{ uses V{ 170 177 178 } }
}
T{ live-interval
- { vreg V int-regs 3687515 }
+ { vreg V int-rep 3687515 }
{ start 172 }
{ end 173 }
{ uses V{ 172 173 } }
}
T{ live-interval
- { vreg V int-regs 3686492 }
+ { vreg V int-rep 3686492 }
{ start 69 }
{ end 74 }
{ uses V{ 69 70 70 74 } }
}
T{ live-interval
- { vreg V int-regs 3687778 }
+ { vreg V int-rep 3687778 }
{ start 202 }
{ end 208 }
{ uses V{ 202 208 } }
}
T{ live-interval
- { vreg V int-regs 3686499 }
+ { vreg V int-rep 3686499 }
{ start 71 }
{ end 72 }
{ uses V{ 71 72 } }
}
T{ live-interval
- { vreg V int-regs 3687520 }
+ { vreg V int-rep 3687520 }
{ start 174 }
{ end 175 }
{ uses V{ 174 175 } }
}
T{ live-interval
- { vreg V int-regs 3687779 }
+ { vreg V int-rep 3687779 }
{ start 203 }
{ end 209 }
{ uses V{ 203 209 } }
}
T{ live-interval
- { vreg V int-regs 3687782 }
+ { vreg V int-rep 3687782 }
{ start 206 }
{ end 207 }
{ uses V{ 206 207 } }
}
T{ live-interval
- { vreg V int-regs 3686503 }
+ { vreg V int-rep 3686503 }
{ start 74 }
{ end 75 }
{ uses V{ 74 75 } }
}
T{ live-interval
- { vreg V int-regs 3686500 }
+ { vreg V int-rep 3686500 }
{ start 72 }
{ end 74 }
{ uses V{ 72 73 73 74 } }
}
T{ live-interval
- { vreg V int-regs 3687780 }
+ { vreg V int-rep 3687780 }
{ start 204 }
{ end 210 }
{ uses V{ 204 210 } }
}
T{ live-interval
- { vreg V int-regs 3686506 }
+ { vreg V int-rep 3686506 }
{ start 75 }
{ end 76 }
{ uses V{ 75 76 } }
}
T{ live-interval
- { vreg V int-regs 3687530 }
+ { vreg V int-rep 3687530 }
{ start 185 }
{ end 192 }
{ uses V{ 185 192 } }
}
T{ live-interval
- { vreg V int-regs 3687528 }
+ { vreg V int-rep 3687528 }
{ start 183 }
{ end 198 }
{ uses V{ 183 198 } }
}
T{ live-interval
- { vreg V int-regs 3687529 }
+ { vreg V int-rep 3687529 }
{ start 184 }
{ end 197 }
{ uses V{ 184 197 } }
}
T{ live-interval
- { vreg V int-regs 3687781 }
+ { vreg V int-rep 3687781 }
{ start 205 }
{ end 211 }
{ uses V{ 205 211 } }
}
T{ live-interval
- { vreg V int-regs 3687535 }
+ { vreg V int-rep 3687535 }
{ start 187 }
{ end 194 }
{ uses V{ 187 194 } }
}
T{ live-interval
- { vreg V int-regs 3686252 }
+ { vreg V int-rep 3686252 }
{ start 9 }
{ end 17 }
{ uses V{ 9 15 17 } }
}
T{ live-interval
- { vreg V int-regs 3686509 }
+ { vreg V int-rep 3686509 }
{ start 76 }
{ end 90 }
{ uses V{ 76 87 90 } }
}
T{ live-interval
- { vreg V int-regs 3687532 }
+ { vreg V int-rep 3687532 }
{ start 186 }
{ end 196 }
{ uses V{ 186 196 } }
}
T{ live-interval
- { vreg V int-regs 3687538 }
+ { vreg V int-rep 3687538 }
{ start 188 }
{ end 193 }
{ uses V{ 188 193 } }
}
T{ live-interval
- { vreg V int-regs 3687827 }
+ { vreg V int-rep 3687827 }
{ start 217 }
{ end 219 }
{ uses V{ 217 219 } }
}
T{ live-interval
- { vreg V int-regs 3687825 }
+ { vreg V int-rep 3687825 }
{ start 215 }
{ end 218 }
{ uses V{ 215 216 218 } }
}
T{ live-interval
- { vreg V int-regs 3687831 }
+ { vreg V int-rep 3687831 }
{ start 218 }
{ end 219 }
{ uses V{ 218 219 } }
}
T{ live-interval
- { vreg V int-regs 3686296 }
+ { vreg V int-rep 3686296 }
{ start 16 }
{ end 18 }
{ uses V{ 16 18 } }
}
T{ live-interval
- { vreg V int-regs 3686302 }
+ { vreg V int-rep 3686302 }
{ start 29 }
{ end 31 }
{ uses V{ 29 31 } }
}
T{ live-interval
- { vreg V int-regs 3687838 }
+ { vreg V int-rep 3687838 }
{ start 231 }
{ end 232 }
{ uses V{ 231 232 } }
}
T{ live-interval
- { vreg V int-regs 3686300 }
+ { vreg V int-rep 3686300 }
{ start 26 }
{ end 27 }
{ uses V{ 26 27 } }
}
T{ live-interval
- { vreg V int-regs 3686301 }
+ { vreg V int-rep 3686301 }
{ start 27 }
{ end 30 }
{ uses V{ 27 28 28 30 } }
}
T{ live-interval
- { vreg V int-regs 3686306 }
+ { vreg V int-rep 3686306 }
{ start 37 }
{ end 93 }
{ uses V{ 37 82 93 } }
}
T{ live-interval
- { vreg V int-regs 3686307 }
+ { vreg V int-rep 3686307 }
{ start 38 }
{ end 88 }
{ uses V{ 38 85 88 } }
}
T{ live-interval
- { vreg V int-regs 3687837 }
+ { vreg V int-rep 3687837 }
{ start 222 }
{ end 223 }
{ uses V{ 222 223 } }
}
T{ live-interval
- { vreg V int-regs 3686305 }
+ { vreg V int-rep 3686305 }
{ start 36 }
{ end 81 }
{ uses V{ 36 42 77 81 } }
}
T{ live-interval
- { vreg V int-regs 3686310 }
+ { vreg V int-rep 3686310 }
{ start 39 }
{ end 95 }
{ uses V{ 39 84 95 } }
}
T{ live-interval
- { vreg V int-regs 3687836 }
+ { vreg V int-rep 3687836 }
{ start 227 }
{ end 228 }
{ uses V{ 227 228 } }
}
T{ live-interval
- { vreg V int-regs 3687839 }
+ { vreg V int-rep 3687839 }
{ start 239 }
{ end 246 }
{ uses V{ 239 245 246 } }
}
T{ live-interval
- { vreg V int-regs 3687841 }
+ { vreg V int-rep 3687841 }
{ start 240 }
{ end 241 }
{ uses V{ 240 241 } }
}
T{ live-interval
- { vreg V int-regs 3687845 }
+ { vreg V int-rep 3687845 }
{ start 241 }
{ end 243 }
{ uses V{ 241 243 } }
}
T{ live-interval
- { vreg V int-regs 3686315 }
+ { vreg V int-rep 3686315 }
{ start 40 }
{ end 94 }
{ uses V{ 40 83 94 } }
}
T{ live-interval
- { vreg V int-regs 3687846 }
+ { vreg V int-rep 3687846 }
{ start 242 }
{ end 245 }
{ uses V{ 242 245 } }
}
T{ live-interval
- { vreg V int-regs 3687849 }
+ { vreg V int-rep 3687849 }
{ start 243 }
{ end 245 }
{ uses V{ 243 244 244 245 } }
}
T{ live-interval
- { vreg V int-regs 3687850 }
+ { vreg V int-rep 3687850 }
{ start 245 }
{ end 245 }
{ uses V{ 245 } }
}
T{ live-interval
- { vreg V int-regs 3687851 }
+ { vreg V int-rep 3687851 }
{ start 246 }
{ end 246 }
{ uses V{ 246 } }
}
T{ live-interval
- { vreg V int-regs 3687852 }
+ { vreg V int-rep 3687852 }
{ start 246 }
{ end 246 }
{ uses V{ 246 } }
}
T{ live-interval
- { vreg V int-regs 3687853 }
+ { vreg V int-rep 3687853 }
{ start 247 }
{ end 248 }
{ uses V{ 247 248 } }
}
T{ live-interval
- { vreg V int-regs 3687854 }
+ { vreg V int-rep 3687854 }
{ start 249 }
{ end 250 }
{ uses V{ 249 250 } }
}
T{ live-interval
- { vreg V int-regs 3687855 }
+ { vreg V int-rep 3687855 }
{ start 258 }
{ end 259 }
{ uses V{ 258 259 } }
}
T{ live-interval
- { vreg V int-regs 3687080 }
+ { vreg V int-rep 3687080 }
{ start 280 }
{ end 285 }
{ uses V{ 280 285 } }
}
T{ live-interval
- { vreg V int-regs 3687081 }
+ { vreg V int-rep 3687081 }
{ start 281 }
{ end 286 }
{ uses V{ 281 286 } }
}
T{ live-interval
- { vreg V int-regs 3687082 }
+ { vreg V int-rep 3687082 }
{ start 282 }
{ end 287 }
{ uses V{ 282 287 } }
}
T{ live-interval
- { vreg V int-regs 3687083 }
+ { vreg V int-rep 3687083 }
{ start 283 }
{ end 288 }
{ uses V{ 283 288 } }
}
T{ live-interval
- { vreg V int-regs 3687085 }
+ { vreg V int-rep 3687085 }
{ start 284 }
{ end 299 }
{ uses V{ 284 285 286 287 288 296 299 } }
}
T{ live-interval
- { vreg V int-regs 3687086 }
+ { vreg V int-rep 3687086 }
{ start 284 }
{ end 284 }
{ uses V{ 284 } }
}
T{ live-interval
- { vreg V int-regs 3687087 }
+ { vreg V int-rep 3687087 }
{ start 289 }
{ end 293 }
{ uses V{ 289 293 } }
}
T{ live-interval
- { vreg V int-regs 3687088 }
+ { vreg V int-rep 3687088 }
{ start 290 }
{ end 294 }
{ uses V{ 290 294 } }
}
T{ live-interval
- { vreg V int-regs 3687089 }
+ { vreg V int-rep 3687089 }
{ start 291 }
{ end 297 }
{ uses V{ 291 297 } }
}
T{ live-interval
- { vreg V int-regs 3687090 }
+ { vreg V int-rep 3687090 }
{ start 292 }
{ end 298 }
{ uses V{ 292 298 } }
}
T{ live-interval
- { vreg V int-regs 3687363 }
+ { vreg V int-rep 3687363 }
{ start 118 }
{ end 119 }
{ uses V{ 118 119 } }
}
T{ live-interval
- { vreg V int-regs 3686599 }
+ { vreg V int-rep 3686599 }
{ start 77 }
{ end 89 }
{ uses V{ 77 86 89 } }
}
T{ live-interval
- { vreg V int-regs 3687370 }
+ { vreg V int-rep 3687370 }
{ start 131 }
{ end 132 }
{ uses V{ 131 132 } }
}
T{ live-interval
- { vreg V int-regs 3687371 }
+ { vreg V int-rep 3687371 }
{ start 138 }
{ end 143 }
{ uses V{ 138 143 } }
}
T{ live-interval
- { vreg V int-regs 3687368 }
+ { vreg V int-rep 3687368 }
{ start 127 }
{ end 128 }
{ uses V{ 127 128 } }
}
T{ live-interval
- { vreg V int-regs 3687369 }
+ { vreg V int-rep 3687369 }
{ start 122 }
{ end 123 }
{ uses V{ 122 123 } }
}
T{ live-interval
- { vreg V int-regs 3687373 }
+ { vreg V int-rep 3687373 }
{ start 139 }
{ end 140 }
{ uses V{ 139 140 } }
}
T{ live-interval
- { vreg V int-regs 3686352 }
+ { vreg V int-rep 3686352 }
{ start 41 }
{ end 91 }
{ uses V{ 41 43 79 91 } }
}
T{ live-interval
- { vreg V int-regs 3687377 }
+ { vreg V int-rep 3687377 }
{ start 140 }
{ end 141 }
{ uses V{ 140 141 } }
}
T{ live-interval
- { vreg V int-regs 3687382 }
+ { vreg V int-rep 3687382 }
{ start 143 }
{ end 143 }
{ uses V{ 143 } }
}
T{ live-interval
- { vreg V int-regs 3687383 }
+ { vreg V int-rep 3687383 }
{ start 144 }
{ end 161 }
{ uses V{ 144 159 161 } }
}
T{ live-interval
- { vreg V int-regs 3687380 }
+ { vreg V int-rep 3687380 }
{ start 141 }
{ end 143 }
{ uses V{ 141 142 142 143 } }
}
T{ live-interval
- { vreg V int-regs 3687381 }
+ { vreg V int-rep 3687381 }
{ start 143 }
{ end 160 }
{ uses V{ 143 160 } }
}
T{ live-interval
- { vreg V int-regs 3687384 }
+ { vreg V int-rep 3687384 }
{ start 145 }
{ end 158 }
{ uses V{ 145 158 } }
}
T{ live-interval
- { vreg V int-regs 3687385 }
+ { vreg V int-rep 3687385 }
{ start 146 }
{ end 157 }
{ uses V{ 146 157 } }
}
T{ live-interval
- { vreg V int-regs 3687640 }
+ { vreg V int-rep 3687640 }
{ start 189 }
{ end 191 }
{ uses V{ 189 191 } }
}
T{ live-interval
- { vreg V int-regs 3687388 }
+ { vreg V int-rep 3687388 }
{ start 147 }
{ end 152 }
{ uses V{ 147 152 } }
}
T{ live-interval
- { vreg V int-regs 3687393 }
+ { vreg V int-rep 3687393 }
{ start 148 }
{ end 153 }
{ uses V{ 148 153 } }
}
T{ live-interval
- { vreg V int-regs 3687398 }
+ { vreg V int-rep 3687398 }
{ start 149 }
{ end 154 }
{ uses V{ 149 154 } }
}
T{ live-interval
- { vreg V int-regs 3686372 }
+ { vreg V int-rep 3686372 }
{ start 42 }
{ end 92 }
{ uses V{ 42 45 78 80 92 } }
}
T{ live-interval
- { vreg V int-regs 3687140 }
+ { vreg V int-rep 3687140 }
{ start 293 }
{ end 295 }
{ uses V{ 293 294 294 295 } }
}
T{ live-interval
- { vreg V int-regs 3687403 }
+ { vreg V int-rep 3687403 }
{ start 150 }
{ end 155 }
{ uses V{ 150 155 } }
}
T{ live-interval
- { vreg V int-regs 3687150 }
+ { vreg V int-rep 3687150 }
{ start 304 }
{ end 306 }
{ uses V{ 304 306 } }
}
T{ live-interval
- { vreg V int-regs 3687151 }
+ { vreg V int-rep 3687151 }
{ start 305 }
{ end 307 }
{ uses V{ 305 307 } }
}
T{ live-interval
- { vreg V int-regs 3687408 }
+ { vreg V int-rep 3687408 }
{ start 151 }
{ end 156 }
{ uses V{ 151 156 } }
}
T{ live-interval
- { vreg V int-regs 3687153 }
+ { vreg V int-rep 3687153 }
{ start 312 }
{ end 313 }
{ uses V{ 312 313 } }
}
T{ live-interval
- { vreg V int-regs 3686902 }
+ { vreg V int-rep 3686902 }
{ start 267 }
{ end 272 }
{ uses V{ 267 272 } }
}
T{ live-interval
- { vreg V int-regs 3686903 }
+ { vreg V int-rep 3686903 }
{ start 268 }
{ end 273 }
{ uses V{ 268 273 } }
}
T{ live-interval
- { vreg V int-regs 3686900 }
+ { vreg V int-rep 3686900 }
{ start 265 }
{ end 270 }
{ uses V{ 265 270 } }
}
T{ live-interval
- { vreg V int-regs 3686901 }
+ { vreg V int-rep 3686901 }
{ start 266 }
{ end 271 }
{ uses V{ 266 271 } }
}
T{ live-interval
- { vreg V int-regs 3687162 }
+ { vreg V int-rep 3687162 }
{ start 100 }
{ end 119 }
{ uses V{ 100 114 117 119 } }
}
T{ live-interval
- { vreg V int-regs 3687163 }
+ { vreg V int-rep 3687163 }
{ start 101 }
{ end 118 }
{ uses V{ 101 115 116 118 } }
}
T{ live-interval
- { vreg V int-regs 3686904 }
+ { vreg V int-rep 3686904 }
{ start 269 }
{ end 274 }
{ uses V{ 269 274 } }
}
T{ live-interval
- { vreg V int-regs 3687166 }
+ { vreg V int-rep 3687166 }
{ start 104 }
{ end 110 }
{ uses V{ 104 110 } }
}
T{ live-interval
- { vreg V int-regs 3687167 }
+ { vreg V int-rep 3687167 }
{ start 105 }
{ end 111 }
{ uses V{ 105 111 } }
}
T{ live-interval
- { vreg V int-regs 3687164 }
+ { vreg V int-rep 3687164 }
{ start 102 }
{ end 108 }
{ uses V{ 102 108 } }
}
T{ live-interval
- { vreg V int-regs 3687165 }
+ { vreg V int-rep 3687165 }
{ start 103 }
{ end 109 }
{ uses V{ 103 109 } }
[ ] [
{
T{ live-interval
- { vreg V int-regs 6449 }
+ { vreg V int-rep 6449 }
{ start 44 }
{ end 56 }
{ uses V{ 44 45 46 56 } }
}
T{ live-interval
- { vreg V int-regs 6454 }
+ { vreg V int-rep 6454 }
{ start 46 }
{ end 49 }
{ uses V{ 46 47 49 } }
}
T{ live-interval
- { vreg V int-regs 6455 }
+ { vreg V int-rep 6455 }
{ start 48 }
{ end 51 }
{ uses V{ 48 51 } }
}
T{ live-interval
- { vreg V int-regs 6460 }
+ { vreg V int-rep 6460 }
{ start 49 }
{ end 52 }
{ uses V{ 49 50 52 } }
}
T{ live-interval
- { vreg V int-regs 6461 }
+ { vreg V int-rep 6461 }
{ start 51 }
{ end 71 }
{ uses V{ 51 52 64 68 71 } }
}
T{ live-interval
- { vreg V int-regs 6464 }
+ { vreg V int-rep 6464 }
{ start 53 }
{ end 54 }
{ uses V{ 53 54 } }
}
T{ live-interval
- { vreg V int-regs 6470 }
+ { vreg V int-rep 6470 }
{ start 58 }
{ end 60 }
{ uses V{ 58 59 60 } }
}
T{ live-interval
- { vreg V int-regs 6469 }
+ { vreg V int-rep 6469 }
{ start 56 }
{ end 58 }
{ uses V{ 56 57 58 } }
}
T{ live-interval
- { vreg V int-regs 6473 }
+ { vreg V int-rep 6473 }
{ start 60 }
{ end 62 }
{ uses V{ 60 61 62 } }
}
T{ live-interval
- { vreg V int-regs 6479 }
+ { vreg V int-rep 6479 }
{ start 62 }
{ end 64 }
{ uses V{ 62 63 64 } }
}
T{ live-interval
- { vreg V int-regs 6735 }
+ { vreg V int-rep 6735 }
{ start 78 }
{ end 96 }
{ uses V{ 78 79 96 } }
}
T{ live-interval
- { vreg V int-regs 6483 }
+ { vreg V int-rep 6483 }
{ start 65 }
{ end 66 }
{ uses V{ 65 66 } }
}
T{ live-interval
- { vreg V int-regs 7845 }
+ { vreg V int-rep 7845 }
{ start 91 }
{ end 93 }
{ uses V{ 91 93 } }
}
T{ live-interval
- { vreg V int-regs 6372 }
+ { vreg V int-rep 6372 }
{ start 42 }
{ end 92 }
{ uses V{ 42 45 78 80 92 } }
{ int-regs
{
T{ live-interval
- { vreg V int-regs 1 }
+ { vreg V int-rep 1 }
{ start 0 }
{ end 20 }
{ reg 0 }
}
T{ live-interval
- { vreg V int-regs 2 }
+ { vreg V int-rep 2 }
{ start 4 }
{ end 40 }
{ reg 0 }
{ int-regs
{
T{ live-interval
- { vreg V int-regs 3 }
+ { vreg V int-rep 3 }
{ start 0 }
{ end 40 }
{ reg 1 }
} active-intervals set
T{ live-interval
- { vreg V int-regs 4 }
+ { vreg V int-rep 4 }
{ start 8 }
{ end 10 }
{ ranges V{ T{ live-range f 8 10 } } }
V{
T{ ##peek
- { dst V int-regs 703128 }
+ { dst V int-rep 703128 }
{ loc D 1 }
}
T{ ##peek
- { dst V int-regs 703129 }
+ { dst V int-rep 703129 }
{ loc D 0 }
}
T{ ##copy
- { dst V int-regs 703134 }
- { src V int-regs 703128 }
+ { dst V int-rep 703134 }
+ { src V int-rep 703128 }
}
T{ ##copy
- { dst V int-regs 703135 }
- { src V int-regs 703129 }
+ { dst V int-rep 703135 }
+ { src V int-rep 703129 }
}
T{ ##compare-imm-branch
- { src1 V int-regs 703128 }
+ { src1 V int-rep 703128 }
{ src2 5 }
{ cc cc/= }
}
V{
T{ ##copy
- { dst V int-regs 703134 }
- { src V int-regs 703129 }
+ { dst V int-rep 703134 }
+ { src V int-rep 703129 }
}
T{ ##copy
- { dst V int-regs 703135 }
- { src V int-regs 703128 }
+ { dst V int-rep 703135 }
+ { src V int-rep 703128 }
}
T{ ##branch }
} 2 test-bb
V{
T{ ##replace
- { src V int-regs 703134 }
+ { src V int-rep 703134 }
{ loc D 0 }
}
T{ ##replace
- { src V int-regs 703135 }
+ { src V int-rep 703135 }
{ loc D 1 }
}
T{ ##epilogue }
V{
T{ ##peek
- { dst V int-regs 689473 }
+ { dst V int-rep 689473 }
{ loc D 2 }
}
T{ ##peek
- { dst V int-regs 689474 }
+ { dst V int-rep 689474 }
{ loc D 1 }
}
T{ ##peek
- { dst V int-regs 689475 }
+ { dst V int-rep 689475 }
{ loc D 0 }
}
T{ ##compare-imm-branch
- { src1 V int-regs 689473 }
+ { src1 V int-rep 689473 }
{ src2 5 }
{ cc cc/= }
}
V{
T{ ##copy
- { dst V int-regs 689481 }
- { src V int-regs 689475 }
+ { dst V int-rep 689481 }
+ { src V int-rep 689475 }
}
T{ ##copy
- { dst V int-regs 689482 }
- { src V int-regs 689474 }
+ { dst V int-rep 689482 }
+ { src V int-rep 689474 }
}
T{ ##copy
- { dst V int-regs 689483 }
- { src V int-regs 689473 }
+ { dst V int-rep 689483 }
+ { src V int-rep 689473 }
}
T{ ##branch }
} 2 test-bb
V{
T{ ##copy
- { dst V int-regs 689481 }
- { src V int-regs 689473 }
+ { dst V int-rep 689481 }
+ { src V int-rep 689473 }
}
T{ ##copy
- { dst V int-regs 689482 }
- { src V int-regs 689475 }
+ { dst V int-rep 689482 }
+ { src V int-rep 689475 }
}
T{ ##copy
- { dst V int-regs 689483 }
- { src V int-regs 689474 }
+ { dst V int-rep 689483 }
+ { src V int-rep 689474 }
}
T{ ##branch }
} 3 test-bb
V{
T{ ##replace
- { src V int-regs 689481 }
+ { src V int-rep 689481 }
{ loc D 0 }
}
T{ ##replace
- { src V int-regs 689482 }
+ { src V int-rep 689482 }
{ loc D 1 }
}
T{ ##replace
- { src V int-regs 689483 }
+ { src V int-rep 689483 }
{ loc D 2 }
}
T{ ##epilogue }
V{
T{ ##peek
- { dst V int-regs 689600 }
+ { dst V int-rep 689600 }
{ loc D 1 }
}
T{ ##peek
- { dst V int-regs 689601 }
+ { dst V int-rep 689601 }
{ loc D 0 }
}
T{ ##compare-imm-branch
- { src1 V int-regs 689600 }
+ { src1 V int-rep 689600 }
{ src2 5 }
{ cc cc/= }
}
V{
T{ ##peek
- { dst V int-regs 689604 }
+ { dst V int-rep 689604 }
{ loc D 2 }
}
T{ ##copy
- { dst V int-regs 689607 }
- { src V int-regs 689604 }
+ { dst V int-rep 689607 }
+ { src V int-rep 689604 }
}
T{ ##copy
- { dst V int-regs 689608 }
- { src V int-regs 689600 }
+ { dst V int-rep 689608 }
+ { src V int-rep 689600 }
}
T{ ##copy
- { dst V int-regs 689610 }
- { src V int-regs 689601 }
+ { dst V int-rep 689610 }
+ { src V int-rep 689601 }
}
T{ ##branch }
} 2 test-bb
V{
T{ ##peek
- { dst V int-regs 689609 }
+ { dst V int-rep 689609 }
{ loc D 2 }
}
T{ ##copy
- { dst V int-regs 689607 }
- { src V int-regs 689600 }
+ { dst V int-rep 689607 }
+ { src V int-rep 689600 }
}
T{ ##copy
- { dst V int-regs 689608 }
- { src V int-regs 689601 }
+ { dst V int-rep 689608 }
+ { src V int-rep 689601 }
}
T{ ##copy
- { dst V int-regs 689610 }
- { src V int-regs 689609 }
+ { dst V int-rep 689610 }
+ { src V int-rep 689609 }
}
T{ ##branch }
} 3 test-bb
V{
T{ ##replace
- { src V int-regs 689607 }
+ { src V int-rep 689607 }
{ loc D 0 }
}
T{ ##replace
- { src V int-regs 689608 }
+ { src V int-rep 689608 }
{ loc D 1 }
}
T{ ##replace
- { src V int-regs 689610 }
+ { src V int-rep 689610 }
{ loc D 2 }
}
T{ ##epilogue }
V{
T{ ##peek
- { dst V int-regs 0 }
+ { dst V int-rep 0 }
{ loc D 0 }
}
T{ ##compare-imm-branch
- { src1 V int-regs 0 }
+ { src1 V int-rep 0 }
{ src2 5 }
{ cc cc/= }
}
V{
T{ ##peek
- { dst V int-regs 1 }
+ { dst V int-rep 1 }
{ loc D 1 }
}
T{ ##copy
- { dst V int-regs 2 }
- { src V int-regs 1 }
+ { dst V int-rep 2 }
+ { src V int-rep 1 }
}
T{ ##branch }
} 2 test-bb
V{
T{ ##peek
- { dst V int-regs 3 }
+ { dst V int-rep 3 }
{ loc D 2 }
}
T{ ##copy
- { dst V int-regs 2 }
- { src V int-regs 3 }
+ { dst V int-rep 2 }
+ { src V int-rep 3 }
}
T{ ##branch }
} 3 test-bb
V{
T{ ##replace
- { src V int-regs 2 }
+ { src V int-rep 2 }
{ loc D 0 }
}
T{ ##return }
! Inactive interval handling: splitting active interval
! if it fits in lifetime hole only partially
-V{ T{ ##peek f V int-regs 3 R 1 } T{ ##branch } } 0 test-bb
+V{ T{ ##peek f V int-rep 3 R 1 } T{ ##branch } } 0 test-bb
V{
- T{ ##peek f V int-regs 2 R 0 }
- T{ ##compare-imm-branch f V int-regs 2 5 cc= }
+ T{ ##peek f V int-rep 2 R 0 }
+ T{ ##compare-imm-branch f V int-rep 2 5 cc= }
} 1 test-bb
V{
- T{ ##peek f V int-regs 0 D 0 }
+ T{ ##peek f V int-rep 0 D 0 }
T{ ##branch }
} 2 test-bb
V{
- T{ ##peek f V int-regs 1 D 1 }
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##replace f V int-regs 1 D 2 }
+ T{ ##peek f V int-rep 1 D 1 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##replace f V int-rep 1 D 2 }
T{ ##branch }
} 3 test-bb
V{
- T{ ##replace f V int-regs 3 R 2 }
- T{ ##replace f V int-regs 0 D 0 }
+ T{ ##replace f V int-rep 3 R 2 }
+ T{ ##replace f V int-rep 0 D 0 }
T{ ##return }
} 4 test-bb
! [ _copy ] [ 3 get instructions>> second class ] unit-test
! Resolve pass; make sure the spilling is done correctly
-V{ T{ ##peek f V int-regs 3 R 1 } T{ ##branch } } 0 test-bb
+V{ T{ ##peek f V int-rep 3 R 1 } T{ ##branch } } 0 test-bb
V{
- T{ ##peek f V int-regs 2 R 0 }
- T{ ##compare-imm-branch f V int-regs 2 5 cc= }
+ T{ ##peek f V int-rep 2 R 0 }
+ T{ ##compare-imm-branch f V int-rep 2 5 cc= }
} 1 test-bb
V{
} 2 test-bb
V{
- T{ ##replace f V int-regs 3 R 1 }
- T{ ##peek f V int-regs 1 D 1 }
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##replace f V int-regs 1 D 2 }
- T{ ##replace f V int-regs 0 D 2 }
+ T{ ##replace f V int-rep 3 R 1 }
+ T{ ##peek f V int-rep 1 D 1 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##replace f V int-rep 1 D 2 }
+ T{ ##replace f V int-rep 0 D 2 }
T{ ##branch }
} 3 test-bb
V{
- T{ ##replace f V int-regs 3 R 2 }
+ T{ ##replace f V int-rep 3 R 2 }
T{ ##return }
} 4 test-bb
} 0 test-bb
V{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##compare-imm-branch f V int-regs 0 5 cc= }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##compare-imm-branch f V int-rep 0 5 cc= }
} 1 test-bb
V{
- T{ ##replace f V int-regs 0 D 0 }
- T{ ##peek f V int-regs 1 D 0 }
- T{ ##peek f V int-regs 2 D 0 }
- T{ ##replace f V int-regs 1 D 0 }
- T{ ##replace f V int-regs 2 D 0 }
+ T{ ##replace f V int-rep 0 D 0 }
+ T{ ##peek f V int-rep 1 D 0 }
+ T{ ##peek f V int-rep 2 D 0 }
+ T{ ##replace f V int-rep 1 D 0 }
+ T{ ##replace f V int-rep 2 D 0 }
T{ ##branch }
} 2 test-bb
} 3 test-bb
V{
- T{ ##peek f V int-regs 1 D 0 }
- T{ ##compare-imm-branch f V int-regs 1 5 cc= }
+ T{ ##peek f V int-rep 1 D 0 }
+ T{ ##compare-imm-branch f V int-rep 1 5 cc= }
} 4 test-bb
V{
- T{ ##replace f V int-regs 0 D 0 }
+ T{ ##replace f V int-rep 0 D 0 }
T{ ##return }
} 5 test-bb
V{
- T{ ##replace f V int-regs 0 D 0 }
+ T{ ##replace f V int-rep 0 D 0 }
T{ ##return }
} 6 test-bb
! got fixed
V{ T{ ##branch } } 0 test-bb
V{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##peek f V int-regs 1 D 1 }
- T{ ##peek f V int-regs 2 D 2 }
- T{ ##peek f V int-regs 3 D 3 }
- T{ ##peek f V int-regs 4 D 0 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##peek f V int-rep 1 D 1 }
+ T{ ##peek f V int-rep 2 D 2 }
+ T{ ##peek f V int-rep 3 D 3 }
+ T{ ##peek f V int-rep 4 D 0 }
T{ ##branch }
} 1 test-bb
V{ T{ ##branch } } 2 test-bb
V{ T{ ##branch } } 3 test-bb
V{
- T{ ##replace f V int-regs 1 D 1 }
- T{ ##replace f V int-regs 2 D 2 }
- T{ ##replace f V int-regs 3 D 3 }
- T{ ##replace f V int-regs 4 D 4 }
- T{ ##replace f V int-regs 0 D 0 }
+ T{ ##replace f V int-rep 1 D 1 }
+ T{ ##replace f V int-rep 2 D 2 }
+ T{ ##replace f V int-rep 3 D 3 }
+ T{ ##replace f V int-rep 4 D 4 }
+ T{ ##replace f V int-rep 0 D 0 }
T{ ##branch }
} 4 test-bb
-V{ T{ ##replace f V int-regs 0 D 0 } T{ ##branch } } 5 test-bb
+V{ T{ ##replace f V int-rep 0 D 0 } T{ ##branch } } 5 test-bb
V{ T{ ##return } } 6 test-bb
V{ T{ ##branch } } 7 test-bb
V{
- T{ ##replace f V int-regs 1 D 1 }
- T{ ##replace f V int-regs 2 D 2 }
- T{ ##replace f V int-regs 3 D 3 }
- T{ ##peek f V int-regs 5 D 1 }
- T{ ##peek f V int-regs 6 D 2 }
- T{ ##peek f V int-regs 7 D 3 }
- T{ ##peek f V int-regs 8 D 4 }
- T{ ##replace f V int-regs 5 D 1 }
- T{ ##replace f V int-regs 6 D 2 }
- T{ ##replace f V int-regs 7 D 3 }
- T{ ##replace f V int-regs 8 D 4 }
+ T{ ##replace f V int-rep 1 D 1 }
+ T{ ##replace f V int-rep 2 D 2 }
+ T{ ##replace f V int-rep 3 D 3 }
+ T{ ##peek f V int-rep 5 D 1 }
+ T{ ##peek f V int-rep 6 D 2 }
+ T{ ##peek f V int-rep 7 D 3 }
+ T{ ##peek f V int-rep 8 D 4 }
+ T{ ##replace f V int-rep 5 D 1 }
+ T{ ##replace f V int-rep 6 D 2 }
+ T{ ##replace f V int-rep 7 D 3 }
+ T{ ##replace f V int-rep 8 D 4 }
T{ ##branch }
} 8 test-bb
V{
- T{ ##replace f V int-regs 1 D 1 }
- T{ ##replace f V int-regs 2 D 2 }
- T{ ##replace f V int-regs 3 D 3 }
+ T{ ##replace f V int-rep 1 D 1 }
+ T{ ##replace f V int-rep 2 D 2 }
+ T{ ##replace f V int-rep 3 D 3 }
T{ ##return }
} 9 test-bb
[ _spill ] [ 1 get instructions>> second class ] unit-test
[ _reload ] [ 4 get instructions>> 4 swap nth class ] unit-test
-[ V{ 3 2 1 } ] [ 8 get instructions>> [ _spill? ] filter [ n>> ] map ] unit-test
-[ V{ 3 2 1 } ] [ 9 get instructions>> [ _reload? ] filter [ n>> ] map ] unit-test
+[ V{ 3 2 1 } ] [ 8 get instructions>> [ _spill? ] filter [ n>> cell / ] map ] unit-test
+[ V{ 3 2 1 } ] [ 9 get instructions>> [ _reload? ] filter [ n>> cell / ] map ] unit-test
! Resolve pass should insert this
[ _reload ] [ 5 get predecessors>> first instructions>> first class ] unit-test
! Some random bug
V{
- T{ ##peek f V int-regs 1 D 1 }
- T{ ##peek f V int-regs 2 D 2 }
- T{ ##replace f V int-regs 1 D 1 }
- T{ ##replace f V int-regs 2 D 2 }
- T{ ##peek f V int-regs 3 D 0 }
- T{ ##peek f V int-regs 0 D 0 }
+ T{ ##peek f V int-rep 1 D 1 }
+ T{ ##peek f V int-rep 2 D 2 }
+ T{ ##replace f V int-rep 1 D 1 }
+ T{ ##replace f V int-rep 2 D 2 }
+ T{ ##peek f V int-rep 3 D 0 }
+ T{ ##peek f V int-rep 0 D 0 }
T{ ##branch }
} 0 test-bb
V{ T{ ##branch } } 1 test-bb
V{
- T{ ##peek f V int-regs 1 D 1 }
- T{ ##peek f V int-regs 2 D 2 }
- T{ ##replace f V int-regs 3 D 3 }
- T{ ##replace f V int-regs 1 D 1 }
- T{ ##replace f V int-regs 2 D 2 }
- T{ ##replace f V int-regs 0 D 3 }
+ T{ ##peek f V int-rep 1 D 1 }
+ T{ ##peek f V int-rep 2 D 2 }
+ T{ ##replace f V int-rep 3 D 3 }
+ T{ ##replace f V int-rep 1 D 1 }
+ T{ ##replace f V int-rep 2 D 2 }
+ T{ ##replace f V int-rep 0 D 3 }
T{ ##branch }
} 2 test-bb
! Spilling an interval immediately after its activated;
! and the interval does not have a use at the activation point
V{
- T{ ##peek f V int-regs 1 D 1 }
- T{ ##peek f V int-regs 2 D 2 }
- T{ ##replace f V int-regs 1 D 1 }
- T{ ##replace f V int-regs 2 D 2 }
- T{ ##peek f V int-regs 0 D 0 }
+ T{ ##peek f V int-rep 1 D 1 }
+ T{ ##peek f V int-rep 2 D 2 }
+ T{ ##replace f V int-rep 1 D 1 }
+ T{ ##replace f V int-rep 2 D 2 }
+ T{ ##peek f V int-rep 0 D 0 }
T{ ##branch }
} 0 test-bb
V{ T{ ##branch } } 1 test-bb
V{
- T{ ##peek f V int-regs 1 D 1 }
+ T{ ##peek f V int-rep 1 D 1 }
T{ ##branch }
} 2 test-bb
V{
- T{ ##replace f V int-regs 1 D 1 }
- T{ ##peek f V int-regs 2 D 2 }
- T{ ##replace f V int-regs 2 D 2 }
+ T{ ##replace f V int-rep 1 D 1 }
+ T{ ##peek f V int-rep 2 D 2 }
+ T{ ##replace f V int-rep 2 D 2 }
T{ ##branch }
} 3 test-bb
V{ T{ ##branch } } 4 test-bb
V{
- T{ ##replace f V int-regs 0 D 0 }
+ T{ ##replace f V int-rep 0 D 0 }
T{ ##return }
} 5 test-bb
V{ T{ ##prologue } T{ ##branch } } 0 test-bb
V{
- T{ ##load-immediate { dst V int-regs 61 } }
- T{ ##peek { dst V int-regs 62 } { loc D 0 } }
- T{ ##peek { dst V int-regs 64 } { loc D 1 } }
+ T{ ##load-immediate { dst V int-rep 61 } }
+ T{ ##peek { dst V int-rep 62 } { loc D 0 } }
+ T{ ##peek { dst V int-rep 64 } { loc D 1 } }
T{ ##slot-imm
- { dst V int-regs 69 }
- { obj V int-regs 64 }
+ { dst V int-rep 69 }
+ { obj V int-rep 64 }
{ slot 1 }
{ tag 2 }
}
- T{ ##copy { dst V int-regs 79 } { src V int-regs 69 } }
+ T{ ##copy { dst V int-rep 79 } { src V int-rep 69 } }
T{ ##slot-imm
- { dst V int-regs 85 }
- { obj V int-regs 62 }
+ { dst V int-rep 85 }
+ { obj V int-rep 62 }
{ slot 2 }
{ tag 7 }
}
T{ ##compare-branch
- { src1 V int-regs 69 }
- { src2 V int-regs 85 }
+ { src1 V int-rep 69 }
+ { src2 V int-rep 85 }
{ cc cc> }
}
} 1 test-bb
V{
T{ ##slot-imm
- { dst V int-regs 97 }
- { obj V int-regs 62 }
+ { dst V int-rep 97 }
+ { obj V int-rep 62 }
{ slot 2 }
{ tag 7 }
}
- T{ ##replace { src V int-regs 79 } { loc D 3 } }
- T{ ##replace { src V int-regs 62 } { loc D 4 } }
- T{ ##replace { src V int-regs 79 } { loc D 1 } }
- T{ ##replace { src V int-regs 62 } { loc D 2 } }
- T{ ##replace { src V int-regs 61 } { loc D 5 } }
- T{ ##replace { src V int-regs 62 } { loc R 0 } }
- T{ ##replace { src V int-regs 69 } { loc R 1 } }
- T{ ##replace { src V int-regs 97 } { loc D 0 } }
+ T{ ##replace { src V int-rep 79 } { loc D 3 } }
+ T{ ##replace { src V int-rep 62 } { loc D 4 } }
+ T{ ##replace { src V int-rep 79 } { loc D 1 } }
+ T{ ##replace { src V int-rep 62 } { loc D 2 } }
+ T{ ##replace { src V int-rep 61 } { loc D 5 } }
+ T{ ##replace { src V int-rep 62 } { loc R 0 } }
+ T{ ##replace { src V int-rep 69 } { loc R 1 } }
+ T{ ##replace { src V int-rep 97 } { loc D 0 } }
T{ ##call { word resize-array } }
T{ ##branch }
} 2 test-bb
V{
- T{ ##peek { dst V int-regs 98 } { loc R 0 } }
- T{ ##peek { dst V int-regs 100 } { loc D 0 } }
+ T{ ##peek { dst V int-rep 98 } { loc R 0 } }
+ T{ ##peek { dst V int-rep 100 } { loc D 0 } }
T{ ##set-slot-imm
- { src V int-regs 100 }
- { obj V int-regs 98 }
+ { src V int-rep 100 }
+ { obj V int-rep 98 }
{ slot 2 }
{ tag 7 }
}
- T{ ##peek { dst V int-regs 108 } { loc D 2 } }
- T{ ##peek { dst V int-regs 110 } { loc D 3 } }
- T{ ##peek { dst V int-regs 112 } { loc D 0 } }
- T{ ##peek { dst V int-regs 114 } { loc D 1 } }
- T{ ##peek { dst V int-regs 116 } { loc D 4 } }
- T{ ##peek { dst V int-regs 119 } { loc R 0 } }
- T{ ##copy { dst V int-regs 109 } { src V int-regs 108 } }
- T{ ##copy { dst V int-regs 111 } { src V int-regs 110 } }
- T{ ##copy { dst V int-regs 113 } { src V int-regs 112 } }
- T{ ##copy { dst V int-regs 115 } { src V int-regs 114 } }
- T{ ##copy { dst V int-regs 117 } { src V int-regs 116 } }
- T{ ##copy { dst V int-regs 120 } { src V int-regs 119 } }
+ T{ ##peek { dst V int-rep 108 } { loc D 2 } }
+ T{ ##peek { dst V int-rep 110 } { loc D 3 } }
+ T{ ##peek { dst V int-rep 112 } { loc D 0 } }
+ T{ ##peek { dst V int-rep 114 } { loc D 1 } }
+ T{ ##peek { dst V int-rep 116 } { loc D 4 } }
+ T{ ##peek { dst V int-rep 119 } { loc R 0 } }
+ T{ ##copy { dst V int-rep 109 } { src V int-rep 108 } }
+ T{ ##copy { dst V int-rep 111 } { src V int-rep 110 } }
+ T{ ##copy { dst V int-rep 113 } { src V int-rep 112 } }
+ T{ ##copy { dst V int-rep 115 } { src V int-rep 114 } }
+ T{ ##copy { dst V int-rep 117 } { src V int-rep 116 } }
+ T{ ##copy { dst V int-rep 120 } { src V int-rep 119 } }
T{ ##branch }
} 3 test-bb
V{
- T{ ##copy { dst V int-regs 109 } { src V int-regs 62 } }
- T{ ##copy { dst V int-regs 111 } { src V int-regs 61 } }
- T{ ##copy { dst V int-regs 113 } { src V int-regs 62 } }
- T{ ##copy { dst V int-regs 115 } { src V int-regs 79 } }
- T{ ##copy { dst V int-regs 117 } { src V int-regs 64 } }
- T{ ##copy { dst V int-regs 120 } { src V int-regs 69 } }
+ T{ ##copy { dst V int-rep 109 } { src V int-rep 62 } }
+ T{ ##copy { dst V int-rep 111 } { src V int-rep 61 } }
+ T{ ##copy { dst V int-rep 113 } { src V int-rep 62 } }
+ T{ ##copy { dst V int-rep 115 } { src V int-rep 79 } }
+ T{ ##copy { dst V int-rep 117 } { src V int-rep 64 } }
+ T{ ##copy { dst V int-rep 120 } { src V int-rep 69 } }
T{ ##branch }
} 4 test-bb
V{
- T{ ##replace { src V int-regs 120 } { loc D 0 } }
- T{ ##replace { src V int-regs 109 } { loc D 3 } }
- T{ ##replace { src V int-regs 111 } { loc D 4 } }
- T{ ##replace { src V int-regs 113 } { loc D 1 } }
- T{ ##replace { src V int-regs 115 } { loc D 2 } }
- T{ ##replace { src V int-regs 117 } { loc D 5 } }
+ T{ ##replace { src V int-rep 120 } { loc D 0 } }
+ T{ ##replace { src V int-rep 109 } { loc D 3 } }
+ T{ ##replace { src V int-rep 111 } { loc D 4 } }
+ T{ ##replace { src V int-rep 113 } { loc D 1 } }
+ T{ ##replace { src V int-rep 115 } { loc D 2 } }
+ T{ ##replace { src V int-rep 117 } { loc D 5 } }
T{ ##epilogue }
T{ ##return }
} 5 test-bb
V{ T{ ##prologue } T{ ##branch } } 0 test-bb
V{
- T{ ##peek { dst V int-regs 85 } { loc D 0 } }
+ T{ ##peek { dst V int-rep 85 } { loc D 0 } }
T{ ##slot-imm
- { dst V int-regs 89 }
- { obj V int-regs 85 }
+ { dst V int-rep 89 }
+ { obj V int-rep 85 }
{ slot 3 }
{ tag 7 }
}
- T{ ##peek { dst V int-regs 91 } { loc D 1 } }
+ T{ ##peek { dst V int-rep 91 } { loc D 1 } }
T{ ##slot-imm
- { dst V int-regs 96 }
- { obj V int-regs 91 }
+ { dst V int-rep 96 }
+ { obj V int-rep 91 }
{ slot 1 }
{ tag 2 }
}
T{ ##add
- { dst V int-regs 109 }
- { src1 V int-regs 89 }
- { src2 V int-regs 96 }
+ { dst V int-rep 109 }
+ { src1 V int-rep 89 }
+ { src2 V int-rep 96 }
}
T{ ##slot-imm
- { dst V int-regs 115 }
- { obj V int-regs 85 }
+ { dst V int-rep 115 }
+ { obj V int-rep 85 }
{ slot 2 }
{ tag 7 }
}
T{ ##slot-imm
- { dst V int-regs 118 }
- { obj V int-regs 115 }
+ { dst V int-rep 118 }
+ { obj V int-rep 115 }
{ slot 1 }
{ tag 2 }
}
T{ ##compare-branch
- { src1 V int-regs 109 }
- { src2 V int-regs 118 }
+ { src1 V int-rep 109 }
+ { src2 V int-rep 118 }
{ cc cc> }
}
} 1 test-bb
V{
T{ ##add-imm
- { dst V int-regs 128 }
- { src1 V int-regs 109 }
+ { dst V int-rep 128 }
+ { src1 V int-rep 109 }
{ src2 8 }
}
- T{ ##load-immediate { dst V int-regs 129 } { val 24 } }
+ T{ ##load-immediate { dst V int-rep 129 } { val 24 } }
T{ ##inc-d { n 4 } }
T{ ##inc-r { n 1 } }
- T{ ##replace { src V int-regs 109 } { loc D 2 } }
- T{ ##replace { src V int-regs 85 } { loc D 3 } }
- T{ ##replace { src V int-regs 128 } { loc D 0 } }
- T{ ##replace { src V int-regs 85 } { loc D 1 } }
- T{ ##replace { src V int-regs 89 } { loc D 4 } }
- T{ ##replace { src V int-regs 96 } { loc R 0 } }
- T{ ##replace { src V int-regs 129 } { loc R 0 } }
+ T{ ##replace { src V int-rep 109 } { loc D 2 } }
+ T{ ##replace { src V int-rep 85 } { loc D 3 } }
+ T{ ##replace { src V int-rep 128 } { loc D 0 } }
+ T{ ##replace { src V int-rep 85 } { loc D 1 } }
+ T{ ##replace { src V int-rep 89 } { loc D 4 } }
+ T{ ##replace { src V int-rep 96 } { loc R 0 } }
+ T{ ##replace { src V int-rep 129 } { loc R 0 } }
T{ ##branch }
} 2 test-bb
V{
- T{ ##peek { dst V int-regs 134 } { loc D 1 } }
+ T{ ##peek { dst V int-rep 134 } { loc D 1 } }
T{ ##slot-imm
- { dst V int-regs 140 }
- { obj V int-regs 134 }
+ { dst V int-rep 140 }
+ { obj V int-rep 134 }
{ slot 2 }
{ tag 7 }
}
T{ ##inc-d { n 1 } }
T{ ##inc-r { n 1 } }
- T{ ##replace { src V int-regs 140 } { loc D 0 } }
- T{ ##replace { src V int-regs 134 } { loc R 0 } }
+ T{ ##replace { src V int-rep 140 } { loc D 0 } }
+ T{ ##replace { src V int-rep 134 } { loc R 0 } }
T{ ##call { word resize-array } }
T{ ##branch }
} 3 test-bb
V{
- T{ ##peek { dst V int-regs 141 } { loc R 0 } }
- T{ ##peek { dst V int-regs 143 } { loc D 0 } }
+ T{ ##peek { dst V int-rep 141 } { loc R 0 } }
+ T{ ##peek { dst V int-rep 143 } { loc D 0 } }
T{ ##set-slot-imm
- { src V int-regs 143 }
- { obj V int-regs 141 }
+ { src V int-rep 143 }
+ { obj V int-rep 141 }
{ slot 2 }
{ tag 7 }
}
T{ ##write-barrier
- { src V int-regs 141 }
- { card# V int-regs 145 }
- { table V int-regs 146 }
+ { src V int-rep 141 }
+ { card# V int-rep 145 }
+ { table V int-rep 146 }
}
T{ ##inc-d { n -1 } }
T{ ##inc-r { n -1 } }
- T{ ##peek { dst V int-regs 156 } { loc D 2 } }
- T{ ##peek { dst V int-regs 158 } { loc D 3 } }
- T{ ##peek { dst V int-regs 160 } { loc D 0 } }
- T{ ##peek { dst V int-regs 162 } { loc D 1 } }
- T{ ##peek { dst V int-regs 164 } { loc D 4 } }
- T{ ##peek { dst V int-regs 167 } { loc R 0 } }
- T{ ##copy { dst V int-regs 157 } { src V int-regs 156 } }
- T{ ##copy { dst V int-regs 159 } { src V int-regs 158 } }
- T{ ##copy { dst V int-regs 161 } { src V int-regs 160 } }
- T{ ##copy { dst V int-regs 163 } { src V int-regs 162 } }
- T{ ##copy { dst V int-regs 165 } { src V int-regs 164 } }
- T{ ##copy { dst V int-regs 168 } { src V int-regs 167 } }
+ T{ ##peek { dst V int-rep 156 } { loc D 2 } }
+ T{ ##peek { dst V int-rep 158 } { loc D 3 } }
+ T{ ##peek { dst V int-rep 160 } { loc D 0 } }
+ T{ ##peek { dst V int-rep 162 } { loc D 1 } }
+ T{ ##peek { dst V int-rep 164 } { loc D 4 } }
+ T{ ##peek { dst V int-rep 167 } { loc R 0 } }
+ T{ ##copy { dst V int-rep 157 } { src V int-rep 156 } }
+ T{ ##copy { dst V int-rep 159 } { src V int-rep 158 } }
+ T{ ##copy { dst V int-rep 161 } { src V int-rep 160 } }
+ T{ ##copy { dst V int-rep 163 } { src V int-rep 162 } }
+ T{ ##copy { dst V int-rep 165 } { src V int-rep 164 } }
+ T{ ##copy { dst V int-rep 168 } { src V int-rep 167 } }
T{ ##branch }
} 4 test-bb
V{
T{ ##inc-d { n 3 } }
T{ ##inc-r { n 1 } }
- T{ ##copy { dst V int-regs 157 } { src V int-regs 85 } }
- T{ ##copy { dst V int-regs 159 } { src V int-regs 89 } }
- T{ ##copy { dst V int-regs 161 } { src V int-regs 85 } }
- T{ ##copy { dst V int-regs 163 } { src V int-regs 109 } }
- T{ ##copy { dst V int-regs 165 } { src V int-regs 91 } }
- T{ ##copy { dst V int-regs 168 } { src V int-regs 96 } }
+ T{ ##copy { dst V int-rep 157 } { src V int-rep 85 } }
+ T{ ##copy { dst V int-rep 159 } { src V int-rep 89 } }
+ T{ ##copy { dst V int-rep 161 } { src V int-rep 85 } }
+ T{ ##copy { dst V int-rep 163 } { src V int-rep 109 } }
+ T{ ##copy { dst V int-rep 165 } { src V int-rep 91 } }
+ T{ ##copy { dst V int-rep 168 } { src V int-rep 96 } }
T{ ##branch }
} 5 test-bb
V{
T{ ##set-slot-imm
- { src V int-regs 163 }
- { obj V int-regs 161 }
+ { src V int-rep 163 }
+ { obj V int-rep 161 }
{ slot 3 }
{ tag 7 }
}
T{ ##inc-d { n 1 } }
T{ ##inc-r { n -1 } }
- T{ ##replace { src V int-regs 168 } { loc D 0 } }
- T{ ##replace { src V int-regs 157 } { loc D 3 } }
- T{ ##replace { src V int-regs 159 } { loc D 4 } }
- T{ ##replace { src V int-regs 161 } { loc D 1 } }
- T{ ##replace { src V int-regs 163 } { loc D 2 } }
- T{ ##replace { src V int-regs 165 } { loc D 5 } }
+ T{ ##replace { src V int-rep 168 } { loc D 0 } }
+ T{ ##replace { src V int-rep 157 } { loc D 3 } }
+ T{ ##replace { src V int-rep 159 } { loc D 4 } }
+ T{ ##replace { src V int-rep 161 } { loc D 1 } }
+ T{ ##replace { src V int-rep 163 } { loc D 2 } }
+ T{ ##replace { src V int-rep 165 } { loc D 5 } }
T{ ##epilogue }
T{ ##return }
} 6 test-bb
V{ T{ ##branch } } 0 test-bb
V{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##compare-imm-branch f V int-regs 0 5 cc= }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##compare-imm-branch f V int-rep 0 5 cc= }
} 1 test-bb
V{ T{ ##branch } } 2 test-bb
V{
- T{ ##peek f V int-regs 1 D 0 }
- T{ ##peek f V int-regs 2 D 0 }
- T{ ##replace f V int-regs 1 D 0 }
- T{ ##replace f V int-regs 2 D 0 }
+ T{ ##peek f V int-rep 1 D 0 }
+ T{ ##peek f V int-rep 2 D 0 }
+ T{ ##replace f V int-rep 1 D 0 }
+ T{ ##replace f V int-rep 2 D 0 }
T{ ##branch }
} 3 test-bb
V{
- T{ ##replace f V int-regs 0 D 0 }
+ T{ ##replace f V int-rep 0 D 0 }
T{ ##return }
} 4 test-bb
V{ T{ ##branch } } 0 test-bb
V{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##compare-imm-branch f V int-regs 0 5 cc= }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##compare-imm-branch f V int-rep 0 5 cc= }
} 1 test-bb
V{
- T{ ##peek f V int-regs 1 D 0 }
- T{ ##peek f V int-regs 2 D 0 }
- T{ ##replace f V int-regs 1 D 0 }
- T{ ##replace f V int-regs 2 D 0 }
- T{ ##replace f V int-regs 0 D 0 }
+ T{ ##peek f V int-rep 1 D 0 }
+ T{ ##peek f V int-rep 2 D 0 }
+ T{ ##replace f V int-rep 1 D 0 }
+ T{ ##replace f V int-rep 2 D 0 }
+ T{ ##replace f V int-rep 0 D 0 }
T{ ##branch }
} 2 test-bb
} 3 test-bb
V{
- T{ ##replace f V int-regs 0 D 0 }
+ T{ ##replace f V int-rep 0 D 0 }
T{ ##return }
} 4 test-bb
{ id 12345 }
{ instructions
V{
- T{ ##gc f V int-regs 6 V int-regs 7 }
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##peek f V int-regs 1 D 1 }
- T{ ##peek f V int-regs 2 D 2 }
- T{ ##peek f V int-regs 3 D 3 }
- T{ ##peek f V int-regs 4 D 4 }
- T{ ##peek f V int-regs 5 D 5 }
- T{ ##replace f V int-regs 0 D 1 }
- T{ ##replace f V int-regs 1 D 2 }
- T{ ##replace f V int-regs 2 D 3 }
- T{ ##replace f V int-regs 3 D 4 }
- T{ ##replace f V int-regs 4 D 5 }
- T{ ##replace f V int-regs 5 D 0 }
+ T{ ##gc f V int-rep 6 V int-rep 7 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##peek f V int-rep 1 D 1 }
+ T{ ##peek f V int-rep 2 D 2 }
+ T{ ##peek f V int-rep 3 D 3 }
+ T{ ##peek f V int-rep 4 D 4 }
+ T{ ##peek f V int-rep 5 D 5 }
+ T{ ##replace f V int-rep 0 D 1 }
+ T{ ##replace f V int-rep 1 D 2 }
+ T{ ##replace f V int-rep 2 D 3 }
+ T{ ##replace f V int-rep 3 D 4 }
+ T{ ##replace f V int-rep 4 D 5 }
+ T{ ##replace f V int-rep 5 D 0 }
}
}
} cfg new over >>entry
{ { int-regs V{ 0 1 2 3 } } } (linear-scan)
instructions>> first
- live-values>> assoc-empty?
+ tagged-values>> assoc-empty?
] with-scope
] unit-test
V{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##peek f V int-regs 1 D 1 }
- T{ ##replace f V int-regs 1 D 1 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##peek f V int-rep 1 D 1 }
+ T{ ##replace f V int-rep 1 D 1 }
T{ ##branch }
} 0 test-bb
V{
- T{ ##gc f V int-regs 2 V int-regs 3 }
+ T{ ##gc f V int-rep 2 V int-rep 3 }
T{ ##branch }
} 1 test-bb
V{
- T{ ##replace f V int-regs 0 D 0 }
+ T{ ##replace f V int-rep 0 D 0 }
T{ ##return }
} 2 test-bb
[ ] [ { 1 2 3 } test-linear-scan-on-cfg ] unit-test
-[ H{ { V int-regs 0 3 } } ] [ 1 get instructions>> first live-values>> ] unit-test
+[ { 3 } ] [ 1 get instructions>> first tagged-values>> ] unit-test
V{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##peek f V int-regs 1 D 1 }
- T{ ##compare-imm-branch f V int-regs 1 5 cc= }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##peek f V int-rep 1 D 1 }
+ T{ ##compare-imm-branch f V int-rep 1 5 cc= }
} 0 test-bb
V{
- T{ ##gc f V int-regs 2 V int-regs 3 }
- T{ ##replace f V int-regs 0 D 0 }
+ T{ ##gc f V int-rep 2 V int-rep 3 }
+ T{ ##replace f V int-rep 0 D 0 }
T{ ##return }
} 1 test-bb
[ ] [ { 1 2 3 } test-linear-scan-on-cfg ] unit-test
-[ H{ { V int-regs 0 3 } } ] [ 1 get instructions>> first live-values>> ] unit-test
+[ { 3 } ] [ 1 get instructions>> first tagged-values>> ] unit-test
: linear-scan ( cfg -- cfg' )
[
dup machine-registers (linear-scan)
- spill-counts get >>spill-counts
cfg-changed
] with-scope ;
IN: compiler.cfg.linear-scan.resolve.tests
USING: compiler.cfg.linear-scan.resolve tools.test kernel namespaces
+accessors
+compiler.cfg
compiler.cfg.instructions cpu.architecture make sequences
compiler.cfg.linear-scan.allocation.state ;
[
{
- { { T{ spill-slot f 0 } int-regs } { 1 int-regs } }
+ { { T{ spill-slot f 0 } int-rep } { 1 int-rep } }
}
] [
[
- 0 <spill-slot> 1 int-regs add-mapping
+ 0 <spill-slot> 1 int-rep add-mapping
] { } make
] unit-test
[
{
- T{ _reload { dst 1 } { class int-regs } { n 0 } }
+ T{ _reload { dst 1 } { rep int-rep } { n 0 } }
}
] [
[
- { T{ spill-slot f 0 } int-regs } { 1 int-regs } >insn
+ { T{ spill-slot f 0 } int-rep } { 1 int-rep } >insn
] { } make
] unit-test
[
{
- T{ _spill { src 1 } { class int-regs } { n 0 } }
+ T{ _spill { src 1 } { rep int-rep } { n 0 } }
}
] [
[
- { 1 int-regs } { T{ spill-slot f 0 } int-regs } >insn
+ { 1 int-rep } { T{ spill-slot f 0 } int-rep } >insn
] { } make
] unit-test
[
{
- T{ _copy { src 1 } { dst 2 } { class int-regs } }
+ T{ ##copy { src 1 } { dst 2 } { rep int-rep } }
}
] [
[
- { 1 int-regs } { 2 int-regs } >insn
+ { 1 int-rep } { 2 int-rep } >insn
] { } make
] unit-test
-H{ { int-regs 10 } { float-regs 20 } } clone spill-counts set
+cfg new 8 >>spill-area-size cfg set
H{ } clone spill-temps set
[
t
] [
- { { { 0 int-regs } { 1 int-regs } } { { 1 int-regs } { 0 int-regs } } }
+ { { { 0 int-rep } { 1 int-rep } } { { 1 int-rep } { 0 int-rep } } }
mapping-instructions {
{
- T{ _spill { src 0 } { class int-regs } { n 10 } }
- T{ _copy { dst 0 } { src 1 } { class int-regs } }
- T{ _reload { dst 1 } { class int-regs } { n 10 } }
+ T{ _spill { src 0 } { rep int-rep } { n 8 } }
+ T{ ##copy { dst 0 } { src 1 } { rep int-rep } }
+ T{ _reload { dst 1 } { rep int-rep } { n 8 } }
}
{
- T{ _spill { src 1 } { class int-regs } { n 10 } }
- T{ _copy { dst 1 } { src 0 } { class int-regs } }
- T{ _reload { dst 0 } { class int-regs } { n 10 } }
+ T{ _spill { src 1 } { rep int-rep } { n 8 } }
+ T{ ##copy { dst 1 } { src 0 } { rep int-rep } }
+ T{ _reload { dst 0 } { rep int-rep } { n 8 } }
}
} member?
] unit-test
\ No newline at end of file
SYMBOL: spill-temps
-: spill-temp ( reg-class -- n )
+: spill-temp ( rep -- n )
spill-temps get [ next-spill-slot ] cache ;
-: add-mapping ( from to reg-class -- )
+: add-mapping ( from to rep -- )
'[ _ 2array ] bi@ 2array , ;
:: resolve-value-data-flow ( bb to vreg -- )
vreg bb vreg-at-end
vreg to vreg-at-start
- 2dup = [ 2drop ] [ vreg reg-class>> add-mapping ] if ;
+ 2dup = [ 2drop ] [ vreg rep>> add-mapping ] if ;
: compute-mappings ( bb to -- mappings )
dup live-in dup assoc-empty? [ 3drop f ] [
drop [ first2 ] [ second spill-temp ] bi _spill ;
: register->register ( from to -- )
- swap [ first ] [ first2 ] bi* _copy ;
+ swap [ first ] [ first2 ] bi* ##copy ;
SYMBOL: temp
! Copyright (C) 2008, 2009 Slava Pestov.
! See http://factorcode.org/license.txt for BSD license.
USING: kernel math accessors sequences namespaces make
-combinators assocs arrays locals cpu.architecture
+combinators assocs arrays locals layouts cpu.architecture
compiler.cfg
compiler.cfg.comparisons
compiler.cfg.stack-frame
[ successors>> [ block-number _dispatch-label ] each ]
bi* ;
-: (compute-gc-roots) ( n live-values -- n )
- [
- [ nip 2array , ]
- [ drop reg-class>> reg-size + ]
- 3bi
- ] assoc-each ;
-
-: oop-values ( regs -- regs' )
- [ drop reg-class>> int-regs eq? ] assoc-filter ;
-
-: data-values ( regs -- regs' )
- [ drop reg-class>> double-float-regs eq? ] assoc-filter ;
-
-: compute-gc-roots ( live-values -- alist )
- [
- [ 0 ] dip
- ! we put float registers last; the GC doesn't actually scan them
- [ oop-values (compute-gc-roots) ]
- [ data-values (compute-gc-roots) ] bi
- drop
- ] { } make ;
-
-: count-gc-roots ( live-values -- n )
- ! Size of GC root area, minus the float registers
- oop-values assoc-size ;
+: gc-root-offsets ( registers -- alist )
+ ! Outputs a sequence of { offset register/spill-slot } pairs
+ [ length iota [ cell * ] map ] keep zip ;
M: ##gc linearize-insn
nip
{
[ temp1>> ]
[ temp2>> ]
- [
- live-values>>
- [ compute-gc-roots ]
- [ count-gc-roots ]
- [ gc-roots-size ]
- tri
- ]
+ [ data-values>> ]
+ [ tagged-values>> gc-root-offsets dup length ]
[ uninitialized-locs>> ]
} cleave
_gc ;
: linearize-basic-blocks ( cfg -- insns )
[
[ linearization-order [ linearize-basic-block ] each ]
- [ spill-counts>> _spill-counts ]
+ [ spill-area-size>> _spill-area-size ]
bi
] { } make ;
! Sanity check...
V{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##replace f V int-regs 0 D 0 }
- T{ ##replace f V int-regs 1 D 1 }
- T{ ##peek f V int-regs 1 D 1 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##replace f V int-rep 0 D 0 }
+ T{ ##replace f V int-rep 1 D 1 }
+ T{ ##peek f V int-rep 1 D 1 }
T{ ##branch }
} 1 test-bb
V{
- T{ ##replace f V int-regs 2 D 0 }
+ T{ ##replace f V int-rep 2 D 0 }
T{ ##branch }
} 2 test-bb
V{
- T{ ##replace f V int-regs 3 D 0 }
+ T{ ##replace f V int-rep 3 D 0 }
T{ ##return }
} 3 test-bb
[
H{
- { V int-regs 1 V int-regs 1 }
- { V int-regs 2 V int-regs 2 }
- { V int-regs 3 V int-regs 3 }
+ { V int-rep 1 V int-rep 1 }
+ { V int-rep 2 V int-rep 2 }
+ { V int-rep 3 V int-rep 3 }
}
]
[ 1 get live-in ]
! Tricky case; defs must be killed before uses
V{
- T{ ##peek f V int-regs 0 D 0 }
+ T{ ##peek f V int-rep 0 D 0 }
T{ ##branch }
} 1 test-bb
V{
- T{ ##add-imm f V int-regs 0 V int-regs 0 10 }
+ T{ ##add-imm f V int-rep 0 V int-rep 0 10 }
T{ ##return }
} 2 test-bb
test-liveness
-[ H{ { V int-regs 0 V int-regs 0 } } ] [ 2 get live-in ] unit-test
\ No newline at end of file
+[ H{ { V int-rep 0 V int-rep 0 } } ] [ 2 get live-in ] unit-test
\ No newline at end of file
! Copyright (C) 2009 Slava Pestov.
! See http://factorcode.org/license.txt for BSD license.
-USING: compiler.cfg.linearization compiler.cfg.gc-checks
-compiler.cfg.linear-scan compiler.cfg.build-stack-frame
-compiler.cfg.rpo ;
+USING: kernel namespaces compiler.cfg compiler.cfg.linearization
+compiler.cfg.gc-checks compiler.cfg.linear-scan
+compiler.cfg.build-stack-frame ;
IN: compiler.cfg.mr
: build-mr ( cfg -- mr )
- insert-gc-checks
- linear-scan
- flatten-cfg
- build-stack-frame ;
\ No newline at end of file
+ dup cfg [
+ insert-gc-checks
+ linear-scan
+ flatten-cfg
+ build-stack-frame
+ ] with-variable ;
\ No newline at end of file
! Copyright (C) 2008, 2009 Slava Pestov.
! See http://factorcode.org/license.txt for BSD license.
USING: kernel sequences accessors combinators namespaces
+compiler.cfg
compiler.cfg.tco
compiler.cfg.useless-conditionals
compiler.cfg.branch-splitting
: optimize-cfg ( cfg -- cfg' )
! Note that compute-predecessors has to be called several times.
! The passes that need this document it.
- [
+ dup cfg [
optimize-tail-calls
delete-useless-conditionals
compute-predecessors
destruct-ssa
delete-empty-blocks
?check
- ] with-scope ;
+ ] with-variable ;
[
{
- T{ ##copy f V int-regs 4 V int-regs 2 }
- T{ ##copy f V int-regs 2 V int-regs 1 }
- T{ ##copy f V int-regs 1 V int-regs 4 }
+ T{ ##copy f V int-rep 4 V int-rep 2 int-rep }
+ T{ ##copy f V int-rep 2 V int-rep 1 int-rep }
+ T{ ##copy f V int-rep 1 V int-rep 4 int-rep }
}
] [
H{
- { V int-regs 1 V int-regs 2 }
- { V int-regs 2 V int-regs 1 }
+ { V int-rep 1 V int-rep 2 }
+ { V int-rep 2 V int-rep 1 }
} test-parallel-copy
] unit-test
[
{
- T{ ##copy f V int-regs 1 V int-regs 2 }
- T{ ##copy f V int-regs 3 V int-regs 4 }
+ T{ ##copy f V int-rep 1 V int-rep 2 int-rep }
+ T{ ##copy f V int-rep 3 V int-rep 4 int-rep }
}
] [
H{
- { V int-regs 1 V int-regs 2 }
- { V int-regs 3 V int-regs 4 }
+ { V int-rep 1 V int-rep 2 }
+ { V int-rep 3 V int-rep 4 }
} test-parallel-copy
] unit-test
[
{
- T{ ##copy f V int-regs 1 V int-regs 3 }
- T{ ##copy f V int-regs 2 V int-regs 1 }
+ T{ ##copy f V int-rep 1 V int-rep 3 int-rep }
+ T{ ##copy f V int-rep 2 V int-rep 1 int-rep }
}
] [
H{
- { V int-regs 1 V int-regs 3 }
- { V int-regs 2 V int-regs 3 }
+ { V int-rep 1 V int-rep 3 }
+ { V int-rep 2 V int-rep 3 }
} test-parallel-copy
] unit-test
[
{
- T{ ##copy f V int-regs 4 V int-regs 3 }
- T{ ##copy f V int-regs 3 V int-regs 2 }
- T{ ##copy f V int-regs 2 V int-regs 1 }
- T{ ##copy f V int-regs 1 V int-regs 4 }
+ T{ ##copy f V int-rep 4 V int-rep 3 int-rep }
+ T{ ##copy f V int-rep 3 V int-rep 2 int-rep }
+ T{ ##copy f V int-rep 2 V int-rep 1 int-rep }
+ T{ ##copy f V int-rep 1 V int-rep 4 int-rep }
}
] [
{
- { V int-regs 2 V int-regs 1 }
- { V int-regs 3 V int-regs 2 }
- { V int-regs 1 V int-regs 3 }
- { V int-regs 4 V int-regs 3 }
+ { V int-rep 2 V int-rep 1 }
+ { V int-rep 3 V int-rep 2 }
+ { V int-rep 1 V int-rep 3 }
+ { V int-rep 4 V int-rep 3 }
} test-parallel-copy
] unit-test
\ No newline at end of file
! Copyright (C) 2009 Slava Pestov.
! See http://factorcode.org/license.txt for BSD license.
-USING: assocs compiler.cfg.hats compiler.cfg.instructions
-deques dlists fry kernel locals namespaces sequences
-hashtables ;
+USING: assocs cpu.architecture compiler.cfg.hats
+compiler.cfg.instructions deques dlists fry kernel locals namespaces
+sequences hashtables ;
IN: compiler.cfg.parallel-copy
! Revisiting Out-of-SSA Translation for Correctness, Code Quality, and Efficiency
] slurp-deque
] with-scope ; inline
-: parallel-copy ( mapping -- ) i [ ##copy ] parallel-mapping ;
\ No newline at end of file
+: parallel-copy ( mapping -- ) i [ int-rep ##copy ] parallel-mapping ;
\ No newline at end of file
IN: compiler.cfg.registers
! Virtual registers, used by CFG and machine IRs
-TUPLE: vreg { reg-class read-only } { n fixnum read-only } ;
+TUPLE: vreg { rep read-only } { n fixnum read-only } ;
M: vreg equal? over vreg? [ [ n>> ] bi@ eq? ] [ 2drop f ] if ;
SYMBOL: vreg-counter
-: next-vreg ( reg-class -- vreg ) \ vreg-counter counter vreg boa ;
+: next-vreg ( rep -- vreg ) \ vreg-counter counter vreg boa ;
! Stack locations -- 'n' is an index starting from the top of the stack
! going down. So 0 is the top of the stack, 1 is what would be the top
renamings get ?at drop ;
: fresh-value ( vreg -- vreg' )
- reg-class>> next-vreg ;
+ rep>> next-vreg ;
RENAMING: rename [ rename-value ] [ rename-value ] [ fresh-value ]
reset-counters
V{
- T{ ##load-immediate f V int-regs 1 100 }
- T{ ##add-imm f V int-regs 2 V int-regs 1 50 }
- T{ ##add-imm f V int-regs 2 V int-regs 2 10 }
+ T{ ##load-immediate f V int-rep 1 100 }
+ T{ ##add-imm f V int-rep 2 V int-rep 1 50 }
+ T{ ##add-imm f V int-rep 2 V int-rep 2 10 }
T{ ##branch }
} 0 test-bb
V{
- T{ ##load-immediate f V int-regs 3 3 }
+ T{ ##load-immediate f V int-rep 3 3 }
T{ ##branch }
} 1 test-bb
V{
- T{ ##load-immediate f V int-regs 3 4 }
+ T{ ##load-immediate f V int-rep 3 4 }
T{ ##branch }
} 2 test-bb
V{
- T{ ##replace f V int-regs 3 D 0 }
+ T{ ##replace f V int-rep 3 D 0 }
T{ ##return }
} 3 test-bb
: test-ssa ( -- )
cfg new 0 get >>entry
+ dup cfg set
compute-predecessors
construct-ssa
drop ;
[
V{
- T{ ##load-immediate f V int-regs 1 100 }
- T{ ##add-imm f V int-regs 2 V int-regs 1 50 }
- T{ ##add-imm f V int-regs 3 V int-regs 2 10 }
+ T{ ##load-immediate f V int-rep 1 100 }
+ T{ ##add-imm f V int-rep 2 V int-rep 1 50 }
+ T{ ##add-imm f V int-rep 3 V int-rep 2 10 }
T{ ##branch }
}
] [ 0 get instructions>> ] unit-test
[
V{
- T{ ##load-immediate f V int-regs 4 3 }
+ T{ ##load-immediate f V int-rep 4 3 }
T{ ##branch }
}
] [ 1 get instructions>> ] unit-test
[
V{
- T{ ##load-immediate f V int-regs 5 4 }
+ T{ ##load-immediate f V int-rep 5 4 }
T{ ##branch }
}
] [ 2 get instructions>> ] unit-test
[
V{
- T{ ##phi f V int-regs 6 H{ { 1 V int-regs 4 } { 2 V int-regs 5 } } }
- T{ ##replace f V int-regs 6 D 0 }
+ T{ ##phi f V int-rep 6 H{ { 1 V int-rep 4 } { 2 V int-rep 5 } } }
+ T{ ##replace f V int-rep 6 D 0 }
T{ ##return }
}
] [
V{ } 0 test-bb
V{ } 1 test-bb
-V{ T{ ##peek f V int-regs 0 D 0 } } 2 test-bb
-V{ T{ ##peek f V int-regs 0 D 0 } } 3 test-bb
-V{ T{ ##replace f V int-regs 0 D 0 } } 4 test-bb
+V{ T{ ##peek f V int-rep 0 D 0 } } 2 test-bb
+V{ T{ ##peek f V int-rep 0 D 0 } } 3 test-bb
+V{ T{ ##replace f V int-rep 0 D 0 } } 4 test-bb
V{ } 5 test-bb
V{ } 6 test-bb
[
V{
- T{ ##phi f V int-regs 3 H{ { 2 V int-regs 1 } { 3 V int-regs 2 } } }
- T{ ##replace f V int-regs 3 D 0 }
+ T{ ##phi f V int-rep 3 H{ { 2 V int-rep 1 } { 3 V int-rep 2 } } }
+ T{ ##replace f V int-rep 3 D 0 }
}
] [
4 get instructions>>
compiler.cfg.registers
compiler.cfg.dominance
compiler.cfg.instructions
+compiler.cfg.renaming
compiler.cfg.renaming.functor
compiler.cfg.ssa.construction.tdmsc ;
IN: compiler.cfg.ssa.construction
H{ } clone stacks set ;
: gen-name ( vreg -- vreg' )
- [ reg-class>> next-vreg dup ] keep
+ [ fresh-value dup ] keep
dup pushed get 2dup key?
[ 2drop stacks get at set-last ]
[ conjoin stacks get push-at ]
IN: compiler.cfg.ssa.construction.tdmsc.tests
: test-tdmsc ( -- )
- cfg new 0 get >>entry
+ cfg new 0 get >>entry dup cfg set
compute-predecessors
dup compute-dominance
compute-merge-sets ;
PRIVATE>
: compute-merge-sets ( cfg -- )
- dup cfg set
H{ } clone visited set
[ compute-levels ]
[ init-merge-sets ]
! Copyright (C) 2009 Slava Pestov.
! See http://factorcode.org/license.txt for BSD license.
USING: accessors assocs kernel locals
+cpu.architecture
compiler.cfg.rpo
compiler.cfg.hats
compiler.cfg.utilities
:: insert-copy ( bb src -- bb dst )
i :> dst
- bb [ dst src ##copy ] add-instructions
+ bb [ dst src int-rep ##copy ] add-instructions
bb dst ;
: convert-phi ( ##phi -- )
GENERIC: prepare-insn ( insn -- )
-: prepare-copy ( insn -- )
+M: ##copy prepare-insn
[ dst>> ] [ src>> ] bi 2array copies get push ;
-M: ##copy prepare-insn prepare-copy ;
-
-M: ##copy-float prepare-insn prepare-copy ;
-
M: ##phi prepare-insn
[ dst>> ] [ inputs>> values ] bi
[ eliminate-copy ] with each ;
[ 2drop ] [ eliminate-copy ] if
] assoc-each ;
-UNION: copy-insn ##copy ##copy-float ;
-
: useless-copy? ( ##copy -- ? )
- dup copy-insn? [ [ dst>> ] [ src>> ] bi eq? ] [ drop f ] if ;
+ dup ##copy? [ [ dst>> ] [ src>> ] bi eq? ] [ drop f ] if ;
: perform-renaming ( cfg -- )
leader-map get keys [ dup leader ] H{ } map>assoc renamings set
compute-live-ranges ;
V{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##peek f V int-regs 2 D 0 }
- T{ ##copy f V int-regs 1 V int-regs 0 }
- T{ ##copy f V int-regs 3 V int-regs 2 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##peek f V int-rep 2 D 0 }
+ T{ ##copy f V int-rep 1 V int-rep 0 }
+ T{ ##copy f V int-rep 3 V int-rep 2 }
T{ ##branch }
} 0 test-bb
V{
- T{ ##peek f V int-regs 4 D 0 }
- T{ ##peek f V int-regs 5 D 0 }
- T{ ##replace f V int-regs 3 D 0 }
- T{ ##peek f V int-regs 6 D 0 }
- T{ ##replace f V int-regs 5 D 0 }
+ T{ ##peek f V int-rep 4 D 0 }
+ T{ ##peek f V int-rep 5 D 0 }
+ T{ ##replace f V int-rep 3 D 0 }
+ T{ ##peek f V int-rep 6 D 0 }
+ T{ ##replace f V int-rep 5 D 0 }
T{ ##return }
} 1 test-bb
[ ] [ test-interference ] unit-test
-[ f ] [ V int-regs 0 V int-regs 1 vregs-interfere? ] unit-test
-[ f ] [ V int-regs 1 V int-regs 0 vregs-interfere? ] unit-test
-[ f ] [ V int-regs 2 V int-regs 3 vregs-interfere? ] unit-test
-[ f ] [ V int-regs 3 V int-regs 2 vregs-interfere? ] unit-test
-[ t ] [ V int-regs 0 V int-regs 2 vregs-interfere? ] unit-test
-[ t ] [ V int-regs 2 V int-regs 0 vregs-interfere? ] unit-test
-[ f ] [ V int-regs 1 V int-regs 3 vregs-interfere? ] unit-test
-[ f ] [ V int-regs 3 V int-regs 1 vregs-interfere? ] unit-test
-[ t ] [ V int-regs 3 V int-regs 4 vregs-interfere? ] unit-test
-[ t ] [ V int-regs 4 V int-regs 3 vregs-interfere? ] unit-test
-[ t ] [ V int-regs 3 V int-regs 5 vregs-interfere? ] unit-test
-[ t ] [ V int-regs 5 V int-regs 3 vregs-interfere? ] unit-test
-[ f ] [ V int-regs 3 V int-regs 6 vregs-interfere? ] unit-test
-[ f ] [ V int-regs 6 V int-regs 3 vregs-interfere? ] unit-test
\ No newline at end of file
+[ f ] [ V int-rep 0 V int-rep 1 vregs-interfere? ] unit-test
+[ f ] [ V int-rep 1 V int-rep 0 vregs-interfere? ] unit-test
+[ f ] [ V int-rep 2 V int-rep 3 vregs-interfere? ] unit-test
+[ f ] [ V int-rep 3 V int-rep 2 vregs-interfere? ] unit-test
+[ t ] [ V int-rep 0 V int-rep 2 vregs-interfere? ] unit-test
+[ t ] [ V int-rep 2 V int-rep 0 vregs-interfere? ] unit-test
+[ f ] [ V int-rep 1 V int-rep 3 vregs-interfere? ] unit-test
+[ f ] [ V int-rep 3 V int-rep 1 vregs-interfere? ] unit-test
+[ t ] [ V int-rep 3 V int-rep 4 vregs-interfere? ] unit-test
+[ t ] [ V int-rep 4 V int-rep 3 vregs-interfere? ] unit-test
+[ t ] [ V int-rep 3 V int-rep 5 vregs-interfere? ] unit-test
+[ t ] [ V int-rep 5 V int-rep 3 vregs-interfere? ] unit-test
+[ f ] [ V int-rep 3 V int-rep 6 vregs-interfere? ] unit-test
+[ f ] [ V int-rep 6 V int-rep 3 vregs-interfere? ] unit-test
\ No newline at end of file
precompute-liveness ;
V{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##replace f V int-regs 0 D 0 }
- T{ ##replace f V int-regs 1 D 1 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##replace f V int-rep 0 D 0 }
+ T{ ##replace f V int-rep 1 D 1 }
} 0 test-bb
V{
- T{ ##replace f V int-regs 2 D 0 }
+ T{ ##replace f V int-rep 2 D 0 }
} 1 test-bb
V{
- T{ ##replace f V int-regs 3 D 0 }
+ T{ ##replace f V int-rep 3 D 0 }
} 2 test-bb
0 { 1 2 } edges
[ t ] [ 1 self-T_q ] unit-test
[ t ] [ 2 self-T_q ] unit-test
-[ f ] [ V int-regs 0 0 get live-in? ] unit-test
-[ t ] [ V int-regs 1 0 get live-in? ] unit-test
-[ t ] [ V int-regs 2 0 get live-in? ] unit-test
-[ t ] [ V int-regs 3 0 get live-in? ] unit-test
+[ f ] [ V int-rep 0 0 get live-in? ] unit-test
+[ t ] [ V int-rep 1 0 get live-in? ] unit-test
+[ t ] [ V int-rep 2 0 get live-in? ] unit-test
+[ t ] [ V int-rep 3 0 get live-in? ] unit-test
-[ f ] [ V int-regs 0 0 get live-out? ] unit-test
-[ f ] [ V int-regs 1 0 get live-out? ] unit-test
-[ t ] [ V int-regs 2 0 get live-out? ] unit-test
-[ t ] [ V int-regs 3 0 get live-out? ] unit-test
+[ f ] [ V int-rep 0 0 get live-out? ] unit-test
+[ f ] [ V int-rep 1 0 get live-out? ] unit-test
+[ t ] [ V int-rep 2 0 get live-out? ] unit-test
+[ t ] [ V int-rep 3 0 get live-out? ] unit-test
-[ f ] [ V int-regs 0 1 get live-in? ] unit-test
-[ f ] [ V int-regs 1 1 get live-in? ] unit-test
-[ t ] [ V int-regs 2 1 get live-in? ] unit-test
-[ f ] [ V int-regs 3 1 get live-in? ] unit-test
+[ f ] [ V int-rep 0 1 get live-in? ] unit-test
+[ f ] [ V int-rep 1 1 get live-in? ] unit-test
+[ t ] [ V int-rep 2 1 get live-in? ] unit-test
+[ f ] [ V int-rep 3 1 get live-in? ] unit-test
-[ f ] [ V int-regs 0 1 get live-out? ] unit-test
-[ f ] [ V int-regs 1 1 get live-out? ] unit-test
-[ f ] [ V int-regs 2 1 get live-out? ] unit-test
-[ f ] [ V int-regs 3 1 get live-out? ] unit-test
+[ f ] [ V int-rep 0 1 get live-out? ] unit-test
+[ f ] [ V int-rep 1 1 get live-out? ] unit-test
+[ f ] [ V int-rep 2 1 get live-out? ] unit-test
+[ f ] [ V int-rep 3 1 get live-out? ] unit-test
-[ f ] [ V int-regs 0 2 get live-in? ] unit-test
-[ f ] [ V int-regs 1 2 get live-in? ] unit-test
-[ f ] [ V int-regs 2 2 get live-in? ] unit-test
-[ t ] [ V int-regs 3 2 get live-in? ] unit-test
+[ f ] [ V int-rep 0 2 get live-in? ] unit-test
+[ f ] [ V int-rep 1 2 get live-in? ] unit-test
+[ f ] [ V int-rep 2 2 get live-in? ] unit-test
+[ t ] [ V int-rep 3 2 get live-in? ] unit-test
-[ f ] [ V int-regs 0 2 get live-out? ] unit-test
-[ f ] [ V int-regs 1 2 get live-out? ] unit-test
-[ f ] [ V int-regs 2 2 get live-out? ] unit-test
-[ f ] [ V int-regs 3 2 get live-out? ] unit-test
+[ f ] [ V int-rep 0 2 get live-out? ] unit-test
+[ f ] [ V int-rep 1 2 get live-out? ] unit-test
+[ f ] [ V int-rep 2 2 get live-out? ] unit-test
+[ f ] [ V int-rep 3 2 get live-out? ] unit-test
V{ } 0 test-bb
V{ } 1 test-bb
V{ } 2 test-bb
V{ } 3 test-bb
V{
- T{ ##phi f V int-regs 2 H{ { 2 V int-regs 0 } { 3 V int-regs 1 } } }
+ T{ ##phi f V int-rep 2 H{ { 2 V int-rep 0 } { 3 V int-rep 1 } } }
} 4 test-bb
test-diamond
[ ] [ test-liveness ] unit-test
-[ t ] [ V int-regs 0 1 get live-in? ] unit-test
-[ t ] [ V int-regs 1 1 get live-in? ] unit-test
-[ f ] [ V int-regs 2 1 get live-in? ] unit-test
+[ t ] [ V int-rep 0 1 get live-in? ] unit-test
+[ t ] [ V int-rep 1 1 get live-in? ] unit-test
+[ f ] [ V int-rep 2 1 get live-in? ] unit-test
-[ t ] [ V int-regs 0 1 get live-out? ] unit-test
-[ t ] [ V int-regs 1 1 get live-out? ] unit-test
-[ f ] [ V int-regs 2 1 get live-out? ] unit-test
+[ t ] [ V int-rep 0 1 get live-out? ] unit-test
+[ t ] [ V int-rep 1 1 get live-out? ] unit-test
+[ f ] [ V int-rep 2 1 get live-out? ] unit-test
-[ t ] [ V int-regs 0 2 get live-in? ] unit-test
-[ f ] [ V int-regs 1 2 get live-in? ] unit-test
-[ f ] [ V int-regs 2 2 get live-in? ] unit-test
+[ t ] [ V int-rep 0 2 get live-in? ] unit-test
+[ f ] [ V int-rep 1 2 get live-in? ] unit-test
+[ f ] [ V int-rep 2 2 get live-in? ] unit-test
-[ f ] [ V int-regs 0 2 get live-out? ] unit-test
-[ f ] [ V int-regs 1 2 get live-out? ] unit-test
-[ f ] [ V int-regs 2 2 get live-out? ] unit-test
+[ f ] [ V int-rep 0 2 get live-out? ] unit-test
+[ f ] [ V int-rep 1 2 get live-out? ] unit-test
+[ f ] [ V int-rep 2 2 get live-out? ] unit-test
-[ f ] [ V int-regs 0 3 get live-in? ] unit-test
-[ t ] [ V int-regs 1 3 get live-in? ] unit-test
-[ f ] [ V int-regs 2 3 get live-in? ] unit-test
+[ f ] [ V int-rep 0 3 get live-in? ] unit-test
+[ t ] [ V int-rep 1 3 get live-in? ] unit-test
+[ f ] [ V int-rep 2 3 get live-in? ] unit-test
-[ f ] [ V int-regs 0 3 get live-out? ] unit-test
-[ f ] [ V int-regs 1 3 get live-out? ] unit-test
-[ f ] [ V int-regs 2 3 get live-out? ] unit-test
+[ f ] [ V int-rep 0 3 get live-out? ] unit-test
+[ f ] [ V int-rep 1 3 get live-out? ] unit-test
+[ f ] [ V int-rep 2 3 get live-out? ] unit-test
-[ f ] [ V int-regs 0 4 get live-in? ] unit-test
-[ f ] [ V int-regs 1 4 get live-in? ] unit-test
-[ f ] [ V int-regs 2 4 get live-in? ] unit-test
+[ f ] [ V int-rep 0 4 get live-in? ] unit-test
+[ f ] [ V int-rep 1 4 get live-in? ] unit-test
+[ f ] [ V int-rep 2 4 get live-in? ] unit-test
-[ f ] [ V int-regs 0 4 get live-out? ] unit-test
-[ f ] [ V int-regs 1 4 get live-out? ] unit-test
-[ f ] [ V int-regs 2 4 get live-out? ] unit-test
+[ f ] [ V int-rep 0 4 get live-out? ] unit-test
+[ f ] [ V int-rep 1 4 get live-out? ] unit-test
+[ f ] [ V int-rep 2 4 get live-out? ] unit-test
! This is the CFG in Figure 3 from the paper
V{ } 0 test-bb
V{ } 2 test-bb
1 2 edge
V{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##peek f V int-regs 1 D 0 }
- T{ ##peek f V int-regs 2 D 0 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##peek f V int-rep 1 D 0 }
+ T{ ##peek f V int-rep 2 D 0 }
} 3 test-bb
V{ } 11 test-bb
2 { 3 11 } edges
V{
- T{ ##replace f V int-regs 0 D 0 }
+ T{ ##replace f V int-rep 0 D 0 }
} 4 test-bb
V{ } 8 test-bb
3 { 8 4 } edges
V{
- T{ ##replace f V int-regs 1 D 0 }
+ T{ ##replace f V int-rep 1 D 0 }
} 9 test-bb
8 9 edge
V{
- T{ ##replace f V int-regs 2 D 0 }
+ T{ ##replace f V int-rep 2 D 0 }
} 5 test-bb
4 5 edge
V{ } 10 test-bb
[ f ] [ 10 get back-edge-target? ] unit-test
[ f ] [ 11 get back-edge-target? ] unit-test
-[ f ] [ V int-regs 0 1 get live-in? ] unit-test
-[ f ] [ V int-regs 1 1 get live-in? ] unit-test
-[ f ] [ V int-regs 2 1 get live-in? ] unit-test
+[ f ] [ V int-rep 0 1 get live-in? ] unit-test
+[ f ] [ V int-rep 1 1 get live-in? ] unit-test
+[ f ] [ V int-rep 2 1 get live-in? ] unit-test
-[ f ] [ V int-regs 0 1 get live-out? ] unit-test
-[ f ] [ V int-regs 1 1 get live-out? ] unit-test
-[ f ] [ V int-regs 2 1 get live-out? ] unit-test
+[ f ] [ V int-rep 0 1 get live-out? ] unit-test
+[ f ] [ V int-rep 1 1 get live-out? ] unit-test
+[ f ] [ V int-rep 2 1 get live-out? ] unit-test
-[ f ] [ V int-regs 0 2 get live-in? ] unit-test
-[ f ] [ V int-regs 1 2 get live-in? ] unit-test
-[ f ] [ V int-regs 2 2 get live-in? ] unit-test
+[ f ] [ V int-rep 0 2 get live-in? ] unit-test
+[ f ] [ V int-rep 1 2 get live-in? ] unit-test
+[ f ] [ V int-rep 2 2 get live-in? ] unit-test
-[ f ] [ V int-regs 0 2 get live-out? ] unit-test
-[ f ] [ V int-regs 1 2 get live-out? ] unit-test
-[ f ] [ V int-regs 2 2 get live-out? ] unit-test
+[ f ] [ V int-rep 0 2 get live-out? ] unit-test
+[ f ] [ V int-rep 1 2 get live-out? ] unit-test
+[ f ] [ V int-rep 2 2 get live-out? ] unit-test
-[ f ] [ V int-regs 0 3 get live-in? ] unit-test
-[ f ] [ V int-regs 1 3 get live-in? ] unit-test
-[ f ] [ V int-regs 2 3 get live-in? ] unit-test
+[ f ] [ V int-rep 0 3 get live-in? ] unit-test
+[ f ] [ V int-rep 1 3 get live-in? ] unit-test
+[ f ] [ V int-rep 2 3 get live-in? ] unit-test
-[ t ] [ V int-regs 0 3 get live-out? ] unit-test
-[ t ] [ V int-regs 1 3 get live-out? ] unit-test
-[ t ] [ V int-regs 2 3 get live-out? ] unit-test
+[ t ] [ V int-rep 0 3 get live-out? ] unit-test
+[ t ] [ V int-rep 1 3 get live-out? ] unit-test
+[ t ] [ V int-rep 2 3 get live-out? ] unit-test
-[ t ] [ V int-regs 0 4 get live-in? ] unit-test
-[ f ] [ V int-regs 1 4 get live-in? ] unit-test
-[ t ] [ V int-regs 2 4 get live-in? ] unit-test
+[ t ] [ V int-rep 0 4 get live-in? ] unit-test
+[ f ] [ V int-rep 1 4 get live-in? ] unit-test
+[ t ] [ V int-rep 2 4 get live-in? ] unit-test
-[ f ] [ V int-regs 0 4 get live-out? ] unit-test
-[ f ] [ V int-regs 1 4 get live-out? ] unit-test
-[ t ] [ V int-regs 2 4 get live-out? ] unit-test
+[ f ] [ V int-rep 0 4 get live-out? ] unit-test
+[ f ] [ V int-rep 1 4 get live-out? ] unit-test
+[ t ] [ V int-rep 2 4 get live-out? ] unit-test
-[ f ] [ V int-regs 0 5 get live-in? ] unit-test
-[ f ] [ V int-regs 1 5 get live-in? ] unit-test
-[ t ] [ V int-regs 2 5 get live-in? ] unit-test
+[ f ] [ V int-rep 0 5 get live-in? ] unit-test
+[ f ] [ V int-rep 1 5 get live-in? ] unit-test
+[ t ] [ V int-rep 2 5 get live-in? ] unit-test
-[ f ] [ V int-regs 0 5 get live-out? ] unit-test
-[ f ] [ V int-regs 1 5 get live-out? ] unit-test
-[ t ] [ V int-regs 2 5 get live-out? ] unit-test
+[ f ] [ V int-rep 0 5 get live-out? ] unit-test
+[ f ] [ V int-rep 1 5 get live-out? ] unit-test
+[ t ] [ V int-rep 2 5 get live-out? ] unit-test
-[ f ] [ V int-regs 0 6 get live-in? ] unit-test
-[ f ] [ V int-regs 1 6 get live-in? ] unit-test
-[ t ] [ V int-regs 2 6 get live-in? ] unit-test
+[ f ] [ V int-rep 0 6 get live-in? ] unit-test
+[ f ] [ V int-rep 1 6 get live-in? ] unit-test
+[ t ] [ V int-rep 2 6 get live-in? ] unit-test
-[ f ] [ V int-regs 0 6 get live-out? ] unit-test
-[ f ] [ V int-regs 1 6 get live-out? ] unit-test
-[ t ] [ V int-regs 2 6 get live-out? ] unit-test
+[ f ] [ V int-rep 0 6 get live-out? ] unit-test
+[ f ] [ V int-rep 1 6 get live-out? ] unit-test
+[ t ] [ V int-rep 2 6 get live-out? ] unit-test
-[ f ] [ V int-regs 0 7 get live-in? ] unit-test
-[ f ] [ V int-regs 1 7 get live-in? ] unit-test
-[ f ] [ V int-regs 2 7 get live-in? ] unit-test
+[ f ] [ V int-rep 0 7 get live-in? ] unit-test
+[ f ] [ V int-rep 1 7 get live-in? ] unit-test
+[ f ] [ V int-rep 2 7 get live-in? ] unit-test
-[ f ] [ V int-regs 0 7 get live-out? ] unit-test
-[ f ] [ V int-regs 1 7 get live-out? ] unit-test
-[ f ] [ V int-regs 2 7 get live-out? ] unit-test
+[ f ] [ V int-rep 0 7 get live-out? ] unit-test
+[ f ] [ V int-rep 1 7 get live-out? ] unit-test
+[ f ] [ V int-rep 2 7 get live-out? ] unit-test
-[ f ] [ V int-regs 0 8 get live-in? ] unit-test
-[ t ] [ V int-regs 1 8 get live-in? ] unit-test
-[ t ] [ V int-regs 2 8 get live-in? ] unit-test
+[ f ] [ V int-rep 0 8 get live-in? ] unit-test
+[ t ] [ V int-rep 1 8 get live-in? ] unit-test
+[ t ] [ V int-rep 2 8 get live-in? ] unit-test
-[ f ] [ V int-regs 0 8 get live-out? ] unit-test
-[ t ] [ V int-regs 1 8 get live-out? ] unit-test
-[ t ] [ V int-regs 2 8 get live-out? ] unit-test
+[ f ] [ V int-rep 0 8 get live-out? ] unit-test
+[ t ] [ V int-rep 1 8 get live-out? ] unit-test
+[ t ] [ V int-rep 2 8 get live-out? ] unit-test
-[ f ] [ V int-regs 0 9 get live-in? ] unit-test
-[ t ] [ V int-regs 1 9 get live-in? ] unit-test
-[ t ] [ V int-regs 2 9 get live-in? ] unit-test
+[ f ] [ V int-rep 0 9 get live-in? ] unit-test
+[ t ] [ V int-rep 1 9 get live-in? ] unit-test
+[ t ] [ V int-rep 2 9 get live-in? ] unit-test
-[ f ] [ V int-regs 0 9 get live-out? ] unit-test
-[ t ] [ V int-regs 1 9 get live-out? ] unit-test
-[ t ] [ V int-regs 2 9 get live-out? ] unit-test
+[ f ] [ V int-rep 0 9 get live-out? ] unit-test
+[ t ] [ V int-rep 1 9 get live-out? ] unit-test
+[ t ] [ V int-rep 2 9 get live-out? ] unit-test
-[ f ] [ V int-regs 0 10 get live-in? ] unit-test
-[ t ] [ V int-regs 1 10 get live-in? ] unit-test
-[ t ] [ V int-regs 2 10 get live-in? ] unit-test
+[ f ] [ V int-rep 0 10 get live-in? ] unit-test
+[ t ] [ V int-rep 1 10 get live-in? ] unit-test
+[ t ] [ V int-rep 2 10 get live-in? ] unit-test
-[ f ] [ V int-regs 0 10 get live-out? ] unit-test
-[ t ] [ V int-regs 1 10 get live-out? ] unit-test
-[ t ] [ V int-regs 2 10 get live-out? ] unit-test
+[ f ] [ V int-rep 0 10 get live-out? ] unit-test
+[ t ] [ V int-rep 1 10 get live-out? ] unit-test
+[ t ] [ V int-rep 2 10 get live-out? ] unit-test
-[ f ] [ V int-regs 0 11 get live-in? ] unit-test
-[ f ] [ V int-regs 1 11 get live-in? ] unit-test
-[ f ] [ V int-regs 2 11 get live-in? ] unit-test
+[ f ] [ V int-rep 0 11 get live-in? ] unit-test
+[ f ] [ V int-rep 1 11 get live-in? ] unit-test
+[ f ] [ V int-rep 2 11 get live-in? ] unit-test
-[ f ] [ V int-regs 0 11 get live-out? ] unit-test
-[ f ] [ V int-regs 1 11 get live-out? ] unit-test
-[ f ] [ V int-regs 2 11 get live-out? ] unit-test
+[ f ] [ V int-rep 0 11 get live-out? ] unit-test
+[ f ] [ V int-rep 1 11 get live-out? ] unit-test
+[ f ] [ V int-rep 2 11 get live-out? ] unit-test
{ return integer }
{ total-size integer }
{ gc-root-size integer }
-spill-counts ;
+{ spill-area-size integer } ;
! Stack frame utilities
: param-base ( -- n )
stack-frame get [ params>> ] [ return>> ] bi + ;
-: spill-float-offset ( n -- offset )
- double-float-regs reg-size * ;
-
-: spill-integer-base ( -- n )
- stack-frame get spill-counts>> double-float-regs [ swap at ] keep reg-size *
+: spill-offset ( n -- offset )
param-base + ;
-: spill-integer-offset ( n -- offset )
- cells spill-integer-base + ;
-
-: spill-area-size ( stack-frame -- n )
- spill-counts>> [ swap reg-size * ] { } assoc>map sum ;
-
: gc-root-base ( -- n )
- stack-frame get spill-area-size
- param-base + ;
+ stack-frame get spill-area-size>> param-base + ;
: gc-root-offset ( n -- n' ) gc-root-base + ;
-: gc-roots-size ( live-values -- n )
- keys [ reg-class>> reg-size ] sigma ;
-
: (stack-frame-size) ( stack-frame -- n )
[
{
- [ spill-area-size ]
- [ gc-root-size>> ]
[ params>> ]
[ return>> ]
+ [ gc-root-size>> ]
+ [ spill-area-size>> ]
} cleave
] sum-outputs ;
} 0 test-bb
V{
- T{ ##replace f V int-regs 0 D 0 }
- T{ ##replace f V int-regs 0 D 1 }
- T{ ##replace f V int-regs 0 D 2 }
+ T{ ##replace f V int-rep 0 D 0 }
+ T{ ##replace f V int-rep 0 D 1 }
+ T{ ##replace f V int-rep 0 D 2 }
T{ ##inc-r f 1 }
} 1 test-bb
V{
- T{ ##peek f V int-regs 0 D 0 }
+ T{ ##peek f V int-rep 0 D 0 }
T{ ##inc-d f 1 }
} 2 test-bb
] [ drop ] if ;
: optimize-tail-calls ( cfg -- cfg' )
- dup cfg set
dup [ optimize-tail-call ] each-basic-block
cfg-changed ;
\ No newline at end of file
[
V{
- T{ ##copy f V int-regs 1 V int-regs 2 }
- T{ ##sub f V int-regs 1 V int-regs 1 V int-regs 3 }
+ T{ ##copy f V int-rep 1 V int-rep 2 int-rep }
+ T{ ##sub f V int-rep 1 V int-rep 1 V int-rep 3 }
}
] [
{
- T{ ##sub f V int-regs 1 V int-regs 2 V int-regs 3 }
+ T{ ##sub f V int-rep 1 V int-rep 2 V int-rep 3 }
+ } (convert-two-operand)
+] unit-test
+
+[
+ V{
+ T{ ##copy f V double-float-rep 1 V double-float-rep 2 double-float-rep }
+ T{ ##sub-float f V double-float-rep 1 V double-float-rep 1 V double-float-rep 3 }
+ }
+] [
+ {
+ T{ ##sub-float f V double-float-rep 1 V double-float-rep 2 V double-float-rep 3 }
} (convert-two-operand)
] unit-test
GENERIC: convert-two-operand* ( insn -- )
: emit-copy ( dst src -- )
- dup reg-class>> {
- { int-regs [ ##copy ] }
- { double-float-regs [ ##copy-float ] }
- } case ; inline
+ dup rep>> ##copy ; inline
M: two-operand-insn convert-two-operand*
[ [ dst>> ] [ src1>> ] bi emit-copy ]
#! its source VN.
[ in>> vn>expr ] [ op>> ] bi {
{ \ ##copy [ ] }
- { \ ##copy-float [ ] }
{ \ ##unbox-float [ simplify-unbox-float ] }
{ \ ##unbox-alien [ simplify-unbox-alien ] }
{ \ ##unbox-any-c-ptr [ simplify-unbox-alien ] }
! Folding constants together
[
{
- T{ ##load-reference f V int-regs 0 0.0 }
- T{ ##load-reference f V int-regs 1 -0.0 }
- T{ ##replace f V int-regs 0 D 0 }
- T{ ##replace f V int-regs 1 D 1 }
+ T{ ##load-reference f V int-rep 0 0.0 }
+ T{ ##load-reference f V int-rep 1 -0.0 }
+ T{ ##replace f V int-rep 0 D 0 }
+ T{ ##replace f V int-rep 1 D 1 }
}
] [
{
- T{ ##load-reference f V int-regs 0 0.0 }
- T{ ##load-reference f V int-regs 1 -0.0 }
- T{ ##replace f V int-regs 0 D 0 }
- T{ ##replace f V int-regs 1 D 1 }
+ T{ ##load-reference f V int-rep 0 0.0 }
+ T{ ##load-reference f V int-rep 1 -0.0 }
+ T{ ##replace f V int-rep 0 D 0 }
+ T{ ##replace f V int-rep 1 D 1 }
} value-numbering-step
] unit-test
[
{
- T{ ##load-reference f V int-regs 0 0.0 }
- T{ ##copy f V int-regs 1 V int-regs 0 }
- T{ ##replace f V int-regs 0 D 0 }
- T{ ##replace f V int-regs 1 D 1 }
+ T{ ##load-reference f V int-rep 0 0.0 }
+ T{ ##copy f V int-rep 1 V int-rep 0 int-rep }
+ T{ ##replace f V int-rep 0 D 0 }
+ T{ ##replace f V int-rep 1 D 1 }
}
] [
{
- T{ ##load-reference f V int-regs 0 0.0 }
- T{ ##load-reference f V int-regs 1 0.0 }
- T{ ##replace f V int-regs 0 D 0 }
- T{ ##replace f V int-regs 1 D 1 }
+ T{ ##load-reference f V int-rep 0 0.0 }
+ T{ ##load-reference f V int-rep 1 0.0 }
+ T{ ##replace f V int-rep 0 D 0 }
+ T{ ##replace f V int-rep 1 D 1 }
} value-numbering-step
] unit-test
[
{
- T{ ##load-reference f V int-regs 0 t }
- T{ ##copy f V int-regs 1 V int-regs 0 }
- T{ ##replace f V int-regs 0 D 0 }
- T{ ##replace f V int-regs 1 D 1 }
+ T{ ##load-reference f V int-rep 0 t }
+ T{ ##copy f V int-rep 1 V int-rep 0 int-rep }
+ T{ ##replace f V int-rep 0 D 0 }
+ T{ ##replace f V int-rep 1 D 1 }
}
] [
{
- T{ ##load-reference f V int-regs 0 t }
- T{ ##load-reference f V int-regs 1 t }
- T{ ##replace f V int-regs 0 D 0 }
- T{ ##replace f V int-regs 1 D 1 }
+ T{ ##load-reference f V int-rep 0 t }
+ T{ ##load-reference f V int-rep 1 t }
+ T{ ##replace f V int-rep 0 D 0 }
+ T{ ##replace f V int-rep 1 D 1 }
} value-numbering-step
] unit-test
! Compare propagation
[
{
- T{ ##load-reference f V int-regs 1 + }
- T{ ##peek f V int-regs 2 D 0 }
- T{ ##compare f V int-regs 4 V int-regs 2 V int-regs 1 cc> }
- T{ ##copy f V int-regs 6 V int-regs 4 }
- T{ ##replace f V int-regs 6 D 0 }
+ T{ ##load-reference f V int-rep 1 + }
+ T{ ##peek f V int-rep 2 D 0 }
+ T{ ##compare f V int-rep 4 V int-rep 2 V int-rep 1 cc> }
+ T{ ##copy f V int-rep 6 V int-rep 4 int-rep }
+ T{ ##replace f V int-rep 6 D 0 }
}
] [
{
- T{ ##load-reference f V int-regs 1 + }
- T{ ##peek f V int-regs 2 D 0 }
- T{ ##compare f V int-regs 4 V int-regs 2 V int-regs 1 cc> }
- T{ ##compare-imm f V int-regs 6 V int-regs 4 5 cc/= }
- T{ ##replace f V int-regs 6 D 0 }
+ T{ ##load-reference f V int-rep 1 + }
+ T{ ##peek f V int-rep 2 D 0 }
+ T{ ##compare f V int-rep 4 V int-rep 2 V int-rep 1 cc> }
+ T{ ##compare-imm f V int-rep 6 V int-rep 4 5 cc/= }
+ T{ ##replace f V int-rep 6 D 0 }
} value-numbering-step trim-temps
] unit-test
[
{
- T{ ##load-reference f V int-regs 1 + }
- T{ ##peek f V int-regs 2 D 0 }
- T{ ##compare f V int-regs 4 V int-regs 2 V int-regs 1 cc<= }
- T{ ##compare f V int-regs 6 V int-regs 2 V int-regs 1 cc> }
- T{ ##replace f V int-regs 6 D 0 }
+ T{ ##load-reference f V int-rep 1 + }
+ T{ ##peek f V int-rep 2 D 0 }
+ T{ ##compare f V int-rep 4 V int-rep 2 V int-rep 1 cc<= }
+ T{ ##compare f V int-rep 6 V int-rep 2 V int-rep 1 cc> }
+ T{ ##replace f V int-rep 6 D 0 }
}
] [
{
- T{ ##load-reference f V int-regs 1 + }
- T{ ##peek f V int-regs 2 D 0 }
- T{ ##compare f V int-regs 4 V int-regs 2 V int-regs 1 cc<= }
- T{ ##compare-imm f V int-regs 6 V int-regs 4 5 cc= }
- T{ ##replace f V int-regs 6 D 0 }
+ T{ ##load-reference f V int-rep 1 + }
+ T{ ##peek f V int-rep 2 D 0 }
+ T{ ##compare f V int-rep 4 V int-rep 2 V int-rep 1 cc<= }
+ T{ ##compare-imm f V int-rep 6 V int-rep 4 5 cc= }
+ T{ ##replace f V int-rep 6 D 0 }
} value-numbering-step trim-temps
] unit-test
[
{
- T{ ##peek f V int-regs 8 D 0 }
- T{ ##peek f V int-regs 9 D -1 }
- T{ ##unbox-float f V double-float-regs 10 V int-regs 8 }
- T{ ##unbox-float f V double-float-regs 11 V int-regs 9 }
- T{ ##compare-float f V int-regs 12 V double-float-regs 10 V double-float-regs 11 cc< }
- T{ ##compare-float f V int-regs 14 V double-float-regs 10 V double-float-regs 11 cc>= }
- T{ ##replace f V int-regs 14 D 0 }
+ T{ ##peek f V int-rep 8 D 0 }
+ T{ ##peek f V int-rep 9 D -1 }
+ T{ ##unbox-float f V double-float-rep 10 V int-rep 8 }
+ T{ ##unbox-float f V double-float-rep 11 V int-rep 9 }
+ T{ ##compare-float f V int-rep 12 V double-float-rep 10 V double-float-rep 11 cc< }
+ T{ ##compare-float f V int-rep 14 V double-float-rep 10 V double-float-rep 11 cc>= }
+ T{ ##replace f V int-rep 14 D 0 }
}
] [
{
- T{ ##peek f V int-regs 8 D 0 }
- T{ ##peek f V int-regs 9 D -1 }
- T{ ##unbox-float f V double-float-regs 10 V int-regs 8 }
- T{ ##unbox-float f V double-float-regs 11 V int-regs 9 }
- T{ ##compare-float f V int-regs 12 V double-float-regs 10 V double-float-regs 11 cc< }
- T{ ##compare-imm f V int-regs 14 V int-regs 12 5 cc= }
- T{ ##replace f V int-regs 14 D 0 }
+ T{ ##peek f V int-rep 8 D 0 }
+ T{ ##peek f V int-rep 9 D -1 }
+ T{ ##unbox-float f V double-float-rep 10 V int-rep 8 }
+ T{ ##unbox-float f V double-float-rep 11 V int-rep 9 }
+ T{ ##compare-float f V int-rep 12 V double-float-rep 10 V double-float-rep 11 cc< }
+ T{ ##compare-imm f V int-rep 14 V int-rep 12 5 cc= }
+ T{ ##replace f V int-rep 14 D 0 }
} value-numbering-step trim-temps
] unit-test
[
{
- T{ ##peek f V int-regs 29 D -1 }
- T{ ##peek f V int-regs 30 D -2 }
- T{ ##compare f V int-regs 33 V int-regs 29 V int-regs 30 cc<= }
- T{ ##compare-branch f V int-regs 29 V int-regs 30 cc<= }
+ T{ ##peek f V int-rep 29 D -1 }
+ T{ ##peek f V int-rep 30 D -2 }
+ T{ ##compare f V int-rep 33 V int-rep 29 V int-rep 30 cc<= }
+ T{ ##compare-branch f V int-rep 29 V int-rep 30 cc<= }
}
] [
{
- T{ ##peek f V int-regs 29 D -1 }
- T{ ##peek f V int-regs 30 D -2 }
- T{ ##compare f V int-regs 33 V int-regs 29 V int-regs 30 cc<= }
- T{ ##compare-imm-branch f V int-regs 33 5 cc/= }
+ T{ ##peek f V int-rep 29 D -1 }
+ T{ ##peek f V int-rep 30 D -2 }
+ T{ ##compare f V int-rep 33 V int-rep 29 V int-rep 30 cc<= }
+ T{ ##compare-imm-branch f V int-rep 33 5 cc/= }
} value-numbering-step trim-temps
] unit-test
! Immediate operand conversion
[
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 100 }
- T{ ##add-imm f V int-regs 2 V int-regs 0 100 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 100 }
+ T{ ##add-imm f V int-rep 2 V int-rep 0 100 }
}
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 100 }
- T{ ##add f V int-regs 2 V int-regs 0 V int-regs 1 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 100 }
+ T{ ##add f V int-rep 2 V int-rep 0 V int-rep 1 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 100 }
- T{ ##add-imm f V int-regs 2 V int-regs 0 100 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 100 }
+ T{ ##add-imm f V int-rep 2 V int-rep 0 100 }
}
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 100 }
- T{ ##add f V int-regs 2 V int-regs 1 V int-regs 0 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 100 }
+ T{ ##add f V int-rep 2 V int-rep 1 V int-rep 0 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 100 }
- T{ ##add-imm f V int-regs 2 V int-regs 0 -100 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 100 }
+ T{ ##add-imm f V int-rep 2 V int-rep 0 -100 }
}
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 100 }
- T{ ##sub f V int-regs 2 V int-regs 0 V int-regs 1 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 100 }
+ T{ ##sub f V int-rep 2 V int-rep 0 V int-rep 1 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 0 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 0 }
}
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##sub f V int-regs 1 V int-regs 0 V int-regs 0 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##sub f V int-rep 1 V int-rep 0 V int-rep 0 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 100 }
- T{ ##mul-imm f V int-regs 2 V int-regs 0 100 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 100 }
+ T{ ##mul-imm f V int-rep 2 V int-rep 0 100 }
}
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 100 }
- T{ ##mul f V int-regs 2 V int-regs 0 V int-regs 1 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 100 }
+ T{ ##mul f V int-rep 2 V int-rep 0 V int-rep 1 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 100 }
- T{ ##mul-imm f V int-regs 2 V int-regs 0 100 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 100 }
+ T{ ##mul-imm f V int-rep 2 V int-rep 0 100 }
}
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 100 }
- T{ ##mul f V int-regs 2 V int-regs 1 V int-regs 0 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 100 }
+ T{ ##mul f V int-rep 2 V int-rep 1 V int-rep 0 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-regs 1 D 0 }
- T{ ##shl-imm f V int-regs 2 V int-regs 1 3 }
+ T{ ##peek f V int-rep 1 D 0 }
+ T{ ##shl-imm f V int-rep 2 V int-rep 1 3 }
}
] [
{
- T{ ##peek f V int-regs 1 D 0 }
- T{ ##mul-imm f V int-regs 2 V int-regs 1 8 }
+ T{ ##peek f V int-rep 1 D 0 }
+ T{ ##mul-imm f V int-rep 2 V int-rep 1 8 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 100 }
- T{ ##and-imm f V int-regs 2 V int-regs 0 100 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 100 }
+ T{ ##and-imm f V int-rep 2 V int-rep 0 100 }
}
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 100 }
- T{ ##and f V int-regs 2 V int-regs 0 V int-regs 1 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 100 }
+ T{ ##and f V int-rep 2 V int-rep 0 V int-rep 1 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 100 }
- T{ ##and-imm f V int-regs 2 V int-regs 0 100 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 100 }
+ T{ ##and-imm f V int-rep 2 V int-rep 0 100 }
}
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 100 }
- T{ ##and f V int-regs 2 V int-regs 1 V int-regs 0 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 100 }
+ T{ ##and f V int-rep 2 V int-rep 1 V int-rep 0 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 100 }
- T{ ##or-imm f V int-regs 2 V int-regs 0 100 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 100 }
+ T{ ##or-imm f V int-rep 2 V int-rep 0 100 }
}
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 100 }
- T{ ##or f V int-regs 2 V int-regs 0 V int-regs 1 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 100 }
+ T{ ##or f V int-rep 2 V int-rep 0 V int-rep 1 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 100 }
- T{ ##or-imm f V int-regs 2 V int-regs 0 100 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 100 }
+ T{ ##or-imm f V int-rep 2 V int-rep 0 100 }
}
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 100 }
- T{ ##or f V int-regs 2 V int-regs 1 V int-regs 0 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 100 }
+ T{ ##or f V int-rep 2 V int-rep 1 V int-rep 0 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 100 }
- T{ ##xor-imm f V int-regs 2 V int-regs 0 100 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 100 }
+ T{ ##xor-imm f V int-rep 2 V int-rep 0 100 }
}
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 100 }
- T{ ##xor f V int-regs 2 V int-regs 0 V int-regs 1 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 100 }
+ T{ ##xor f V int-rep 2 V int-rep 0 V int-rep 1 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 100 }
- T{ ##xor-imm f V int-regs 2 V int-regs 0 100 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 100 }
+ T{ ##xor-imm f V int-rep 2 V int-rep 0 100 }
}
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 100 }
- T{ ##xor f V int-regs 2 V int-regs 1 V int-regs 0 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 100 }
+ T{ ##xor f V int-rep 2 V int-rep 1 V int-rep 0 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 100 }
- T{ ##compare-imm f V int-regs 2 V int-regs 0 100 cc<= }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 100 }
+ T{ ##compare-imm f V int-rep 2 V int-rep 0 100 cc<= }
}
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 100 }
- T{ ##compare f V int-regs 2 V int-regs 0 V int-regs 1 cc<= }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 100 }
+ T{ ##compare f V int-rep 2 V int-rep 0 V int-rep 1 cc<= }
} value-numbering-step trim-temps
] unit-test
[
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 100 }
- T{ ##compare-imm f V int-regs 2 V int-regs 0 100 cc>= }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 100 }
+ T{ ##compare-imm f V int-rep 2 V int-rep 0 100 cc>= }
}
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 100 }
- T{ ##compare f V int-regs 2 V int-regs 1 V int-regs 0 cc<= }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 100 }
+ T{ ##compare f V int-rep 2 V int-rep 1 V int-rep 0 cc<= }
} value-numbering-step trim-temps
] unit-test
[
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 100 }
- T{ ##compare-imm-branch f V int-regs 0 100 cc<= }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 100 }
+ T{ ##compare-imm-branch f V int-rep 0 100 cc<= }
}
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 100 }
- T{ ##compare-branch f V int-regs 0 V int-regs 1 cc<= }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 100 }
+ T{ ##compare-branch f V int-rep 0 V int-rep 1 cc<= }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 100 }
- T{ ##compare-imm-branch f V int-regs 0 100 cc>= }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 100 }
+ T{ ##compare-imm-branch f V int-rep 0 100 cc>= }
}
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 100 }
- T{ ##compare-branch f V int-regs 1 V int-regs 0 cc<= }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 100 }
+ T{ ##compare-branch f V int-rep 1 V int-rep 0 cc<= }
} value-numbering-step trim-temps
] unit-test
! Reassociation
[
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 100 }
- T{ ##add-imm f V int-regs 2 V int-regs 0 100 }
- T{ ##load-immediate f V int-regs 3 50 }
- T{ ##add-imm f V int-regs 4 V int-regs 0 150 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 100 }
+ T{ ##add-imm f V int-rep 2 V int-rep 0 100 }
+ T{ ##load-immediate f V int-rep 3 50 }
+ T{ ##add-imm f V int-rep 4 V int-rep 0 150 }
}
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 100 }
- T{ ##add f V int-regs 2 V int-regs 0 V int-regs 1 }
- T{ ##load-immediate f V int-regs 3 50 }
- T{ ##add f V int-regs 4 V int-regs 2 V int-regs 3 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 100 }
+ T{ ##add f V int-rep 2 V int-rep 0 V int-rep 1 }
+ T{ ##load-immediate f V int-rep 3 50 }
+ T{ ##add f V int-rep 4 V int-rep 2 V int-rep 3 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 100 }
- T{ ##add-imm f V int-regs 2 V int-regs 0 100 }
- T{ ##load-immediate f V int-regs 3 50 }
- T{ ##add-imm f V int-regs 4 V int-regs 0 150 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 100 }
+ T{ ##add-imm f V int-rep 2 V int-rep 0 100 }
+ T{ ##load-immediate f V int-rep 3 50 }
+ T{ ##add-imm f V int-rep 4 V int-rep 0 150 }
}
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 100 }
- T{ ##add f V int-regs 2 V int-regs 1 V int-regs 0 }
- T{ ##load-immediate f V int-regs 3 50 }
- T{ ##add f V int-regs 4 V int-regs 3 V int-regs 2 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 100 }
+ T{ ##add f V int-rep 2 V int-rep 1 V int-rep 0 }
+ T{ ##load-immediate f V int-rep 3 50 }
+ T{ ##add f V int-rep 4 V int-rep 3 V int-rep 2 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 100 }
- T{ ##add-imm f V int-regs 2 V int-regs 0 100 }
- T{ ##load-immediate f V int-regs 3 50 }
- T{ ##add-imm f V int-regs 4 V int-regs 0 50 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 100 }
+ T{ ##add-imm f V int-rep 2 V int-rep 0 100 }
+ T{ ##load-immediate f V int-rep 3 50 }
+ T{ ##add-imm f V int-rep 4 V int-rep 0 50 }
}
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 100 }
- T{ ##add f V int-regs 2 V int-regs 0 V int-regs 1 }
- T{ ##load-immediate f V int-regs 3 50 }
- T{ ##sub f V int-regs 4 V int-regs 2 V int-regs 3 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 100 }
+ T{ ##add f V int-rep 2 V int-rep 0 V int-rep 1 }
+ T{ ##load-immediate f V int-rep 3 50 }
+ T{ ##sub f V int-rep 4 V int-rep 2 V int-rep 3 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 100 }
- T{ ##add-imm f V int-regs 2 V int-regs 0 -100 }
- T{ ##load-immediate f V int-regs 3 50 }
- T{ ##add-imm f V int-regs 4 V int-regs 0 -150 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 100 }
+ T{ ##add-imm f V int-rep 2 V int-rep 0 -100 }
+ T{ ##load-immediate f V int-rep 3 50 }
+ T{ ##add-imm f V int-rep 4 V int-rep 0 -150 }
}
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 100 }
- T{ ##sub f V int-regs 2 V int-regs 0 V int-regs 1 }
- T{ ##load-immediate f V int-regs 3 50 }
- T{ ##sub f V int-regs 4 V int-regs 2 V int-regs 3 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 100 }
+ T{ ##sub f V int-rep 2 V int-rep 0 V int-rep 1 }
+ T{ ##load-immediate f V int-rep 3 50 }
+ T{ ##sub f V int-rep 4 V int-rep 2 V int-rep 3 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 100 }
- T{ ##mul-imm f V int-regs 2 V int-regs 0 100 }
- T{ ##load-immediate f V int-regs 3 50 }
- T{ ##mul-imm f V int-regs 4 V int-regs 0 5000 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 100 }
+ T{ ##mul-imm f V int-rep 2 V int-rep 0 100 }
+ T{ ##load-immediate f V int-rep 3 50 }
+ T{ ##mul-imm f V int-rep 4 V int-rep 0 5000 }
}
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 100 }
- T{ ##mul f V int-regs 2 V int-regs 0 V int-regs 1 }
- T{ ##load-immediate f V int-regs 3 50 }
- T{ ##mul f V int-regs 4 V int-regs 2 V int-regs 3 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 100 }
+ T{ ##mul f V int-rep 2 V int-rep 0 V int-rep 1 }
+ T{ ##load-immediate f V int-rep 3 50 }
+ T{ ##mul f V int-rep 4 V int-rep 2 V int-rep 3 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 100 }
- T{ ##mul-imm f V int-regs 2 V int-regs 0 100 }
- T{ ##load-immediate f V int-regs 3 50 }
- T{ ##mul-imm f V int-regs 4 V int-regs 0 5000 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 100 }
+ T{ ##mul-imm f V int-rep 2 V int-rep 0 100 }
+ T{ ##load-immediate f V int-rep 3 50 }
+ T{ ##mul-imm f V int-rep 4 V int-rep 0 5000 }
}
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 100 }
- T{ ##mul f V int-regs 2 V int-regs 1 V int-regs 0 }
- T{ ##load-immediate f V int-regs 3 50 }
- T{ ##mul f V int-regs 4 V int-regs 3 V int-regs 2 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 100 }
+ T{ ##mul f V int-rep 2 V int-rep 1 V int-rep 0 }
+ T{ ##load-immediate f V int-rep 3 50 }
+ T{ ##mul f V int-rep 4 V int-rep 3 V int-rep 2 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 100 }
- T{ ##and-imm f V int-regs 2 V int-regs 0 100 }
- T{ ##load-immediate f V int-regs 3 50 }
- T{ ##and-imm f V int-regs 4 V int-regs 0 32 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 100 }
+ T{ ##and-imm f V int-rep 2 V int-rep 0 100 }
+ T{ ##load-immediate f V int-rep 3 50 }
+ T{ ##and-imm f V int-rep 4 V int-rep 0 32 }
}
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 100 }
- T{ ##and f V int-regs 2 V int-regs 0 V int-regs 1 }
- T{ ##load-immediate f V int-regs 3 50 }
- T{ ##and f V int-regs 4 V int-regs 2 V int-regs 3 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 100 }
+ T{ ##and f V int-rep 2 V int-rep 0 V int-rep 1 }
+ T{ ##load-immediate f V int-rep 3 50 }
+ T{ ##and f V int-rep 4 V int-rep 2 V int-rep 3 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 100 }
- T{ ##and-imm f V int-regs 2 V int-regs 0 100 }
- T{ ##load-immediate f V int-regs 3 50 }
- T{ ##and-imm f V int-regs 4 V int-regs 0 32 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 100 }
+ T{ ##and-imm f V int-rep 2 V int-rep 0 100 }
+ T{ ##load-immediate f V int-rep 3 50 }
+ T{ ##and-imm f V int-rep 4 V int-rep 0 32 }
}
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 100 }
- T{ ##and f V int-regs 2 V int-regs 1 V int-regs 0 }
- T{ ##load-immediate f V int-regs 3 50 }
- T{ ##and f V int-regs 4 V int-regs 3 V int-regs 2 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 100 }
+ T{ ##and f V int-rep 2 V int-rep 1 V int-rep 0 }
+ T{ ##load-immediate f V int-rep 3 50 }
+ T{ ##and f V int-rep 4 V int-rep 3 V int-rep 2 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 100 }
- T{ ##or-imm f V int-regs 2 V int-regs 0 100 }
- T{ ##load-immediate f V int-regs 3 50 }
- T{ ##or-imm f V int-regs 4 V int-regs 0 118 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 100 }
+ T{ ##or-imm f V int-rep 2 V int-rep 0 100 }
+ T{ ##load-immediate f V int-rep 3 50 }
+ T{ ##or-imm f V int-rep 4 V int-rep 0 118 }
}
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 100 }
- T{ ##or f V int-regs 2 V int-regs 0 V int-regs 1 }
- T{ ##load-immediate f V int-regs 3 50 }
- T{ ##or f V int-regs 4 V int-regs 2 V int-regs 3 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 100 }
+ T{ ##or f V int-rep 2 V int-rep 0 V int-rep 1 }
+ T{ ##load-immediate f V int-rep 3 50 }
+ T{ ##or f V int-rep 4 V int-rep 2 V int-rep 3 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 100 }
- T{ ##or-imm f V int-regs 2 V int-regs 0 100 }
- T{ ##load-immediate f V int-regs 3 50 }
- T{ ##or-imm f V int-regs 4 V int-regs 0 118 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 100 }
+ T{ ##or-imm f V int-rep 2 V int-rep 0 100 }
+ T{ ##load-immediate f V int-rep 3 50 }
+ T{ ##or-imm f V int-rep 4 V int-rep 0 118 }
}
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 100 }
- T{ ##or f V int-regs 2 V int-regs 1 V int-regs 0 }
- T{ ##load-immediate f V int-regs 3 50 }
- T{ ##or f V int-regs 4 V int-regs 3 V int-regs 2 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 100 }
+ T{ ##or f V int-rep 2 V int-rep 1 V int-rep 0 }
+ T{ ##load-immediate f V int-rep 3 50 }
+ T{ ##or f V int-rep 4 V int-rep 3 V int-rep 2 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 100 }
- T{ ##xor-imm f V int-regs 2 V int-regs 0 100 }
- T{ ##load-immediate f V int-regs 3 50 }
- T{ ##xor-imm f V int-regs 4 V int-regs 0 86 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 100 }
+ T{ ##xor-imm f V int-rep 2 V int-rep 0 100 }
+ T{ ##load-immediate f V int-rep 3 50 }
+ T{ ##xor-imm f V int-rep 4 V int-rep 0 86 }
}
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 100 }
- T{ ##xor f V int-regs 2 V int-regs 0 V int-regs 1 }
- T{ ##load-immediate f V int-regs 3 50 }
- T{ ##xor f V int-regs 4 V int-regs 2 V int-regs 3 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 100 }
+ T{ ##xor f V int-rep 2 V int-rep 0 V int-rep 1 }
+ T{ ##load-immediate f V int-rep 3 50 }
+ T{ ##xor f V int-rep 4 V int-rep 2 V int-rep 3 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 100 }
- T{ ##xor-imm f V int-regs 2 V int-regs 0 100 }
- T{ ##load-immediate f V int-regs 3 50 }
- T{ ##xor-imm f V int-regs 4 V int-regs 0 86 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 100 }
+ T{ ##xor-imm f V int-rep 2 V int-rep 0 100 }
+ T{ ##load-immediate f V int-rep 3 50 }
+ T{ ##xor-imm f V int-rep 4 V int-rep 0 86 }
}
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 100 }
- T{ ##xor f V int-regs 2 V int-regs 1 V int-regs 0 }
- T{ ##load-immediate f V int-regs 3 50 }
- T{ ##xor f V int-regs 4 V int-regs 3 V int-regs 2 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 100 }
+ T{ ##xor f V int-rep 2 V int-rep 1 V int-rep 0 }
+ T{ ##load-immediate f V int-rep 3 50 }
+ T{ ##xor f V int-rep 4 V int-rep 3 V int-rep 2 }
} value-numbering-step
] unit-test
! Simplification
[
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##peek f V int-regs 1 D 1 }
- T{ ##load-immediate f V int-regs 2 0 }
- T{ ##copy f V int-regs 3 V int-regs 0 }
- T{ ##replace f V int-regs 3 D 0 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##peek f V int-rep 1 D 1 }
+ T{ ##load-immediate f V int-rep 2 0 }
+ T{ ##copy f V int-rep 3 V int-rep 0 int-rep }
+ T{ ##replace f V int-rep 3 D 0 }
}
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##peek f V int-regs 1 D 1 }
- T{ ##sub f V int-regs 2 V int-regs 1 V int-regs 1 }
- T{ ##add f V int-regs 3 V int-regs 0 V int-regs 2 }
- T{ ##replace f V int-regs 3 D 0 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##peek f V int-rep 1 D 1 }
+ T{ ##sub f V int-rep 2 V int-rep 1 V int-rep 1 }
+ T{ ##add f V int-rep 3 V int-rep 0 V int-rep 2 }
+ T{ ##replace f V int-rep 3 D 0 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##peek f V int-regs 1 D 1 }
- T{ ##load-immediate f V int-regs 2 0 }
- T{ ##copy f V int-regs 3 V int-regs 0 }
- T{ ##replace f V int-regs 3 D 0 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##peek f V int-rep 1 D 1 }
+ T{ ##load-immediate f V int-rep 2 0 }
+ T{ ##copy f V int-rep 3 V int-rep 0 int-rep }
+ T{ ##replace f V int-rep 3 D 0 }
}
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##peek f V int-regs 1 D 1 }
- T{ ##sub f V int-regs 2 V int-regs 1 V int-regs 1 }
- T{ ##sub f V int-regs 3 V int-regs 0 V int-regs 2 }
- T{ ##replace f V int-regs 3 D 0 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##peek f V int-rep 1 D 1 }
+ T{ ##sub f V int-rep 2 V int-rep 1 V int-rep 1 }
+ T{ ##sub f V int-rep 3 V int-rep 0 V int-rep 2 }
+ T{ ##replace f V int-rep 3 D 0 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##peek f V int-regs 1 D 1 }
- T{ ##load-immediate f V int-regs 2 0 }
- T{ ##copy f V int-regs 3 V int-regs 0 }
- T{ ##replace f V int-regs 3 D 0 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##peek f V int-rep 1 D 1 }
+ T{ ##load-immediate f V int-rep 2 0 }
+ T{ ##copy f V int-rep 3 V int-rep 0 int-rep }
+ T{ ##replace f V int-rep 3 D 0 }
}
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##peek f V int-regs 1 D 1 }
- T{ ##sub f V int-regs 2 V int-regs 1 V int-regs 1 }
- T{ ##or f V int-regs 3 V int-regs 0 V int-regs 2 }
- T{ ##replace f V int-regs 3 D 0 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##peek f V int-rep 1 D 1 }
+ T{ ##sub f V int-rep 2 V int-rep 1 V int-rep 1 }
+ T{ ##or f V int-rep 3 V int-rep 0 V int-rep 2 }
+ T{ ##replace f V int-rep 3 D 0 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##peek f V int-regs 1 D 1 }
- T{ ##load-immediate f V int-regs 2 0 }
- T{ ##copy f V int-regs 3 V int-regs 0 }
- T{ ##replace f V int-regs 3 D 0 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##peek f V int-rep 1 D 1 }
+ T{ ##load-immediate f V int-rep 2 0 }
+ T{ ##copy f V int-rep 3 V int-rep 0 int-rep }
+ T{ ##replace f V int-rep 3 D 0 }
}
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##peek f V int-regs 1 D 1 }
- T{ ##sub f V int-regs 2 V int-regs 1 V int-regs 1 }
- T{ ##xor f V int-regs 3 V int-regs 0 V int-regs 2 }
- T{ ##replace f V int-regs 3 D 0 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##peek f V int-rep 1 D 1 }
+ T{ ##sub f V int-rep 2 V int-rep 1 V int-rep 1 }
+ T{ ##xor f V int-rep 3 V int-rep 0 V int-rep 2 }
+ T{ ##replace f V int-rep 3 D 0 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 1 }
- T{ ##copy f V int-regs 2 V int-regs 0 }
- T{ ##replace f V int-regs 2 D 0 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 1 }
+ T{ ##copy f V int-rep 2 V int-rep 0 int-rep }
+ T{ ##replace f V int-rep 2 D 0 }
}
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 1 }
- T{ ##mul f V int-regs 2 V int-regs 0 V int-regs 1 }
- T{ ##replace f V int-regs 2 D 0 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 1 }
+ T{ ##mul f V int-rep 2 V int-rep 0 V int-rep 1 }
+ T{ ##replace f V int-rep 2 D 0 }
} value-numbering-step
] unit-test
! Constant folding
[
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 1 }
- T{ ##load-immediate f V int-regs 2 3 }
- T{ ##load-immediate f V int-regs 3 4 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 1 }
+ T{ ##load-immediate f V int-rep 2 3 }
+ T{ ##load-immediate f V int-rep 3 4 }
}
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 1 }
- T{ ##load-immediate f V int-regs 2 3 }
- T{ ##add f V int-regs 3 V int-regs 1 V int-regs 2 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 1 }
+ T{ ##load-immediate f V int-rep 2 3 }
+ T{ ##add f V int-rep 3 V int-rep 1 V int-rep 2 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 1 }
- T{ ##load-immediate f V int-regs 2 3 }
- T{ ##load-immediate f V int-regs 3 -2 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 1 }
+ T{ ##load-immediate f V int-rep 2 3 }
+ T{ ##load-immediate f V int-rep 3 -2 }
}
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 1 }
- T{ ##load-immediate f V int-regs 2 3 }
- T{ ##sub f V int-regs 3 V int-regs 1 V int-regs 2 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 1 }
+ T{ ##load-immediate f V int-rep 2 3 }
+ T{ ##sub f V int-rep 3 V int-rep 1 V int-rep 2 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 2 }
- T{ ##load-immediate f V int-regs 2 3 }
- T{ ##load-immediate f V int-regs 3 6 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 2 }
+ T{ ##load-immediate f V int-rep 2 3 }
+ T{ ##load-immediate f V int-rep 3 6 }
}
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 2 }
- T{ ##load-immediate f V int-regs 2 3 }
- T{ ##mul f V int-regs 3 V int-regs 1 V int-regs 2 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 2 }
+ T{ ##load-immediate f V int-rep 2 3 }
+ T{ ##mul f V int-rep 3 V int-rep 1 V int-rep 2 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 2 }
- T{ ##load-immediate f V int-regs 2 1 }
- T{ ##load-immediate f V int-regs 3 0 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 2 }
+ T{ ##load-immediate f V int-rep 2 1 }
+ T{ ##load-immediate f V int-rep 3 0 }
}
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 2 }
- T{ ##load-immediate f V int-regs 2 1 }
- T{ ##and f V int-regs 3 V int-regs 1 V int-regs 2 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 2 }
+ T{ ##load-immediate f V int-rep 2 1 }
+ T{ ##and f V int-rep 3 V int-rep 1 V int-rep 2 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 2 }
- T{ ##load-immediate f V int-regs 2 1 }
- T{ ##load-immediate f V int-regs 3 3 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 2 }
+ T{ ##load-immediate f V int-rep 2 1 }
+ T{ ##load-immediate f V int-rep 3 3 }
}
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 2 }
- T{ ##load-immediate f V int-regs 2 1 }
- T{ ##or f V int-regs 3 V int-regs 1 V int-regs 2 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 2 }
+ T{ ##load-immediate f V int-rep 2 1 }
+ T{ ##or f V int-rep 3 V int-rep 1 V int-rep 2 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 2 }
- T{ ##load-immediate f V int-regs 2 3 }
- T{ ##load-immediate f V int-regs 3 1 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 2 }
+ T{ ##load-immediate f V int-rep 2 3 }
+ T{ ##load-immediate f V int-rep 3 1 }
}
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 2 }
- T{ ##load-immediate f V int-regs 2 3 }
- T{ ##xor f V int-regs 3 V int-regs 1 V int-regs 2 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 2 }
+ T{ ##load-immediate f V int-rep 2 3 }
+ T{ ##xor f V int-rep 3 V int-rep 1 V int-rep 2 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 1 }
- T{ ##load-immediate f V int-regs 3 8 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 1 }
+ T{ ##load-immediate f V int-rep 3 8 }
}
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 1 }
- T{ ##shl-imm f V int-regs 3 V int-regs 1 3 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 1 }
+ T{ ##shl-imm f V int-rep 3 V int-rep 1 3 }
} value-numbering-step
] unit-test
cell 8 = [
[
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 -1 }
- T{ ##load-immediate f V int-regs 3 HEX: ffffffffffff }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 -1 }
+ T{ ##load-immediate f V int-rep 3 HEX: ffffffffffff }
}
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 -1 }
- T{ ##shr-imm f V int-regs 3 V int-regs 1 16 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 -1 }
+ T{ ##shr-imm f V int-rep 3 V int-rep 1 16 }
} value-numbering-step
] unit-test
] when
[
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 -8 }
- T{ ##load-immediate f V int-regs 3 -4 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 -8 }
+ T{ ##load-immediate f V int-rep 3 -4 }
}
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 -8 }
- T{ ##sar-imm f V int-regs 3 V int-regs 1 1 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 -8 }
+ T{ ##sar-imm f V int-rep 3 V int-rep 1 1 }
} value-numbering-step
] unit-test
cell 8 = [
[
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 65536 }
- T{ ##load-immediate f V int-regs 2 140737488355328 }
- T{ ##add f V int-regs 3 V int-regs 0 V int-regs 2 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 65536 }
+ T{ ##load-immediate f V int-rep 2 140737488355328 }
+ T{ ##add f V int-rep 3 V int-rep 0 V int-rep 2 }
}
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 65536 }
- T{ ##shl-imm f V int-regs 2 V int-regs 1 31 }
- T{ ##add f V int-regs 3 V int-regs 0 V int-regs 2 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 65536 }
+ T{ ##shl-imm f V int-rep 2 V int-rep 1 31 }
+ T{ ##add f V int-rep 3 V int-rep 0 V int-rep 2 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 2 140737488355328 }
- T{ ##add f V int-regs 3 V int-regs 0 V int-regs 2 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 2 140737488355328 }
+ T{ ##add f V int-rep 3 V int-rep 0 V int-rep 2 }
}
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 2 140737488355328 }
- T{ ##add f V int-regs 3 V int-regs 0 V int-regs 2 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 2 140737488355328 }
+ T{ ##add f V int-rep 3 V int-rep 0 V int-rep 2 }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 2 2147483647 }
- T{ ##add-imm f V int-regs 3 V int-regs 0 2147483647 }
- T{ ##add-imm f V int-regs 4 V int-regs 3 2147483647 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 2 2147483647 }
+ T{ ##add-imm f V int-rep 3 V int-rep 0 2147483647 }
+ T{ ##add-imm f V int-rep 4 V int-rep 3 2147483647 }
}
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 2 2147483647 }
- T{ ##add f V int-regs 3 V int-regs 0 V int-regs 2 }
- T{ ##add f V int-regs 4 V int-regs 3 V int-regs 2 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 2 2147483647 }
+ T{ ##add f V int-rep 3 V int-rep 0 V int-rep 2 }
+ T{ ##add f V int-rep 4 V int-rep 3 V int-rep 2 }
} value-numbering-step
] unit-test
] when
! Branch folding
[
{
- T{ ##load-immediate f V int-regs 1 1 }
- T{ ##load-immediate f V int-regs 2 2 }
- T{ ##load-immediate f V int-regs 3 5 }
+ T{ ##load-immediate f V int-rep 1 1 }
+ T{ ##load-immediate f V int-rep 2 2 }
+ T{ ##load-immediate f V int-rep 3 5 }
}
] [
{
- T{ ##load-immediate f V int-regs 1 1 }
- T{ ##load-immediate f V int-regs 2 2 }
- T{ ##compare f V int-regs 3 V int-regs 1 V int-regs 2 cc= }
+ T{ ##load-immediate f V int-rep 1 1 }
+ T{ ##load-immediate f V int-rep 2 2 }
+ T{ ##compare f V int-rep 3 V int-rep 1 V int-rep 2 cc= }
} value-numbering-step
] unit-test
[
{
- T{ ##load-immediate f V int-regs 1 1 }
- T{ ##load-immediate f V int-regs 2 2 }
- T{ ##load-reference f V int-regs 3 t }
+ T{ ##load-immediate f V int-rep 1 1 }
+ T{ ##load-immediate f V int-rep 2 2 }
+ T{ ##load-reference f V int-rep 3 t }
}
] [
{
- T{ ##load-immediate f V int-regs 1 1 }
- T{ ##load-immediate f V int-regs 2 2 }
- T{ ##compare f V int-regs 3 V int-regs 1 V int-regs 2 cc/= }
+ T{ ##load-immediate f V int-rep 1 1 }
+ T{ ##load-immediate f V int-rep 2 2 }
+ T{ ##compare f V int-rep 3 V int-rep 1 V int-rep 2 cc/= }
} value-numbering-step
] unit-test
[
{
- T{ ##load-immediate f V int-regs 1 1 }
- T{ ##load-immediate f V int-regs 2 2 }
- T{ ##load-reference f V int-regs 3 t }
+ T{ ##load-immediate f V int-rep 1 1 }
+ T{ ##load-immediate f V int-rep 2 2 }
+ T{ ##load-reference f V int-rep 3 t }
}
] [
{
- T{ ##load-immediate f V int-regs 1 1 }
- T{ ##load-immediate f V int-regs 2 2 }
- T{ ##compare f V int-regs 3 V int-regs 1 V int-regs 2 cc< }
+ T{ ##load-immediate f V int-rep 1 1 }
+ T{ ##load-immediate f V int-rep 2 2 }
+ T{ ##compare f V int-rep 3 V int-rep 1 V int-rep 2 cc< }
} value-numbering-step
] unit-test
[
{
- T{ ##load-immediate f V int-regs 1 1 }
- T{ ##load-immediate f V int-regs 2 2 }
- T{ ##load-immediate f V int-regs 3 5 }
+ T{ ##load-immediate f V int-rep 1 1 }
+ T{ ##load-immediate f V int-rep 2 2 }
+ T{ ##load-immediate f V int-rep 3 5 }
}
] [
{
- T{ ##load-immediate f V int-regs 1 1 }
- T{ ##load-immediate f V int-regs 2 2 }
- T{ ##compare f V int-regs 3 V int-regs 2 V int-regs 1 cc< }
+ T{ ##load-immediate f V int-rep 1 1 }
+ T{ ##load-immediate f V int-rep 2 2 }
+ T{ ##compare f V int-rep 3 V int-rep 2 V int-rep 1 cc< }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 5 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 5 }
}
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##compare f V int-regs 1 V int-regs 0 V int-regs 0 cc< }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##compare f V int-rep 1 V int-rep 0 V int-rep 0 cc< }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-reference f V int-regs 1 t }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-reference f V int-rep 1 t }
}
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##compare f V int-regs 1 V int-regs 0 V int-regs 0 cc<= }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##compare f V int-rep 1 V int-rep 0 V int-rep 0 cc<= }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 5 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 5 }
}
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##compare f V int-regs 1 V int-regs 0 V int-regs 0 cc> }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##compare f V int-rep 1 V int-rep 0 V int-rep 0 cc> }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-reference f V int-regs 1 t }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-reference f V int-rep 1 t }
}
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##compare f V int-regs 1 V int-regs 0 V int-regs 0 cc>= }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##compare f V int-rep 1 V int-rep 0 V int-rep 0 cc>= }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-immediate f V int-regs 1 5 }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-immediate f V int-rep 1 5 }
}
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##compare f V int-regs 1 V int-regs 0 V int-regs 0 cc/= }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##compare f V int-rep 1 V int-rep 0 V int-rep 0 cc/= }
} value-numbering-step
] unit-test
[
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-reference f V int-regs 1 t }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-reference f V int-rep 1 t }
}
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##compare f V int-regs 1 V int-regs 0 V int-regs 0 cc= }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##compare f V int-rep 1 V int-rep 0 V int-rep 0 cc= }
} value-numbering-step
] unit-test
[
{
- T{ ##load-immediate f V int-regs 1 1 }
- T{ ##load-immediate f V int-regs 2 2 }
+ T{ ##load-immediate f V int-rep 1 1 }
+ T{ ##load-immediate f V int-rep 2 2 }
T{ ##branch }
}
1
] [
{
- T{ ##load-immediate f V int-regs 1 1 }
- T{ ##load-immediate f V int-regs 2 2 }
- T{ ##compare-branch f V int-regs 1 V int-regs 2 cc= }
+ T{ ##load-immediate f V int-rep 1 1 }
+ T{ ##load-immediate f V int-rep 2 2 }
+ T{ ##compare-branch f V int-rep 1 V int-rep 2 cc= }
} test-branch-folding
] unit-test
[
{
- T{ ##load-immediate f V int-regs 1 1 }
- T{ ##load-immediate f V int-regs 2 2 }
+ T{ ##load-immediate f V int-rep 1 1 }
+ T{ ##load-immediate f V int-rep 2 2 }
T{ ##branch }
}
0
] [
{
- T{ ##load-immediate f V int-regs 1 1 }
- T{ ##load-immediate f V int-regs 2 2 }
- T{ ##compare-branch f V int-regs 1 V int-regs 2 cc/= }
+ T{ ##load-immediate f V int-rep 1 1 }
+ T{ ##load-immediate f V int-rep 2 2 }
+ T{ ##compare-branch f V int-rep 1 V int-rep 2 cc/= }
} test-branch-folding
] unit-test
[
{
- T{ ##load-immediate f V int-regs 1 1 }
- T{ ##load-immediate f V int-regs 2 2 }
+ T{ ##load-immediate f V int-rep 1 1 }
+ T{ ##load-immediate f V int-rep 2 2 }
T{ ##branch }
}
0
] [
{
- T{ ##load-immediate f V int-regs 1 1 }
- T{ ##load-immediate f V int-regs 2 2 }
- T{ ##compare-branch f V int-regs 1 V int-regs 2 cc< }
+ T{ ##load-immediate f V int-rep 1 1 }
+ T{ ##load-immediate f V int-rep 2 2 }
+ T{ ##compare-branch f V int-rep 1 V int-rep 2 cc< }
} test-branch-folding
] unit-test
[
{
- T{ ##load-immediate f V int-regs 1 1 }
- T{ ##load-immediate f V int-regs 2 2 }
+ T{ ##load-immediate f V int-rep 1 1 }
+ T{ ##load-immediate f V int-rep 2 2 }
T{ ##branch }
}
1
] [
{
- T{ ##load-immediate f V int-regs 1 1 }
- T{ ##load-immediate f V int-regs 2 2 }
- T{ ##compare-branch f V int-regs 2 V int-regs 1 cc< }
+ T{ ##load-immediate f V int-rep 1 1 }
+ T{ ##load-immediate f V int-rep 2 2 }
+ T{ ##compare-branch f V int-rep 2 V int-rep 1 cc< }
} test-branch-folding
] unit-test
[
{
- T{ ##peek f V int-regs 0 D 0 }
+ T{ ##peek f V int-rep 0 D 0 }
T{ ##branch }
}
1
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##compare-branch f V int-regs 0 V int-regs 0 cc< }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##compare-branch f V int-rep 0 V int-rep 0 cc< }
} test-branch-folding
] unit-test
[
{
- T{ ##peek f V int-regs 0 D 0 }
+ T{ ##peek f V int-rep 0 D 0 }
T{ ##branch }
}
0
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##compare-branch f V int-regs 0 V int-regs 0 cc<= }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##compare-branch f V int-rep 0 V int-rep 0 cc<= }
} test-branch-folding
] unit-test
[
{
- T{ ##peek f V int-regs 0 D 0 }
+ T{ ##peek f V int-rep 0 D 0 }
T{ ##branch }
}
1
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##compare-branch f V int-regs 0 V int-regs 0 cc> }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##compare-branch f V int-rep 0 V int-rep 0 cc> }
} test-branch-folding
] unit-test
[
{
- T{ ##peek f V int-regs 0 D 0 }
+ T{ ##peek f V int-rep 0 D 0 }
T{ ##branch }
}
0
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##compare-branch f V int-regs 0 V int-regs 0 cc>= }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##compare-branch f V int-rep 0 V int-rep 0 cc>= }
} test-branch-folding
] unit-test
[
{
- T{ ##peek f V int-regs 0 D 0 }
+ T{ ##peek f V int-rep 0 D 0 }
T{ ##branch }
}
0
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##compare-branch f V int-regs 0 V int-regs 0 cc= }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##compare-branch f V int-rep 0 V int-rep 0 cc= }
} test-branch-folding
] unit-test
[
{
- T{ ##peek f V int-regs 0 D 0 }
+ T{ ##peek f V int-rep 0 D 0 }
T{ ##branch }
}
1
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##compare-branch f V int-regs 0 V int-regs 0 cc/= }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##compare-branch f V int-rep 0 V int-rep 0 cc/= }
} test-branch-folding
] unit-test
[
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##load-reference f V int-regs 1 t }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##load-reference f V int-rep 1 t }
T{ ##branch }
}
0
] [
{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##compare f V int-regs 1 V int-regs 0 V int-regs 0 cc<= }
- T{ ##compare-imm-branch f V int-regs 1 5 cc/= }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##compare f V int-rep 1 V int-rep 0 V int-rep 0 cc<= }
+ T{ ##compare-imm-branch f V int-rep 1 5 cc/= }
} test-branch-folding
] unit-test
V{ T{ ##branch } } 0 test-bb
V{
- T{ ##peek f V int-regs 0 D 0 }
- T{ ##compare-branch f V int-regs 0 V int-regs 0 cc< }
+ T{ ##peek f V int-rep 0 D 0 }
+ T{ ##compare-branch f V int-rep 0 V int-rep 0 cc< }
} 1 test-bb
V{
- T{ ##load-immediate f V int-regs 1 1 }
+ T{ ##load-immediate f V int-rep 1 1 }
T{ ##branch }
} 2 test-bb
V{
- T{ ##load-immediate f V int-regs 2 2 }
+ T{ ##load-immediate f V int-rep 2 2 }
T{ ##branch }
} 3 test-bb
V{
- T{ ##phi f V int-regs 3 H{ { 2 V int-regs 1 } { 3 V int-regs 2 } } }
- T{ ##replace f V int-regs 3 D 0 }
+ T{ ##phi f V int-rep 3 H{ { 2 V int-rep 1 } { 3 V int-rep 2 } } }
+ T{ ##replace f V int-rep 3 D 0 }
T{ ##return }
} 4 test-bb
[ 2 ] [ 4 get instructions>> length ] unit-test
V{
- T{ ##peek f V int-regs 0 D 0 }
+ T{ ##peek f V int-rep 0 D 0 }
T{ ##branch }
} 0 test-bb
V{
- T{ ##peek f V int-regs 1 D 1 }
- T{ ##compare-branch f V int-regs 1 V int-regs 1 cc< }
+ T{ ##peek f V int-rep 1 D 1 }
+ T{ ##compare-branch f V int-rep 1 V int-rep 1 cc< }
} 1 test-bb
V{
- T{ ##copy f V int-regs 2 V int-regs 0 }
+ T{ ##copy f V int-rep 2 V int-rep 0 int-rep }
T{ ##branch }
} 2 test-bb
V{
- T{ ##phi f V int-regs 3 V{ } }
+ T{ ##phi f V int-rep 3 V{ } }
T{ ##branch }
} 3 test-bb
V{
- T{ ##replace f V int-regs 3 D 0 }
+ T{ ##replace f V int-rep 3 D 0 }
T{ ##return }
} 4 test-bb
-1 get V int-regs 1 2array
-2 get V int-regs 0 2array 2array 3 get instructions>> first (>>inputs)
+1 get V int-rep 1 2array
+2 get V int-rep 0 2array 2array 3 get instructions>> first (>>inputs)
test-diamond
V{ T{ ##prologue } T{ ##branch } } 0 test-bb
V{
- T{ ##peek { dst V int-regs 15 } { loc D 0 } }
- T{ ##copy { dst V int-regs 16 } { src V int-regs 15 } }
- T{ ##copy { dst V int-regs 17 } { src V int-regs 15 } }
- T{ ##copy { dst V int-regs 18 } { src V int-regs 15 } }
- T{ ##copy { dst V int-regs 19 } { src V int-regs 15 } }
+ T{ ##peek { dst V int-rep 15 } { loc D 0 } }
+ T{ ##copy { dst V int-rep 16 } { src V int-rep 15 } { rep int-rep } }
+ T{ ##copy { dst V int-rep 17 } { src V int-rep 15 } { rep int-rep } }
+ T{ ##copy { dst V int-rep 18 } { src V int-rep 15 } { rep int-rep } }
+ T{ ##copy { dst V int-rep 19 } { src V int-rep 15 } { rep int-rep } }
T{ ##compare
- { dst V int-regs 20 }
- { src1 V int-regs 18 }
- { src2 V int-regs 19 }
+ { dst V int-rep 20 }
+ { src1 V int-rep 18 }
+ { src2 V int-rep 19 }
{ cc cc= }
- { temp V int-regs 22 }
+ { temp V int-rep 22 }
}
- T{ ##copy { dst V int-regs 21 } { src V int-regs 20 } }
+ T{ ##copy { dst V int-rep 21 } { src V int-rep 20 } { rep int-rep } }
T{ ##compare-imm-branch
- { src1 V int-regs 21 }
+ { src1 V int-rep 21 }
{ src2 5 }
{ cc cc/= }
}
} 1 test-bb
V{
- T{ ##copy { dst V int-regs 23 } { src V int-regs 15 } }
- T{ ##copy { dst V int-regs 24 } { src V int-regs 15 } }
- T{ ##load-reference { dst V int-regs 25 } { obj t } }
+ T{ ##copy { dst V int-rep 23 } { src V int-rep 15 } { rep int-rep } }
+ T{ ##copy { dst V int-rep 24 } { src V int-rep 15 } { rep int-rep } }
+ T{ ##load-reference { dst V int-rep 25 } { obj t } }
T{ ##branch }
} 2 test-bb
V{
- T{ ##replace { src V int-regs 25 } { loc D 0 } }
+ T{ ##replace { src V int-rep 25 } { loc D 0 } }
T{ ##epilogue }
T{ ##return }
} 3 test-bb
V{
- T{ ##copy { dst V int-regs 26 } { src V int-regs 15 } }
- T{ ##copy { dst V int-regs 27 } { src V int-regs 15 } }
+ T{ ##copy { dst V int-rep 26 } { src V int-rep 15 } { rep int-rep } }
+ T{ ##copy { dst V int-rep 27 } { src V int-rep 15 } { rep int-rep } }
T{ ##add
- { dst V int-regs 28 }
- { src1 V int-regs 26 }
- { src2 V int-regs 27 }
+ { dst V int-rep 28 }
+ { src1 V int-rep 26 }
+ { src2 V int-rep 27 }
}
T{ ##branch }
} 4 test-bb
V{
- T{ ##replace { src V int-regs 28 } { loc D 0 } }
+ T{ ##replace { src V int-rep 28 } { loc D 0 } }
T{ ##epilogue }
T{ ##return }
} 5 test-bb
! Local value numbering. Predecessors must be recomputed after this
: >copy ( insn -- insn/##copy )
dup dst>> dup vreg>vn vn>vreg
- 2dup eq? [ 2drop ] [ \ ##copy new-insn nip ] if ;
+ 2dup eq? [ 2drop ] [ dup rep>> \ ##copy new-insn nip ] if ;
: rewrite-loop ( insn -- insn' )
dup rewrite [ rewrite-loop ] [ ] ?if ;
M: ##integer>float generate-insn dst/src %integer>float ;
M: ##float>integer generate-insn dst/src %float>integer ;
-M: ##copy generate-insn dst/src %copy ;
-M: ##copy-float generate-insn dst/src %copy-float ;
-M: ##unbox-float generate-insn dst/src %unbox-float ;
-M: ##unbox-any-c-ptr generate-insn dst/src/temp %unbox-any-c-ptr ;
-M: ##box-float generate-insn dst/src/temp %box-float ;
-M: ##box-alien generate-insn dst/src/temp %box-alien ;
+M: ##copy generate-insn [ dst/src ] [ rep>> ] bi %copy ;
+
+M: ##unbox-float generate-insn dst/src %unbox-float ;
+M: ##unbox-any-c-ptr generate-insn dst/src/temp %unbox-any-c-ptr ;
+M: ##box-float generate-insn dst/src/temp %box-float ;
+M: ##box-alien generate-insn dst/src/temp %box-alien ;
M: ##alien-unsigned-1 generate-insn dst/src %alien-unsigned-1 ;
M: ##alien-unsigned-2 generate-insn dst/src %alien-unsigned-2 ;
GENERIC# save-gc-root 1 ( gc-root operand temp -- )
M:: spill-slot save-gc-root ( gc-root operand temp -- )
- temp operand n>> %reload-integer
+ temp operand n>> int-rep %reload
gc-root temp %save-gc-root ;
M: object save-gc-root drop %save-gc-root ;
: save-gc-roots ( gc-roots temp -- ) '[ _ save-gc-root ] assoc-each ;
+: save-data-regs ( data-regs -- ) [ first3 %spill ] each ;
+
GENERIC# load-gc-root 1 ( gc-root operand temp -- )
M:: spill-slot load-gc-root ( gc-root operand temp -- )
gc-root temp %load-gc-root
- temp operand n>> %spill-integer ;
+ temp operand n>> int-rep %spill ;
M: object load-gc-root drop %load-gc-root ;
: load-gc-roots ( gc-roots temp -- ) '[ _ load-gc-root ] assoc-each ;
+: load-data-regs ( data-regs -- ) [ first3 %reload ] each ;
+
M: _gc generate-insn
"no-gc" define-label
{
[ [ "no-gc" get ] dip [ temp1>> ] [ temp2>> ] bi %check-nursery ]
[ [ uninitialized-locs>> ] [ temp1>> ] bi wipe-locs ]
- [ [ gc-roots>> ] [ temp1>> ] bi save-gc-roots ]
- [ gc-root-count>> %call-gc ]
- [ [ gc-roots>> ] [ temp1>> ] bi load-gc-roots ]
+ [ data-values>> save-data-regs ]
+ [ [ tagged-values>> ] [ temp1>> ] bi save-gc-roots ]
+ [ gc-root-size>> %call-gc ]
+ [ [ tagged-values>> ] [ temp1>> ] bi load-gc-roots ]
+ [ data-values>> load-data-regs ]
} cleave
"no-gc" resolve-label ;
%alien-global ;
! ##alien-invoke
-GENERIC: reg-class-variable ( register-class -- symbol )
-
-M: reg-class reg-class-variable ;
-
-M: float-regs reg-class-variable drop float-regs ;
+GENERIC: next-fastcall-param ( reg-class -- )
-GENERIC: inc-reg-class ( register-class -- )
+: ?dummy-stack-params ( rep -- )
+ dummy-stack-params? [ rep-size cell align stack-params +@ ] [ drop ] if ;
-: ?dummy-stack-params ( reg-class -- )
- dummy-stack-params? [ reg-size cell align stack-params +@ ] [ drop ] if ;
+: ?dummy-int-params ( rep -- )
+ dummy-int-params? [ rep-size cell /i 1 max int-regs +@ ] [ drop ] if ;
-: ?dummy-int-params ( reg-class -- )
- dummy-int-params? [ reg-size cell /i 1 max int-regs +@ ] [ drop ] if ;
-
-: ?dummy-fp-params ( reg-class -- )
+: ?dummy-fp-params ( rep -- )
drop dummy-fp-params? [ float-regs inc ] when ;
-M: int-regs inc-reg-class
- [ reg-class-variable inc ]
- [ ?dummy-stack-params ]
- [ ?dummy-fp-params ]
- tri ;
+M: int-rep next-fastcall-param
+ int-regs inc [ ?dummy-stack-params ] [ ?dummy-fp-params ] bi ;
-M: float-regs inc-reg-class
- [ reg-class-variable inc ]
- [ ?dummy-stack-params ]
- [ ?dummy-int-params ]
- tri ;
+M: single-float-rep next-fastcall-param
+ float-regs inc [ ?dummy-stack-params ] [ ?dummy-int-params ] bi ;
-GENERIC: reg-class-full? ( class -- ? )
+M: double-float-rep next-fastcall-param
+ float-regs inc [ ?dummy-stack-params ] [ ?dummy-int-params ] bi ;
+
+GENERIC: reg-class-full? ( reg-class -- ? )
M: stack-params reg-class-full? drop t ;
-M: object reg-class-full?
- [ reg-class-variable get ] [ param-regs length ] bi >= ;
+M: reg-class reg-class-full?
+ [ get ] [ param-regs length ] bi >= ;
-: spill-param ( reg-class -- n reg-class )
+: alloc-stack-param ( rep -- n reg-class rep )
stack-params get
- [ reg-size cell align stack-params +@ ] dip
- stack-params ;
+ [ rep-size cell align stack-params +@ ] dip
+ stack-params dup ;
-: fastcall-param ( reg-class -- n reg-class )
- [ reg-class-variable get ] [ inc-reg-class ] [ ] tri ;
+: alloc-fastcall-param ( rep -- n reg-class rep )
+ [ reg-class-of [ get ] [ inc ] [ ] tri ] keep ;
-: alloc-parameter ( parameter -- reg reg-class )
- c-type-reg-class dup reg-class-full?
- [ spill-param ] [ fastcall-param ] if
- [ param-reg ] keep ;
+: alloc-parameter ( parameter -- reg rep )
+ c-type-rep dup reg-class-of reg-class-full?
+ [ alloc-stack-param ] [ alloc-fastcall-param ] if
+ [ param-reg ] dip ;
: (flatten-int-type) ( size -- seq )
cell /i "void*" c-type <repetition> ;
: reverse-each-parameter ( parameters quot -- )
[ [ parameter-sizes nip ] keep ] dip 2reverse-each ; inline
-: reset-freg-counts ( -- )
+: reset-fastcall-counts ( -- )
{ int-regs float-regs stack-params } [ 0 swap set ] each ;
: with-param-regs ( quot -- )
#! In quot you can call alloc-parameter
- [ reset-freg-counts call ] with-scope ; inline
+ [ reset-fastcall-counts call ] with-scope ; inline
: move-parameters ( node word -- )
#! Moves values from C stack to registers (if word is
alien-parameters [ box-parameter ] each-parameter ;
: registers>objects ( node -- )
+ ! Generate code for boxing input parameters in a callback.
[
dup \ %save-param-reg move-parameters
"nest_stacks" f %alien-invoke
>binary-branch< %compare-float-branch ;
M: _spill generate-insn
- [ src>> ] [ n>> ] [ class>> ] tri {
- { int-regs [ %spill-integer ] }
- { double-float-regs [ %spill-float ] }
- } case ;
+ [ src>> ] [ n>> ] [ rep>> ] tri %spill ;
M: _reload generate-insn
- [ dst>> ] [ n>> ] [ class>> ] tri {
- { int-regs [ %reload-integer ] }
- { double-float-regs [ %reload-float ] }
- } case ;
-
-M: _copy generate-insn
- [ dst>> ] [ src>> ] [ class>> ] tri {
- { int-regs [ %copy ] }
- { double-float-regs [ %copy-float ] }
- } case ;
-
-M: _spill-counts generate-insn drop ;
+ [ dst>> ] [ n>> ] [ rep>> ] tri %reload ;
+
+M: _spill-area-size generate-insn drop ;
V{ T{ ##prologue } T{ ##branch } } 0 test-bb
V{
T{ ##inc-d f 1 }
- T{ ##replace f V int-regs 0 D 0 }
+ T{ ##replace f V int-rep 0 D 0 }
T{ ##branch }
} [ clone ] map append 1 test-bb
V{
! loading immediates
[ f ] [
V{
- T{ ##load-immediate f V int-regs 0 5 }
+ T{ ##load-immediate f V int-rep 0 5 }
} compile-test-bb
] unit-test
[ "hello" ] [
V{
- T{ ##load-reference f V int-regs 0 "hello" }
+ T{ ##load-reference f V int-rep 0 "hello" }
} compile-test-bb
] unit-test
! one of the sources
[ t ] [
V{
- T{ ##load-immediate f V int-regs 1 $[ 2 cell log2 shift ] }
- T{ ##load-reference f V int-regs 0 { t f t } }
- T{ ##slot f V int-regs 0 V int-regs 0 V int-regs 1 $[ array tag-number ] V int-regs 2 }
+ T{ ##load-immediate f V int-rep 1 $[ 2 cell log2 shift ] }
+ T{ ##load-reference f V int-rep 0 { t f t } }
+ T{ ##slot f V int-rep 0 V int-rep 0 V int-rep 1 $[ array tag-number ] V int-rep 2 }
} compile-test-bb
] unit-test
[ t ] [
V{
- T{ ##load-reference f V int-regs 0 { t f t } }
- T{ ##slot-imm f V int-regs 0 V int-regs 0 2 $[ array tag-number ] V int-regs 2 }
+ T{ ##load-reference f V int-rep 0 { t f t } }
+ T{ ##slot-imm f V int-rep 0 V int-rep 0 2 $[ array tag-number ] V int-rep 2 }
} compile-test-bb
] unit-test
[ t ] [
V{
- T{ ##load-immediate f V int-regs 1 $[ 2 cell log2 shift ] }
- T{ ##load-reference f V int-regs 0 { t f t } }
- T{ ##set-slot f V int-regs 0 V int-regs 0 V int-regs 1 $[ array tag-number ] V int-regs 2 }
+ T{ ##load-immediate f V int-rep 1 $[ 2 cell log2 shift ] }
+ T{ ##load-reference f V int-rep 0 { t f t } }
+ T{ ##set-slot f V int-rep 0 V int-rep 0 V int-rep 1 $[ array tag-number ] V int-rep 2 }
} compile-test-bb
dup first eq?
] unit-test
[ t ] [
V{
- T{ ##load-reference f V int-regs 0 { t f t } }
- T{ ##set-slot-imm f V int-regs 0 V int-regs 0 2 $[ array tag-number ] }
+ T{ ##load-reference f V int-rep 0 { t f t } }
+ T{ ##set-slot-imm f V int-rep 0 V int-rep 0 2 $[ array tag-number ] }
} compile-test-bb
dup first eq?
] unit-test
[ 8 ] [
V{
- T{ ##load-immediate f V int-regs 0 4 }
- T{ ##shl f V int-regs 0 V int-regs 0 V int-regs 0 }
+ T{ ##load-immediate f V int-rep 0 4 }
+ T{ ##shl f V int-rep 0 V int-rep 0 V int-rep 0 }
} compile-test-bb
] unit-test
[ 4 ] [
V{
- T{ ##load-immediate f V int-regs 0 4 }
- T{ ##shl-imm f V int-regs 0 V int-regs 0 3 }
+ T{ ##load-immediate f V int-rep 0 4 }
+ T{ ##shl-imm f V int-rep 0 V int-rep 0 3 }
} compile-test-bb
] unit-test
[ 31 ] [
V{
- T{ ##load-reference f V int-regs 1 B{ 31 67 52 } }
- T{ ##unbox-any-c-ptr f V int-regs 0 V int-regs 1 V int-regs 2 }
- T{ ##alien-unsigned-1 f V int-regs 0 V int-regs 0 }
- T{ ##shl-imm f V int-regs 0 V int-regs 0 3 }
+ T{ ##load-reference f V int-rep 1 B{ 31 67 52 } }
+ T{ ##unbox-any-c-ptr f V int-rep 0 V int-rep 1 V int-rep 2 }
+ T{ ##alien-unsigned-1 f V int-rep 0 V int-rep 0 }
+ T{ ##shl-imm f V int-rep 0 V int-rep 0 3 }
} compile-test-bb
] unit-test
[ CHAR: l ] [
V{
- T{ ##load-reference f V int-regs 0 "hello world" }
- T{ ##load-immediate f V int-regs 1 3 }
- T{ ##string-nth f V int-regs 0 V int-regs 0 V int-regs 1 V int-regs 2 }
- T{ ##shl-imm f V int-regs 0 V int-regs 0 3 }
+ T{ ##load-reference f V int-rep 0 "hello world" }
+ T{ ##load-immediate f V int-rep 1 3 }
+ T{ ##string-nth f V int-rep 0 V int-rep 0 V int-rep 1 V int-rep 2 }
+ T{ ##shl-imm f V int-rep 0 V int-rep 0 3 }
} compile-test-bb
] unit-test
[ 1 ] [
V{
- T{ ##load-immediate f V int-regs 0 16 }
- T{ ##add-imm f V int-regs 0 V int-regs 0 -8 }
+ T{ ##load-immediate f V int-rep 0 16 }
+ T{ ##add-imm f V int-rep 0 V int-rep 0 -8 }
} compile-test-bb
] unit-test
[ 100 ] [
V{
- T{ ##load-immediate f V int-regs 0 100 }
- T{ ##integer>bignum f V int-regs 0 V int-regs 0 V int-regs 1 }
+ T{ ##load-immediate f V int-rep 0 100 }
+ T{ ##integer>bignum f V int-rep 0 V int-rep 0 V int-rep 1 }
} compile-test-bb
] unit-test
[ 1 ] [
V{
- T{ ##load-reference f V int-regs 0 ALIEN: 8 }
- T{ ##unbox-any-c-ptr f V int-regs 0 V int-regs 0 V int-regs 1 }
+ T{ ##load-reference f V int-rep 0 ALIEN: 8 }
+ T{ ##unbox-any-c-ptr f V int-rep 0 V int-rep 0 V int-rep 1 }
} compile-test-bb
] unit-test
-! Copyright (C) 2006, 2008 Slava Pestov.
+! Copyright (C) 2006, 2009 Slava Pestov.
! See http://factorcode.org/license.txt for BSD license.
USING: accessors arrays generic kernel kernel.private math
memory namespaces make sequences layouts system hashtables
classes alien byte-arrays combinators words sets fry ;
IN: cpu.architecture
-! Register classes
-SINGLETON: int-regs
-SINGLETON: single-float-regs
-SINGLETON: double-float-regs
-UNION: float-regs single-float-regs double-float-regs ;
-UNION: reg-class int-regs float-regs ;
+! Representations -- these are like low-level types
-! A pseudo-register class for parameters spilled on the stack
-SINGLETON: stack-params
+! Integer registers can contain data with one of these two representations
+SINGLETONS: tagged-rep int-rep ;
-GENERIC: reg-size ( register-class -- n )
+! Floating point registers can contain data with
+! one of these representations
+SINGLETONS: single-float-rep double-float-rep ;
-M: int-regs reg-size drop cell ;
+UNION: representation tagged-rep int-rep single-float-rep double-float-rep ;
-M: single-float-regs reg-size drop 4 ;
+! Register classes
+SINGLETONS: int-regs float-regs ;
-M: double-float-regs reg-size drop 8 ;
+UNION: reg-class int-regs float-regs ;
+CONSTANT: reg-classes { int-regs float-regs }
-M: stack-params reg-size drop cell ;
+! A pseudo-register class for parameters spilled on the stack
+SINGLETON: stack-params
+
+: reg-class-of ( rep -- reg-class )
+ {
+ { tagged-rep [ int-regs ] }
+ { int-rep [ int-regs ] }
+ { single-float-rep [ float-regs ] }
+ { double-float-rep [ float-regs ] }
+ { stack-params [ stack-params ] }
+ } case ;
+
+: rep-size ( rep -- n )
+ {
+ { tagged-rep [ cell ] }
+ { int-rep [ cell ] }
+ { single-float-rep [ 4 ] }
+ { double-float-rep [ 8 ] }
+ { stack-params [ cell ] }
+ } case ;
! Mapping from register class to machine registers
HOOK: machine-registers cpu ( -- assoc )
-! Return values of this class go here
-GENERIC: return-reg ( register-class -- reg )
-
-! Sequence of registers used for parameter passing in class
-GENERIC: param-regs ( register-class -- regs )
-
-GENERIC: param-reg ( n register-class -- reg )
-
-M: object param-reg param-regs nth ;
-
HOOK: two-operand? cpu ( -- ? )
HOOK: %load-immediate cpu ( reg obj -- )
HOOK: %integer>float cpu ( dst src -- )
HOOK: %float>integer cpu ( dst src -- )
-HOOK: %copy cpu ( dst src -- )
-HOOK: %copy-float cpu ( dst src -- )
+HOOK: %copy cpu ( dst src rep -- )
HOOK: %unbox-float cpu ( dst src -- )
HOOK: %unbox-any-c-ptr cpu ( dst src temp -- )
HOOK: %box-float cpu ( dst src temp -- )
HOOK: %compare-imm-branch cpu ( label cc src1 src2 -- )
HOOK: %compare-float-branch cpu ( label cc src1 src2 -- )
-HOOK: %spill-integer cpu ( src n -- )
-HOOK: %spill-float cpu ( src n -- )
-HOOK: %reload-integer cpu ( dst n -- )
-HOOK: %reload-float cpu ( dst n -- )
+HOOK: %spill cpu ( src n rep -- )
+HOOK: %reload cpu ( dst n rep -- )
HOOK: %loop-entry cpu ( -- )
! FFI stuff
+! Return values of this class go here
+GENERIC: return-reg ( reg-class -- reg )
+
+! Sequence of registers used for parameter passing in class
+GENERIC: param-regs ( reg-class -- regs )
+
+M: stack-params param-regs drop f ;
+
+GENERIC: param-reg ( n reg-class -- reg )
+
+M: reg-class param-reg param-regs nth ;
+
+M: stack-params param-reg drop ;
+
! Is this integer small enough to appear in value template
! slots?
HOOK: small-enough? cpu ( n -- ? )
HOOK: %prepare-unbox cpu ( -- )
-HOOK: %unbox cpu ( n reg-class func -- )
+HOOK: %unbox cpu ( n rep func -- )
HOOK: %unbox-long-long cpu ( n func -- )
HOOK: %unbox-large-struct cpu ( n c-type -- )
-HOOK: %box cpu ( n reg-class func -- )
+HOOK: %box cpu ( n rep func -- )
HOOK: %box-long-long cpu ( n func -- )
HOOK: %box-large-struct cpu ( n c-type -- )
-GENERIC: %save-param-reg ( stack reg reg-class -- )
+HOOK: %save-param-reg cpu ( stack reg rep -- )
-GENERIC: %load-param-reg ( stack reg reg-class -- )
+HOOK: %load-param-reg cpu ( stack reg rep -- )
HOOK: %prepare-alien-invoke cpu ( -- )
HOOK: %callback-return cpu ( params -- )
M: object %callback-return drop %return ;
-
-M: stack-params param-reg drop ;
-
-M: stack-params param-regs drop f ;
M: ppc machine-registers
{
{ int-regs $[ 2 12 [a,b] 15 29 [a,b] append ] }
- { double-float-regs $[ 0 29 [a,b] ] }
+ { float-regs $[ 0 29 [a,b] ] }
} ;
CONSTANT: scratch-reg 30
M: int-regs %save-param-reg drop 1 rot local@ STW ;
M: int-regs %load-param-reg drop 1 rot local@ LWZ ;
-GENERIC: STF ( src dst off reg-class -- )
+M: single-float-rep %save-param-reg drop 1 rot local@ STFS ;
+M: single-float-rep %load-param-reg 1 rot local@ LFS ;
-M: single-float-regs STF drop STFS ;
-M: double-float-regs STF drop STFD ;
+M: double-float-rep %save-param-reg drop 1 rot local@ STFD ;
+M: double-float-rep %load-param-reg 1 rot local@ LFD ;
-M: float-regs %save-param-reg [ 1 rot local@ ] dip STF ;
-
-GENERIC: LF ( dst src off reg-class -- )
-
-M: single-float-regs LF drop LFS ;
-M: double-float-regs LF drop LFD ;
-
-M: float-regs %load-param-reg [ 1 rot local@ ] dip LF ;
-
-M: stack-params %load-param-reg ( stack reg reg-class -- )
+M: stack-params %load-param-reg ( stack reg rep -- )
drop [ 0 1 rot local@ LWZ 0 1 ] dip param@ STW ;
: next-param@ ( n -- x ) param@ stack-frame get total-size>> + ;
-M: stack-params %save-param-reg ( stack reg reg-class -- )
+M: stack-params %save-param-reg ( stack reg rep -- )
#! Funky. Read the parameter from the caller's stack frame.
#! This word is used in callbacks
drop
3 ds-reg 0 LWZ
ds-reg dup cell SUBI ;
-M: ppc %unbox ( n reg-class func -- )
+M: ppc %unbox ( n rep func -- )
! Value must be in r3
! Call the unboxer
f %alien-invoke
! Store the return value on the C stack
- over [ [ return-reg ] keep %save-param-reg ] [ 2drop ] if ;
+ over [ [ reg-class-of return-reg ] keep %save-param-reg ] [ 2drop ] if ;
M: ppc %unbox-long-long ( n func -- )
! Value must be in r3:r4
! Call the function
"to_value_struct" f %alien-invoke ;
-M: ppc %box ( n reg-class func -- )
+M: ppc %box ( n rep func -- )
! If the source is a stack location, load it into freg #0.
! If the source is f, then we assume the value is already in
! freg #0.
- [ over [ 0 over param-reg swap %load-param-reg ] [ 2drop ] if ] dip
+ [ over [ 0 over reg-class-of param-reg swap %load-param-reg ] [ 2drop ] if ] dip
f %alien-invoke ;
M: ppc %box-long-long ( n func -- )
IN: cpu.x86.32
! We implement the FFI for Linux, OS X and Windows all at once.
-! OS X requires that the stack be 16-byte aligned, and we do
-! this on all platforms, sacrificing some stack space for
-! code simplicity.
+! OS X requires that the stack be 16-byte aligned.
M: x86.32 machine-registers
{
{ int-regs { EAX ECX EDX EBP EBX } }
- { double-float-regs { XMM0 XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7 } }
+ { float-regs { XMM0 XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7 } }
} ;
M: x86.32 ds-reg ESI ;
M: x86.32 rs-reg EDI ;
M: x86.32 stack-reg ESP ;
-M: x86.32 temp-reg-1 ECX ;
-M: x86.32 temp-reg-2 EDX ;
+M: x86.32 temp-reg ECX ;
M:: x86.32 %dispatch ( src temp -- )
! Load jump table base.
! On x86, parameters are never passed in registers.
M: int-regs return-reg drop EAX ;
M: int-regs param-regs drop { } ;
-M: int-regs push-return-reg return-reg PUSH ;
-
-M: int-regs load-return-reg
- return-reg swap next-stack@ MOV ;
-
-M: int-regs store-return-reg
- [ stack@ ] [ return-reg ] bi* MOV ;
-
M: float-regs param-regs drop { } ;
-: FSTP ( operand size -- ) 4 = [ FSTPS ] [ FSTPL ] if ;
-
-M: float-regs push-return-reg
- stack-reg swap reg-size
- [ SUB ] [ [ [] ] dip FSTP ] 2bi ;
+GENERIC: push-return-reg ( rep -- )
+GENERIC: load-return-reg ( n rep -- )
+GENERIC: store-return-reg ( n rep -- )
-: FLD ( operand size -- ) 4 = [ FLDS ] [ FLDL ] if ;
+M: int-rep push-return-reg drop EAX PUSH ;
+M: int-rep load-return-reg drop EAX swap next-stack@ MOV ;
+M: int-rep store-return-reg drop stack@ EAX MOV ;
-M: float-regs load-return-reg
- [ next-stack@ ] [ reg-size ] bi* FLD ;
+M: single-float-rep push-return-reg drop ESP 4 SUB ESP [] FSTPS ;
+M: single-float-rep load-return-reg drop next-stack@ FLDS ;
+M: single-float-rep store-return-reg drop stack@ FSTPS ;
-M: float-regs store-return-reg
- [ stack@ ] [ reg-size ] bi* FSTP ;
+M: double-float-rep push-return-reg drop ESP 8 SUB ESP [] FSTPL ;
+M: double-float-rep load-return-reg drop next-stack@ FLDL ;
+M: double-float-rep store-return-reg drop stack@ FSTPL ;
: align-sub ( n -- )
[ align-stack ] keep - decr-stack-reg ;
0 PUSH rc-absolute-cell rel-this
3 cells - decr-stack-reg ;
-M: object %load-param-reg 3drop ;
+M: x86.32 %load-param-reg 3drop ;
-M: object %save-param-reg 3drop ;
+M: x86.32 %save-param-reg 3drop ;
-: (%box) ( n reg-class -- )
+: (%box) ( n rep -- )
#! If n is f, push the return register onto the stack; we
#! are boxing a return value of a C function. If n is an
#! integer, push [ESP+n] on the stack; we are boxing a
#! parameter being passed to a callback from C.
over [ load-return-reg ] [ 2drop ] if ;
-M:: x86.32 %box ( n reg-class func -- )
- n reg-class (%box)
- reg-class reg-size [
- reg-class push-return-reg
+M:: x86.32 %box ( n rep func -- )
+ n rep (%box)
+ rep rep-size [
+ rep push-return-reg
func f %alien-invoke
] with-aligned-stack ;
EAX ESI [] MOV
ESI 4 SUB ;
-: (%unbox) ( func -- )
+: call-unbox-func ( func -- )
4 [
! Push parameter
EAX PUSH
f %alien-invoke
] with-aligned-stack ;
-M: x86.32 %unbox ( n reg-class func -- )
+M: x86.32 %unbox ( n rep func -- )
#! The value being unboxed must already be in EAX.
#! If n is f, we're unboxing a return value about to be
#! returned by the callback. Otherwise, we're unboxing
#! a parameter to a C function about to be called.
- (%unbox)
+ call-unbox-func
! Store the return value on the C stack
over [ store-return-reg ] [ 2drop ] if ;
M: x86.32 %unbox-long-long ( n func -- )
- (%unbox)
+ call-unbox-func
! Store the return value on the C stack
[
dup stack@ EAX MOV
M: x86.64 machine-registers
{
{ int-regs { RAX RCX RDX RBX RBP RSI RDI R8 R9 R10 R11 R12 R13 } }
- { double-float-regs {
+ { float-regs {
XMM0 XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7
XMM8 XMM9 XMM10 XMM11 XMM12 XMM13 XMM14 XMM15
} }
M: float-regs return-reg drop XMM0 ;
M: x86.64 %prologue ( n -- )
- temp-reg-1 0 MOV rc-absolute-cell rel-this
+ temp-reg 0 MOV rc-absolute-cell rel-this
dup PUSH
- temp-reg-1 PUSH
+ temp-reg PUSH
stack-reg swap 3 cells - SUB ;
-M: stack-params %load-param-reg
+M: stack-params copy-register*
drop
- [ R11 swap param@ MOV ] dip
- param@ R11 MOV ;
+ {
+ { [ dup integer? ] [ R11 swap next-stack@ MOV R11 MOV ] }
+ { [ over integer? ] [ R11 swap MOV param@ R11 MOV ] }
+ } cond ;
-M: stack-params %save-param-reg
- drop
- R11 swap next-stack@ MOV
- param@ R11 MOV ;
+M: x86 %save-param-reg [ param@ ] 2dip copy-register ;
+
+M: x86 %load-param-reg [ swap param@ ] dip copy-register ;
: with-return-regs ( quot -- )
[
param-reg-1 R14 [] MOV
R14 cell SUB ;
-M: x86.64 %unbox ( n reg-class func -- )
+M:: x86.64 %unbox ( n rep func -- )
! Call the unboxer
- f %alien-invoke
- ! Store the return value on the C stack
- over [ [ return-reg ] keep %save-param-reg ] [ 2drop ] if ;
+ func f %alien-invoke
+ ! Store the return value on the C stack if this is an
+ ! alien-invoke, otherwise leave it the return register if
+ ! this is the end of alien-callback
+ n [ n rep reg-class-of return-reg rep %save-param-reg ] when ;
M: x86.64 %unbox-long-long ( n func -- )
- int-regs swap %unbox ;
+ [ int-rep ] dip %unbox ;
: %unbox-struct-field ( c-type i -- )
! Alien must be in param-reg-1.
- R11 swap cells [+] swap reg-class>> {
+ R11 swap cells [+] swap rep>> reg-class-of {
{ int-regs [ int-regs get pop swap MOV ] }
- { double-float-regs [ float-regs get pop swap MOVSD ] }
+ { float-regs [ float-regs get pop swap MOVSD ] }
} case ;
M: x86.64 %unbox-small-struct ( c-type -- )
! Copy the struct to the C stack
"to_value_struct" f %alien-invoke ;
-: load-return-value ( reg-class -- )
- 0 over param-reg swap return-reg
- 2dup eq? [ 2drop ] [ MOV ] if ;
-
-M: x86.64 %box ( n reg-class func -- )
- rot [
- rot [ 0 swap param-reg ] keep %load-param-reg
+: load-return-value ( rep -- )
+ [ [ 0 ] dip reg-class-of param-reg ]
+ [ reg-class-of return-reg ]
+ [ ]
+ tri copy-register ;
+
+M:: x86.64 %box ( n rep func -- )
+ n [
+ n
+ 0 rep reg-class-of param-reg
+ rep %load-param-reg
] [
- swap load-return-value
- ] if*
- f %alien-invoke ;
+ rep load-return-value
+ ] if
+ func f %alien-invoke ;
M: x86.64 %box-long-long ( n func -- )
- int-regs swap %box ;
+ [ int-rep ] dip %box ;
: box-struct-field@ ( i -- operand ) 1+ cells param@ ;
: %box-struct-field ( c-type i -- )
- box-struct-field@ swap reg-class>> {
+ box-struct-field@ swap c-type-rep reg-class-of {
{ int-regs [ int-regs get pop MOV ] }
- { double-float-regs [ float-regs get pop MOVSD ] }
+ { float-regs [ float-regs get pop MOVSD ] }
} case ;
M: x86.64 %box-small-struct ( c-type -- )
compiler.cfg.registers ;
IN: cpu.x86.64.unix
-M: int-regs param-regs drop { RDI RSI RDX RCX R8 R9 } ;
+M: int-regs param-regs
+ drop { RDI RSI RDX RCX R8 R9 } ;
M: float-regs param-regs
drop { XMM0 XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7 } ;
! The ABI for passing structs by value is pretty messed up
<< "void*" c-type clone "__stack_value" define-primitive-type
-stack-params "__stack_value" c-type (>>reg-class) >>
+stack-params "__stack_value" c-type (>>rep) >>
: struct-types&offset ( struct-type -- pairs )
fields>> [
: flatten-small-struct ( c-type -- seq )
struct-types&offset split-struct [
- [ c-type c-type-reg-class ] map
+ [ c-type c-type-rep reg-class-of ] map
int-regs swap member? "void*" "double" ? c-type
] map ;
M: x86.64 dummy-fp-params? f ;
-M: x86.64 temp-reg-1 R8 ;
-
-M: x86.64 temp-reg-2 R9 ;
+M: x86.64 temp-reg R8 ;
M: x86.64 dummy-fp-params? t ;
-M: x86.64 temp-reg-1 RAX ;
-
-M: x86.64 temp-reg-2 RCX ;
+M: x86.64 temp-reg RAX ;
<<
"longlong" "ptrdiff_t" typedef
XMM0 XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7
XMM8 XMM9 XMM10 XMM11 XMM12 XMM13 XMM14 XMM15 ;
-<PRIVATE
-
-GENERIC: extended? ( op -- ? )
-
-M: object extended? drop f ;
-
PREDICATE: register < word
"register" word-prop ;
+<PRIVATE
+
PREDICATE: register-8 < register
"register-size" word-prop 8 = ;
PREDICATE: register-128 < register
"register-size" word-prop 128 = ;
+GENERIC: extended? ( op -- ? )
+
+M: object extended? drop f ;
+
M: register extended? "register" word-prop 7 > ;
! Addressing modes
: param@ ( n -- op ) reserved-area-size + stack@ ;
-: spill-integer@ ( n -- op ) spill-integer-offset param@ ;
-
-: spill-float@ ( n -- op ) spill-float-offset param@ ;
+: spill@ ( n -- op ) spill-offset param@ ;
: gc-root@ ( n -- op ) gc-root-offset param@ ;
M: x86 stack-frame-size ( stack-frame -- i )
(stack-frame-size) 3 cells reserved-area-size + + align-stack ;
-HOOK: temp-reg-1 cpu ( -- reg )
-HOOK: temp-reg-2 cpu ( -- reg )
+! Must be a volatile register not used for parameter passing, for safe
+! use in calls in and out of C
+HOOK: temp-reg cpu ( -- reg )
+! Fastcall calling convention
HOOK: param-reg-1 cpu ( -- reg )
HOOK: param-reg-2 cpu ( -- reg )
M: x86 %not drop NOT ;
M: x86 %log2 BSR ;
-: ?MOV ( dst src -- )
- 2dup = [ 2drop ] [ MOV ] if ; inline
-
:: overflow-template ( label dst src1 src2 insn -- )
src1 src2 insn call
label JO ; inline
M: x86 %integer>float CVTSI2SD ;
M: x86 %float>integer CVTTSD2SI ;
-M: x86 %copy ( dst src -- ) ?MOV ;
+GENERIC: copy-register* ( dst src rep -- )
-M: x86 %copy-float ( dst src -- )
- 2dup = [ 2drop ] [ MOVSD ] if ;
+M: int-rep copy-register* drop MOV ;
+M: tagged-rep copy-register* drop MOV ;
+M: single-float-rep copy-register* drop MOVSS ;
+M: double-float-rep copy-register* drop MOVSD ;
+
+: copy-register ( dst src rep -- )
+ 2over eq? [ 3drop ] [ copy-register* ] if ;
+
+M: x86 %copy ( dst src rep -- ) copy-register ;
M: x86 %unbox-float ( dst src -- )
float-offset [+] MOVSD ;
[ quot call ] with-save/restore
] if ; inline
+: ?MOV ( dst src -- )
+ 2dup = [ 2drop ] [ MOV ] if ; inline
+
M:: x86 %string-nth ( dst src index temp -- )
! We request a small-reg of size 8 since those of size 16 are
! a superset.
{ cc/= [ JNE ] }
} case ;
-M: x86 %spill-integer ( src n -- ) spill-integer@ swap MOV ;
-M: x86 %reload-integer ( dst n -- ) spill-integer@ MOV ;
-
-M: x86 %spill-float ( src n -- ) spill-float@ swap MOVSD ;
-M: x86 %reload-float ( dst n -- ) spill-float@ MOVSD ;
+M: x86 %spill ( src n rep -- ) [ spill@ swap ] dip copy-register ;
+M: x86 %reload ( dst n rep -- ) [ spill@ ] dip copy-register ;
M: x86 %loop-entry 16 code-alignment [ NOP ] times ;
-M: int-regs %save-param-reg drop [ param@ ] dip MOV ;
-M: int-regs %load-param-reg drop swap param@ MOV ;
-
-GENERIC: MOVSS/D ( dst src reg-class -- )
-
-M: single-float-regs MOVSS/D drop MOVSS ;
-M: double-float-regs MOVSS/D drop MOVSD ;
-
-M: float-regs %save-param-reg [ param@ ] 2dip MOVSS/D ;
-M: float-regs %load-param-reg [ swap param@ ] dip MOVSS/D ;
-
-GENERIC: push-return-reg ( reg-class -- )
-GENERIC: load-return-reg ( n reg-class -- )
-GENERIC: store-return-reg ( n reg-class -- )
-
M: x86 %prepare-alien-invoke
#! Save Factor stack pointers in case the C code calls a
#! callback which does a GC, which must reliably trace
#! all roots.
- temp-reg-1 "stack_chain" f %alien-global
- temp-reg-1 temp-reg-1 [] MOV
- temp-reg-1 [] stack-reg MOV
- temp-reg-1 [] cell SUB
- temp-reg-1 2 cells [+] ds-reg MOV
- temp-reg-1 3 cells [+] rs-reg MOV ;
+ temp-reg "stack_chain" f %alien-global
+ temp-reg temp-reg [] MOV
+ temp-reg [] stack-reg MOV
+ temp-reg [] cell SUB
+ temp-reg 2 cells [+] ds-reg MOV
+ temp-reg 3 cells [+] rs-reg MOV ;
M: x86 value-struct? drop t ;
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