Also bump the signal handler frame sizes up again since it looks like we shrank them too much.
"end_callback" jit-call
] \ c-to-factor define-sub-primitive
-! The signal-handler and leaf-signal-handler subprimitives are special-cased
-! in vm/quotations.cpp not to trigger generation of a stack frame, so they can
-! peform their own prolog/epilog preserving registers.
-
-:: jit-signal-handler-prolog ( -- frame-size )
- signal-handler-stack-frame-size :> frame-size
- ! minus a cell each for flags and return address
- ! use LEA so we don't dirty flags
- ESP ESP frame-size 2 bootstrap-cells - neg [+] LEA
- ESP [] EAX MOV
- ESP 1 bootstrap-cells [+] ECX MOV
- ESP 2 bootstrap-cells [+] EDX MOV
- ESP 3 bootstrap-cells [+] EBX MOV
- ESP 4 bootstrap-cells [+] EBP MOV
- ESP 5 bootstrap-cells [+] ESI MOV
- ESP 6 bootstrap-cells [+] EDI MOV
- PUSHF
- ESP frame-size 3 bootstrap-cells - [+] 0 MOV rc-absolute-cell rel-this
- ESP frame-size 2 bootstrap-cells - [+] frame-size MOV
- ! subprimitive definition assumes vm's been loaded
- jit-load-vm
- frame-size ;
-
-:: jit-signal-handler-epilog ( frame-size -- )
- POPF
- EAX ESP [] MOV
- ECX ESP 1 bootstrap-cells [+] MOV
- EDX ESP 2 bootstrap-cells [+] MOV
- EBX ESP 3 bootstrap-cells [+] MOV
- EBP ESP 4 bootstrap-cells [+] MOV
- ESI ESP 5 bootstrap-cells [+] MOV
- EDI ESP 6 bootstrap-cells [+] MOV
- ESP ESP frame-size 2 bootstrap-cells - [+] LEA ;
+: signal-handler-save-regs ( -- regs )
+ { EAX ECX EDX EBX EBP ESI EDI } ;
[
EAX ds-reg [] MOV
: signal-handler-save-regs ( -- regs )
{ RAX RCX RDX RBX RBP RSI RDI R8 R9 R10 R11 R12 R13 R14 R15 } ;
-:: jit-signal-handler-prolog ( -- frame-size )
- signal-handler-save-regs :> save-regs
- signal-handler-stack-frame-size :> frame-size
- ! minus a cell each for flags, return address
- ! use LEA so we don't dirty flags
- RSP RSP frame-size 2 bootstrap-cells - neg [+] LEA
- save-regs [| r i | RSP i bootstrap-cells [+] r MOV ] each-index
- PUSHF
- frame-size ;
-
-:: jit-signal-handler-epilog ( frame-size -- )
- POPF
- signal-handler-save-regs
- [| r i | r RSP i bootstrap-cells [+] MOV ] each-index
- RSP RSP frame-size 2 bootstrap-cells - [+] LEA ;
-
[
arg1 ds-reg [] MOV
ds-reg bootstrap-cell SUB
IN: bootstrap.x86
: leaf-stack-frame-size ( -- n ) 2 bootstrap-cells ;
-: signal-handler-stack-frame-size ( -- n ) 18 bootstrap-cells ;
+: signal-handler-stack-frame-size ( -- n ) 20 bootstrap-cells ;
: stack-frame-size ( -- n ) 4 bootstrap-cells ;
: nv-regs ( -- seq ) { RBX R12 R13 R14 R15 } ;
: volatile-regs ( -- seq ) { RAX RCX RDX RSI RDI R8 R9 R10 R11 } ;
DEFER: stack-reg
: leaf-stack-frame-size ( -- n ) 2 bootstrap-cells ;
-: signal-handler-stack-frame-size ( -- n ) 22 bootstrap-cells ;
+: signal-handler-stack-frame-size ( -- n ) 24 bootstrap-cells ;
: stack-frame-size ( -- n ) 8 bootstrap-cells ;
: nv-regs ( -- seq ) { RBX RSI RDI R12 R13 R14 R15 } ;
: volatile-regs ( -- seq ) { RAX RCX RDX R8 R9 R10 R11 } ;
! not to trigger generation of a stack frame, so they can
! peform their own prolog/epilog preserving registers.
+: jit-signal-handler-prolog ( -- )
+ ! minus a cell each for flags, return address
+ ! use LEA so we don't dirty flags
+ stack-reg stack-reg signal-handler-stack-frame-size
+ 2 bootstrap-cells - neg [+] LEA
+
+ signal-handler-save-regs
+ [| r i | stack-reg i bootstrap-cells [+] r MOV ] each-index
+
+ PUSHF ;
+
+: jit-signal-handler-epilog ( -- )
+ POPF
+
+ signal-handler-save-regs
+ [| r i | r stack-reg i bootstrap-cells [+] MOV ] each-index
+
+ stack-reg stack-reg signal-handler-stack-frame-size
+ 2 bootstrap-cells - [+] LEA ;
+
[| |
- jit-signal-handler-prolog :> frame-size
+ jit-signal-handler-prolog
jit-save-context
temp0 vm-reg vm-signal-handler-addr-offset [+] MOV
temp0 CALL
- frame-size jit-signal-handler-epilog
+ jit-signal-handler-epilog
0 RET
] \ signal-handler define-sub-primitive
[| |
- jit-signal-handler-prolog :> frame-size
+ jit-signal-handler-prolog
jit-save-context
temp0 vm-reg vm-signal-handler-addr-offset [+] MOV
temp0 CALL
- frame-size jit-signal-handler-epilog
+ jit-signal-handler-epilog
! Pop the fake leaf frame along with our return address
leaf-stack-frame-size bootstrap-cell - RET
] \ leaf-signal-handler define-sub-primitive
[| |
- jit-signal-handler-prolog :> frame-size
+ jit-signal-handler-prolog
temp0 vm-reg vm-signal-handler-addr-offset [+] MOV
temp0 CALL
- frame-size jit-signal-handler-epilog
+ jit-signal-handler-epilog
red-zone-size RET
] \ ffi-signal-handler define-sub-primitive
[| |
- jit-signal-handler-prolog :> frame-size
+ jit-signal-handler-prolog
temp0 vm-reg vm-signal-handler-addr-offset [+] MOV
temp0 CALL
- frame-size jit-signal-handler-epilog
+ jit-signal-handler-epilog
red-zone-size 16 bootstrap-cell - + RET
] \ ffi-leaf-signal-handler define-sub-primitive
/* Must match the leaf-stack-frame-size, signal-handler-stack-frame-size,
and stack-frame-size constants in basis/cpu/x86/64/unix/bootstrap.factor */
static const unsigned LEAF_FRAME_SIZE = 16;
-static const unsigned SIGNAL_HANDLER_STACK_FRAME_SIZE = 144;
+static const unsigned SIGNAL_HANDLER_STACK_FRAME_SIZE = 160;
static const unsigned JIT_FRAME_SIZE = 32;
}
/* Must match the leaf-stack-frame-size, signal-handler-stack-frame-size,
and stack-frame-size constants in basis/cpu/x86/64/unix/bootstrap.factor */
static const unsigned LEAF_FRAME_SIZE = 16;
-static const unsigned SIGNAL_HANDLER_STACK_FRAME_SIZE = 144;
+static const unsigned SIGNAL_HANDLER_STACK_FRAME_SIZE = 160;
static const unsigned JIT_FRAME_SIZE = 32;
}
and stack-frame-size constants in basis/cpu/x86/64/windows/bootstrap.factor */
static const unsigned LEAF_FRAME_SIZE = 16;
-static const unsigned SIGNAL_HANDLER_STACK_FRAME_SIZE = 176;
+static const unsigned SIGNAL_HANDLER_STACK_FRAME_SIZE = 192;
static const unsigned JIT_FRAME_SIZE = 64;
}