cpu.arm.assembler: common code goes here, 32/64-specific code is in its own files

As suggested by gifti, we can have names for the assembler that correspond
to the opcodes and we can further remove the 32/64 split since most code
should only use one or the other.

diff --git a/basis/cpu/arm/assembler/32/32.factor b/basis/cpu/arm/assembler/32/32.factor
new file mode 100644 (file)
index 0000000..7f833a1
--- /dev/null
+++ b/basis/cpu/arm/assembler/32/32.factor
@@ -0,0 +1,28 @@
+! Copyright (C) 2023 Doug Coleman.
+! See https://factorcode.org/license.txt for BSD license.
+USING: cpu.arm.assembler cpu.arm.assembler.opcodes kernel math ;
+IN: cpu.arm.assembler.32
+
+: ADC ( Rm Rn Rd -- ) ADC32-encode ;
+: ADCS ( Rm Rn Rd -- ) ADCS32-encode ;
+
+: ADDi ( imm12 Rn Rd -- )
+    [ 12 prepare-split-imm 1 0 ? swap ] 2dip
+    ADDi32-encode ;
+
+: ASRi ( imm6 Rn Rd -- ) [ 6 ?bits ] 2dip ASRi32-encode ;
+
+: CMPi ( imm12 Rd -- )
+    [ 12 prepare-split-imm 1 0 ? swap ] dip
+    CMPi32-encode ;
+
+: LSLi ( imm6 Rn Rd -- ) [ 6 ?bits ] 2dip LSLi32-encode ;
+: LSRi ( imm6 Rn Rd -- ) [ 6 ?bits ] 2dip LSRi32-encode ;
+
+: STRuoff ( imm12 Rn Rt -- )
+    [ -2 shift ] 2dip STRuoff32-encode ;
+
+: SUBi ( imm12 Rn Rd -- )
+    [ 12 prepare-split-imm 1 0 ? swap ] 2dip
+    SUBi32-encode ;
+

diff --git a/basis/cpu/arm/assembler/32/authors.txt b/basis/cpu/arm/assembler/32/authors.txt
new file mode 100644 (file)
index 0000000..7c1b2f2
--- /dev/null
+++ b/basis/cpu/arm/assembler/32/authors.txt
@@ -0,0 +1 @@
+Doug Coleman

diff --git a/basis/cpu/arm/assembler/64/64.factor b/basis/cpu/arm/assembler/64/64.factor
new file mode 100644 (file)
index 0000000..b21cefb
--- /dev/null
+++ b/basis/cpu/arm/assembler/64/64.factor
@@ -0,0 +1,69 @@
+! Copyright (C) 2023 Doug Coleman.
+! See https://factorcode.org/license.txt for BSD license.
+USING: cpu.arm.assembler cpu.arm.assembler.opcodes kernel math
+math.bitwise ;
+IN: cpu.arm.assembler.64
+
+: ADC ( Rm Rn Rd -- ) ADC64-encode ;
+: ADCS ( Rm Rn Rd -- ) ADCS64-encode ;
+
+: ADDi ( imm12 Rn Rd -- )
+    [ 12 prepare-split-imm 1 0 ? swap ] 2dip
+    ADDi64-encode ;
+
+: ASRi ( imm6 Rn Rd -- ) [ 6 ?bits ] 2dip ASRi64-encode ;
+
+: CBNZ ( imm19 Rt -- ) [ 19 ?bits ] dip CBNZ64-encode ;
+
+: CMPi ( imm12 Rd -- )
+    [ 12 prepare-split-imm 1 0 ? swap ] dip
+    CMPi64-encode ;
+
+! cond4 is EQ NE CS HS CC LO MI PL VS VC HI LS GE LT GT LE AL NV
+: CSEL ( Rm Rn Rd cond4 -- ) -rot CSEL64-encode ;
+: CSET ( Rd cond4 -- ) swap CSET64-encode ;
+: CSETM ( Rd cond4 -- ) swap CSETM64-encode ;
+
+: LDR-pre ( imm9 Rn Rt -- ) LDRpre64-encode ;
+: LDR-post ( imm9 Rn Rt -- ) LDRpost64-encode ;
+: LDR-uoff ( imm12 Rn Rt -- ) [ 8 / ] 2dip LDRuoff64-encode ;
+
+: LDP-pre ( offset register-offset register-mid register -- )
+    [ 8 / 7 bits ] 3dip swapd LDPpre64-encode ;
+
+: LDP-post ( offset register-offset register-mid register -- )
+    [ 8 / 7 bits ] 3dip swapd LDPpost64-encode ;
+
+: LDP-signed-offset ( offset register-offset register-mid register -- )
+    [ 8 / 7 bits ] 3dip swapd LDPsoff64-encode ;
+
+: LSLi ( imm6 Rn Rd -- ) [ 6 ?bits ] 2dip LSLi64-encode ;
+: LSRi ( imm6 Rn Rd -- ) [ 6 ?bits ] 2dip LSRi64-encode ;
+
+
+: MOVwi ( imm Rt -- ) [ 0 ] 2dip MOVwi64-encode ;
+: MOVr ( Rn Rd -- ) MOVr64-encode ;
+
+
+
+! stp     x29, x30, [sp,#-16]!
+! -16 SP X30 X29 STP-pre
+: STP-pre ( offset register-offset register-mid register -- )
+    [ 8 / 7 bits ] 3dip swapd STPpre64-encode ;
+
+: STP-post ( offset register-offset register-mid register -- )
+    [ 8 / 7 bits ] 3dip swapd STPpost64-encode ;
+
+: STP-signed-offset ( offset register-offset register-mid register -- )
+    [ 8 / 7 bits ] 3dip swapd STPsoff64-encode ;
+
+: STRr ( Rm Rn Rt -- )
+    [ 0 0 ] 2dip STRr64-encode ;
+
+: STRuoff ( imm12 Rn Rt -- )
+    [ -3 shift ] 2dip STRuoff64-encode ;
+
+: SUBi ( imm12 Rn Rd -- )
+    [ 12 prepare-split-imm 1 0 ? swap ] 2dip
+    SUBi64-encode ;
+

diff --git a/basis/cpu/arm/assembler/64/authors.txt b/basis/cpu/arm/assembler/64/authors.txt
new file mode 100644 (file)
index 0000000..7c1b2f2
--- /dev/null
+++ b/basis/cpu/arm/assembler/64/authors.txt
@@ -0,0 +1 @@
+Doug Coleman

diff --git a/basis/cpu/arm/assembler/assembler.factor b/basis/cpu/arm/assembler/assembler.factor
index aade11ddf96aca1e49b9d013eb8230532e3a059e..5ec603272b5b794bc3a8edbc1e567694eb30f629 100644 (file)
--- a/basis/cpu/arm/assembler/assembler.factor
+++ b/basis/cpu/arm/assembler/assembler.factor
@@ -15,43 +15,6 @@ ERROR: arm64-encoding-imm original n-bits-requested truncated ;
 
 ! : ip ( -- address ) arm64-assembler get ip>> ;
 
-: ADR ( imm21 Rd -- )
-    [ [ 2 bits ] [ -2 shift 19 ?bits ] bi ] dip ADR-encode ;
-
-: ADRP ( imm21 Rd -- )
-    [ [ 2 bits ] [ -2 shift 19 ?bits ] bi ] dip ADRP-encode ;
-
-: LDR-pre ( imm9 Rn Rt -- ) LDRpre64-encode ;
-: LDR-post ( imm9 Rn Rt -- ) LDRpost64-encode ;
-: LDR-uoff ( imm12 Rn Rt -- ) [ 8 / ] 2dip LDRuoff64-encode ;
-: LDR-literal ( imm19 Rt -- ) [ 4 / 19 bits ] dip LDRl64-encode ;
-
-: MOVwi64 ( imm Rt -- ) [ 0 ] 2dip MOVwi64-encode ;
-: MOVr64 ( Rn Rd -- ) MOVr64-encode ;
-
-: RET ( register/f -- ) X30 or RET-encode ;
-
-! stp     x29, x30, [sp,#-16]!
-! -16 SP X30 X29 STP-pre
-: STP-pre ( offset register-offset register-mid register -- )
-    [ 8 / 7 bits ] 3dip swapd STPpre64-encode ;
-
-: STP-post ( offset register-offset register-mid register -- )
-    [ 8 / 7 bits ] 3dip swapd STPpost64-encode ;
-
-: STP-signed-offset ( offset register-offset register-mid register -- )
-    [ 8 / 7 bits ] 3dip swapd STPsoff64-encode ;
-
-
-: LDP-pre ( offset register-offset register-mid register -- )
-    [ 8 / 7 bits ] 3dip swapd LDPpre64-encode ;
-
-: LDP-post ( offset register-offset register-mid register -- )
-    [ 8 / 7 bits ] 3dip swapd LDPpost64-encode ;
-
-: LDP-signed-offset ( offset register-offset register-mid register -- )
-    [ 8 / 7 bits ] 3dip swapd LDPsoff64-encode ;
-
 ! Some instructions allow an immediate literal of n bits
 ! or n bits shifted. This means there are invalid immediate
 ! values, e.g. imm12 of 1, 4096, but not 4097
@@ -69,68 +32,19 @@ ERROR: imm-out-of-range imm n ;
         [ imm-out-of-range ]
     } cond ;
 
-: ADDi32 ( imm12 Rn Rd -- )
-    [ 12 prepare-split-imm 1 0 ? swap ] 2dip
-    ADDi32-encode ;
-
-: ADDi64 ( imm12 Rn Rd -- )
-    [ 12 prepare-split-imm 1 0 ? swap ] 2dip
-    ADDi64-encode ;
-
-: SUBi32 ( imm12 Rn Rd -- )
-    [ 12 prepare-split-imm 1 0 ? swap ] 2dip
-    SUBi32-encode ;
-
-: SUBi64 ( imm12 Rn Rd -- )
-    [ 12 prepare-split-imm 1 0 ? swap ] 2dip
-    SUBi64-encode ;
-
-: CMPi32 ( imm12 Rd -- )
-    [ 12 prepare-split-imm 1 0 ? swap ] dip
-    CMPi32-encode ;
-
-: CMPi64 ( imm12 Rd -- )
-    [ 12 prepare-split-imm 1 0 ? swap ] dip
-    CMPi64-encode ;
-
-: STRuoff32 ( imm12 Rn Rt -- )
-    [ -2 shift ] 2dip STRuoff32-encode ;
-
-: STRuoff64 ( imm12 Rn Rt -- )
-    [ -3 shift ] 2dip STRuoff64-encode ;
-
-: STRr64 ( Rm Rn Rt -- )
-    [ 0 0 ] 2dip STRr64-encode ;
-
-: STR-pre ( imm9 Rn Rt -- )
-    [ 9 bits ] 2dip STRpre64-encode ;
+: ADR ( imm21 Rd -- )
+    [ [ 2 bits ] [ -2 shift 19 ?bits ] bi ] dip ADR-encode ;
 
-: STR-post ( imm9 Rn Rt -- )
-    [ 9 bits ] 2dip STRpost64-encode ;
+: ADRP ( imm21 Rd -- )
+    [ [ 2 bits ] [ -2 shift 19 ?bits ] bi ] dip ADRP-encode ;
 
-: ASRi32 ( imm6 Rn Rd -- ) [ 6 ?bits ] 2dip ASRi32-encode ;
-: ASRi64 ( imm6 Rn Rd -- ) [ 6 ?bits ] 2dip ASRi64-encode ;
-: LSLi32 ( imm6 Rn Rd -- ) [ 6 ?bits ] 2dip LSLi32-encode ;
-: LSLi64 ( imm6 Rn Rd -- ) [ 6 ?bits ] 2dip LSLi64-encode ;
-: LSRi32 ( imm6 Rn Rd -- ) [ 6 ?bits ] 2dip LSRi32-encode ;
-: LSRi64 ( imm6 Rn Rd -- ) [ 6 ?bits ] 2dip LSRi64-encode ;
+: RET ( register/f -- ) X30 or RET-encode ;
 
 : SVC ( imm16 -- ) 16 ?bits SVC-encode ;
 
-: ADC32 ( Rm Rn Rd -- ) ADC32-encode ;
-: ADCS32 ( Rm Rn Rd -- ) ADCS32-encode ;
-: ADC64 ( Rm Rn Rd -- ) ADC64-encode ;
-: ADCS64 ( Rm Rn Rd -- ) ADCS64-encode ;
-
 : BRK ( imm16 -- ) 16 ?bits BRK-encode ;
 : HLT ( imm16 -- ) 16 ?bits HLT-encode ;
 
-: CBNZ ( imm19 Rt -- ) [ 19 ?bits ] dip CBNZ64-encode ;
-! cond4 is EQ NE CS HS CC LO MI PL VS VC HI LS GE LT GT LE AL NV
-: CSEL ( Rm Rn Rd cond4 -- ) -rot CSEL64-encode ;
-: CSET ( Rd cond4 -- ) swap CSET64-encode ;
-: CSETM ( Rd cond4 -- ) swap CSETM64-encode ;
-
 ! B but that is breakpoint
 : Br ( imm26 -- ) 26 ?bits B-encode ;
 : B.cond ( imm19 cond4 -- ) [ 19 ?bits ] dip B.cond-encode ;