cpu.ppc: fix non-optimizing compiler backend

diff --git a/basis/cpu/ppc/bootstrap.factor b/basis/cpu/ppc/bootstrap.factor
index fc525b7f4ebe3493b04cc8b3b2dc11e2c06ac3b4..a5267b898b76a9b6b4b55c991fb41413123b291a 100644 (file)
--- a/basis/cpu/ppc/bootstrap.factor
+++ b/basis/cpu/ppc/bootstrap.factor
@@ -28,13 +28,13 @@ CONSTANT: vm-reg 15
 : jit-save-context ( -- )\r
     4 vm-reg 0 LWZ\r
     1 4 0 STW\r
-    ds-reg vm-reg 8 STW\r
-    rs-reg vm-reg 12 STW ;\r
+    ds-reg 4 8 STW\r
+    rs-reg 4 12 STW ;\r
 \r
-: jit-load-context ( -- )\r
+: jit-restore-context ( -- )\r
     4 vm-reg 0 LWZ\r
-    ds-reg vm-reg 8 LWZ\r
-    rs-reg vm-reg 12 LWZ ;\r
+    ds-reg 4 8 LWZ\r
+    rs-reg 4 12 LWZ ;\r
 \r
 [\r
     0 3 LOAD32 rc-absolute-ppc-2/2 rt-literal jit-rel\r
@@ -68,7 +68,7 @@ CONSTANT: vm-reg 15
     0 4 LOAD32 rc-absolute-ppc-2/2 rt-primitive jit-rel\r
     4 MTLR\r
     BLRL\r
-    jit-load-context\r
+    jit-restore-context\r
 ] jit-primitive jit-define\r
 \r
 [ 0 BL rc-relative-ppc-3 rt-xt-pic jit-rel ] jit-word-call jit-define\r
@@ -198,6 +198,30 @@ CONSTANT: vm-reg 15
     [ BNE ] [ 0 B rc-relative-ppc-3 rt-xt jit-rel ] jit-conditional*\r
 ] pic-hit jit-define\r
 \r
+! Inline cache miss entry points\r
+: jit-load-return-address ( -- ) 6 MFLR ;\r
+\r
+! These are always in tail position with an existing stack\r
+! frame, and the stack. The frame setup takes this into account.\r
+: jit-inline-cache-miss ( -- )\r
+    jit-save-context\r
+    3 6 MR\r
+    4 vm-reg MR\r
+    0 5 LOAD32 "inline_cache_miss" f rc-absolute-ppc-2/2 jit-dlsym\r
+    5 MTLR\r
+    BLRL\r
+    jit-restore-context ;\r
+\r
+[ jit-load-return-address jit-inline-cache-miss ]\r
+[ 3 MTLR BLRL ]\r
+[ 3 MTCTR BCTR ]\r
+\ inline-cache-miss define-sub-primitive*\r
+\r
+[ jit-inline-cache-miss ]\r
+[ 3 MTLR BLRL ]\r
+[ 3 MTCTR BCTR ]\r
+\ inline-cache-miss-tail define-sub-primitive*\r
+\r
 ! ! ! Megamorphic caches\r
 \r
 [\r
@@ -502,35 +526,12 @@ CONSTANT: vm-reg 15
     rs-reg 3 rs-reg SUBF\r
 ] \ drop-locals define-sub-primitive\r
 \r
-! Inline cache miss entry points\r
-: jit-load-return-address ( -- ) 6 MFLR ;\r
-\r
-! These are always in tail position with an existing stack\r
-! frame, and the stack. The frame setup takes this into account.\r
-: jit-inline-cache-miss ( -- )\r
-    jit-save-context\r
-    3 6 MR\r
-    4 vm-reg MR\r
-    0 5 LOAD32 "inline_cache_miss" f rc-absolute-ppc-2/2 jit-dlsym\r
-    5 MTLR\r
-    BLRL ;\r
-\r
-[ jit-load-return-address jit-inline-cache-miss ]\r
-[ 3 MTLR BLRL ]\r
-[ 3 MTCTR BCTR ]\r
-\ inline-cache-miss define-sub-primitive*\r
-\r
-[ jit-inline-cache-miss ]\r
-[ 3 MTLR BLRL ]\r
-[ 3 MTCTR BCTR ]\r
-\ inline-cache-miss-tail define-sub-primitive*\r
-\r
 ! Overflowing fixnum arithmetic\r
 :: jit-overflow ( insn func -- )\r
-    jit-save-context\r
-    3 ds-reg -4 LWZ\r
-    4 ds-reg 0 LWZ\r
     ds-reg ds-reg 4 SUBI\r
+    jit-save-context\r
+    3 ds-reg 0 LWZ\r
+    4 ds-reg 4 LWZ\r
     0 0 LI\r
     0 MTXER\r
     6 4 3 insn call( d a s -- )\r
@@ -549,11 +550,11 @@ CONSTANT: vm-reg 15
 [ [ SUBFO. ] "overflow_fixnum_subtract" jit-overflow ] \ fixnum- define-sub-primitive\r
 \r
 [\r
+    ds-reg ds-reg 4 SUBI\r
     jit-save-context\r
     3 ds-reg 0 LWZ\r
     3 3 tag-bits get SRAWI\r
-    4 ds-reg -4 LWZ\r
-    ds-reg ds-reg 4 SUBI\r
+    4 ds-reg 4 LWZ\r
     0 0 LI\r
     0 MTXER\r
     6 3 4 MULLWO.\r