Fix PowerPC compiler backend for recent changes

diff --git a/basis/bootstrap/image/image.factor b/basis/bootstrap/image/image.factor
index 9415f191403c76068cf8067275092c404328eaa8..b3eb7646af1b89472d84d06e91d7bd6d32422da0 100644 (file)
--- a/basis/bootstrap/image/image.factor
+++ b/basis/bootstrap/image/image.factor
@@ -193,7 +193,7 @@ USERENV: jit-if 29
 USERENV: jit-epilog 30
 USERENV: jit-return 31
 USERENV: jit-profiling 32
-USERENV: jit-push-immediate 33
+USERENV: jit-push 33
 USERENV: jit-dip-word 34
 USERENV: jit-dip 35
 USERENV: jit-2dip-word 36

diff --git a/basis/cpu/ppc/bootstrap.factor b/basis/cpu/ppc/bootstrap.factor
index 753fff13c43209bae6fbfc138be9bc9187728613..40fa5c4b7876e03e84157aa909d39be7cc96bb01 100644 (file)
--- a/basis/cpu/ppc/bootstrap.factor
+++ b/basis/cpu/ppc/bootstrap.factor
@@ -21,7 +21,7 @@ CONSTANT: rs-reg 14
 : next-save ( -- n ) stack-frame bootstrap-cell - ;\r
 : xt-save ( -- n ) stack-frame 2 bootstrap-cells - ;\r
 \r
-: jit-conditional* ( test-quot true-quot -- )\r
+: jit-conditional* ( test-quot false-quot -- )\r
     [ '[ bootstrap-cell /i 1 + @ ] ] dip jit-conditional ; inline\r
 \r
 : jit-save-context ( -- )\r
@@ -53,14 +53,14 @@ CONSTANT: rs-reg 14
 [\r
     0 3 LOAD32 rc-absolute-ppc-2/2 rt-literal jit-rel\r
     3 ds-reg 4 STWU\r
-] jit-push-immediate jit-define\r
+] jit-push jit-define\r
 \r
 [\r
     jit-save-context\r
-    4 0 swap LOAD32 rc-absolute-ppc-2/2 rt-vm jit-rel\r
-    0 5 LOAD32 rc-absolute-ppc-2/2 rt-primitive jit-rel\r
-    5 MTCTR\r
-    BCTR\r
+    0 3 LOAD32 rc-absolute-ppc-2/2 rt-vm jit-rel\r
+    0 4 LOAD32 rc-absolute-ppc-2/2 rt-primitive jit-rel\r
+    4 MTLR\r
+    BLRL\r
 ] jit-primitive jit-define\r
 \r
 [ 0 BL rc-relative-ppc-3 rt-xt-pic jit-rel ] jit-word-call jit-define\r
@@ -235,7 +235,7 @@ CONSTANT: rs-reg 14
 [\r
     3 ds-reg 0 LWZ\r
     ds-reg dup 4 SUBI\r
-    4 0 swap LOAD32 0 jit-parameter rc-absolute-ppc-2/2 rt-vm jit-rel\r
+    0 4 LOAD32 0 rc-absolute-ppc-2/2 jit-vm\r
     5 3 quot-xt-offset LWZ\r
 ]\r
 [ 5 MTLR BLRL ]\r
@@ -502,35 +502,39 @@ CONSTANT: rs-reg 14
 : jit-inline-cache-miss ( -- )\r
     jit-save-context\r
     3 6 MR\r
-    4 0 LOAD32 0 rc-absolute-ppc-2/2 jit-vm\r
-    5 0 LOAD32 "inline_cache_miss" f rc-absolute-ppc-2/2 jit-dlsym ;\r
+    0 4 LOAD32 0 rc-absolute-ppc-2/2 jit-vm\r
+    0 5 LOAD32 "inline_cache_miss" f rc-absolute-ppc-2/2 jit-dlsym\r
+    5 MTLR\r
+    BLRL ;\r
 \r
 [ jit-load-return-address jit-inline-cache-miss ]\r
-[ 5 MTLR BLRL ]\r
-[ 5 MTCTR BCTR ]\r
+[ 3 MTLR BLRL ]\r
+[ 3 MTCTR BCTR ]\r
 \ inline-cache-miss define-sub-primitive*\r
 \r
 [ jit-inline-cache-miss ]\r
-[ 5 MTLR BLRL ]\r
-[ 5 MTCTR BCTR ]\r
+[ 3 MTLR BLRL ]\r
+[ 3 MTCTR BCTR ]\r
 \ inline-cache-miss-tail define-sub-primitive*\r
 \r
 ! Overflowing fixnum arithmetic\r
 :: jit-overflow ( insn func -- )\r
     jit-save-context\r
-    3 ds-reg 0 LWZ\r
-    4 ds-reg -4 LWZ\r
+    3 ds-reg -4 LWZ\r
+    4 ds-reg 0 LWZ\r
     ds-reg ds-reg 4 SUBI\r
     0 0 LI\r
     0 MTXER\r
-    6 3 4 insn call( d a s -- )\r
+    6 4 3 insn call( d a s -- )\r
     6 ds-reg 0 STW\r
     [ BNO ]\r
     [\r
        0 5 LOAD32 0 rc-absolute-ppc-2/2 jit-vm\r
        0 6 LOAD32 func f rc-absolute-ppc-2/2 jit-dlsym\r
+       6 MTLR\r
+       BLRL\r
     ]\r
-    jit-conditional ;\r
+    jit-conditional* ;\r
 \r
 [ [ ADDO. ] "overflow_fixnum_add" jit-overflow ] \ fixnum+ define-sub-primitive\r
 \r
@@ -554,7 +558,7 @@ CONSTANT: rs-reg 14
         6 MTLR\r
         BLRL\r
     ]\r
-    jit-conditional\r
+    jit-conditional*\r
 ] \ fixnum* define-sub-primitive\r
 \r
 [ "bootstrap.ppc" forget-vocab ] with-compilation-unit\r

diff --git a/basis/cpu/x86/bootstrap.factor b/basis/cpu/x86/bootstrap.factor
index db048dd31460280f876792532d2ebe2eab50627b..6eeb3d64efa0e7b779c45091f1ad5c4e81d09e36 100644 (file)
--- a/basis/cpu/x86/bootstrap.factor
+++ b/basis/cpu/x86/bootstrap.factor
@@ -28,7 +28,7 @@ big-endian off
     ds-reg bootstrap-cell ADD
     ! store literal on datastack
     ds-reg [] temp0 MOV
-] jit-push-immediate jit-define
+] jit-push jit-define
 
 [
     temp3 0 MOV rc-absolute-cell rt-here jit-rel