Add RT_INLINE_CACHE_MISS relocation type to avoid frequent dlsym lookups when compili...

diff --git a/basis/compiler/codegen/relocation/relocation.factor b/basis/compiler/codegen/relocation/relocation.factor
index e5132a75094ce558576f69fd7f12a6fcc5f957aa..f2bc0d0de7f8c2ce4c0c7ca2f879d5b86a67f324 100644 (file)
--- a/basis/compiler/codegen/relocation/relocation.factor
+++ b/basis/compiler/codegen/relocation/relocation.factor
@@ -99,6 +99,9 @@ MEMO: cached-string>symbol ( symbol -- obj ) string>symbol ;
 : rel-exception-handler ( class -- )
     rt-exception-handler add-relocation ;
 
+: rel-inline-cache-miss ( class -- )
+    rt-inline-cache-miss add-relocation ;
+
 : init-relocation ( -- )
     V{ } clone parameter-table set
     V{ } clone literal-table set

diff --git a/basis/compiler/constants/constants.factor b/basis/compiler/constants/constants.factor
index 97da3b7516842c653b6eb93cbc4178af5c1e85dc..3440b85a8054c0b14e8c2d2485317fe6b2c66ae0 100644 (file)
--- a/basis/compiler/constants/constants.factor
+++ b/basis/compiler/constants/constants.factor
@@ -69,6 +69,7 @@ CONSTANT: rt-cards-offset 10
 CONSTANT: rt-decks-offset 11
 CONSTANT: rt-exception-handler 12
 CONSTANT: rt-dlsym-toc 13
+CONSTANT: rt-inline-cache-miss 14
 
 : rc-absolute? ( n -- ? )
     ${

diff --git a/basis/cpu/x86/32/bootstrap.factor b/basis/cpu/x86/32/bootstrap.factor
index 4474e402fe1f6b3d16f76afb7d8fbc9ab083d74a..39f72de2b9e8ee1a11f3f9c1ad41d180ab02c432 100755 (executable)
--- a/basis/cpu/x86/32/bootstrap.factor
+++ b/basis/cpu/x86/32/bootstrap.factor
@@ -192,7 +192,7 @@ IN: bootstrap.x86
     jit-save-context
     ESP 4 [+] vm-reg MOV
     ESP [] pic-tail-reg MOV
-    "inline_cache_miss" jit-call
+    0 CALL rc-relative rel-inline-cache-miss
     jit-restore-context ;
 
 [ jit-load-return-address jit-inline-cache-miss ]

diff --git a/basis/cpu/x86/64/bootstrap.factor b/basis/cpu/x86/64/bootstrap.factor
index 7e6e937f9c6d79079edae60633fbde0da8c3a83e..162ed5125a0959aff37b0e09fd2347503512ae1d 100755 (executable)
--- a/basis/cpu/x86/64/bootstrap.factor
+++ b/basis/cpu/x86/64/bootstrap.factor
@@ -181,7 +181,8 @@ IN: bootstrap.x86
     jit-save-context
     arg1 RBX MOV
     arg2 vm-reg MOV
-    "inline_cache_miss" jit-call
+    RAX 0 MOV rc-absolute-cell rel-inline-cache-miss
+    RAX CALL
     jit-load-context
     jit-restore-context ;
 

diff --git a/vm/code_blocks.cpp b/vm/code_blocks.cpp
index 13a80849cff67d1ccaab0bdf542f569c97e9c0a7..d46a4a9c2c8b5d70d45496da1daa987b729a0df6 100755 (executable)
--- a/vm/code_blocks.cpp
+++ b/vm/code_blocks.cpp
@@ -269,6 +269,9 @@ void factor_vm::store_external_address(instruction_operand op)
                op.store_value(compute_dlsym_toc_address(parameters,index));
                break;
 #endif
+       case RT_INLINE_CACHE_MISS:
+               op.store_value((cell)&factor::inline_cache_miss);
+               break;
        default:
                critical_error("Bad rel type in store_external_address()",op.rel_type());
                break;

diff --git a/vm/instruction_operands.hpp b/vm/instruction_operands.hpp
index a5286d5324a8521663d0675b38e3e2369ee581e1..b5a9931b8134ba7f3a73a01b15ada2167b3840dd 100644 (file)
--- a/vm/instruction_operands.hpp
+++ b/vm/instruction_operands.hpp
@@ -32,6 +32,9 @@ enum relocation_type {
        RT_EXCEPTION_HANDLER,
        /* arg is a literal table index, holding a pair (symbol/dll) */
        RT_DLSYM_TOC,
+       /* address of inline_cache_miss function. This is a separate
+       relocation to reduce compile time and size for PICs. */
+       RT_INLINE_CACHE_MISS
 };
 
 enum relocation_class {
@@ -117,6 +120,7 @@ struct relocation_entry {
                case RT_CARDS_OFFSET:
                case RT_DECKS_OFFSET:
                case RT_EXCEPTION_HANDLER:
+               case RT_INLINE_CACHE_MISS:
                        return 0;
                default:
                        critical_error("Bad rel type in number_of_parameters()",rel_type());